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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com preliminary XRT86SH328 28-channel ds1/e1 framer/liu with ds3 mux & vt-mapper - sonet january 2007 rev. p1.0.6 general description the XRT86SH328 is an integrated vt/tu mapper with 28 port t1/e1 line interface units. the XRT86SH328 contains integrated ds1/e1/j1 framers for performance monitoring. the XRT86SH328 processes the section, line and path overhead in the sonet/sdh data-stream. the processing of path overhead bytes within the sts-1s or tug-3s include 64 bytes (of buffer) for storing the (section trace and path trace) messages. path overhead bytes can be accessed either by on-chip registers or a serial output port. each of the 28 t1 or e1 channels use an internal de- synchronizer circuit with an internal pointer leak algorithm. this removes the jitter due to mapping and pointer adjustments from the t1 or e1 signals that are de-mapped from the incoming sonet/sdh data- stream. these de-synchronizer circuits do not need any external clock references for its operation. the transmit blocks permit flexible insertion of toh and poh bytes via both hardware and software control. the receive blocks receive a sonet sts-1 signals or an sdh stm-1 signal and performs the necessary transport and path overhead processing. a prbs pattern generator and receiver is implemented within each of the 28 t1/e1 channels in order to implement and measure bit-error performance. a general purpose microprocessor interface is included for control, configuration and monitoring. features ? provides mapping of up to 28 t1 streams as asynchronous vt1.5 into an sts-1 spe or tu-11 tributary unit into an stm-1/vc-3 or tug-3 from stm-1/ vc-4 ? supports 28 t1 streams m13 multiplexed into a serial ds3 ? supports 21 e1 streams m13 multiplexed into a serial ds3 (compliant with itu-t g.747) ? 28 t1 streams m13 multiplexed into a ds3 and ds3 is asynchronously mapped into sts-1. ? 21 e1 streams m13 multiplexed into a ds3 (itu-t g.747) and ds3 is asynchronously mapped into sts-1. ? supports 21 e1 mapped as asynchronous vt2 into an sts-1 spe or tu-12 tributary units into stm-1/vc-3 or tug-3 from a stm-1/vc-4. ? supports tu cross-mapping function tu-12/vc-11/t1. ? supports mixed mapping of vt-g/vt1.5 and vt-g/vt2. ? supports mixed mapping of tug-2/tu-11 and tug-2/ tu-12 ? 28 vt1.5/tu-11 or 21 vt-2/tu-12 tributaries can be passed as transparent between sonet/sdh telecom bus on the line side and clock and data on the system side. ? supports unframed t1/e1 signals ? supports ds1/e1 performance monitoring in both egress and ingress direction ? vc-11/vc-12 tandem connection monitoring support ? complies with the category i intrinsic jitter requirements for ds1 signals being de-mapped from sonet, per telcordia gr-253-core ? complies with the "mapping jitter generation specification" for ds1 and e1 signals being de-mapped from sdh, per itu-t g.783 ? complies with the "combined jitter generation specification" for ds1 and e1 signals being de-mapped from sdh, per itu-t g.783 ? line and facility loop-backs ? each of the 28 t1/e1 channels includes a prbs generator and receiver. ? each of the 28 vt-mapper blocks are capable of generating bip-2 and rei errors upon software command (for diagnostic purposes). ? the transmit and receive ds3 framer blocks support both the m13(m23) and the c-bit parity framing formats. ? integrated 28 t1/e1/j1 shor t-haul line interface units ? ieee 1149.1 standard boundary scan ? low power: 1.8v power supply for core logic; 3.3v power supply for i/o ? general purpose microprocessor interface applications ? channelized and unchannelized ds3 applications ? t1/e1 terminals ? sonet/sdh adm
XRT86SH328 preliminary 2 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 f igure 1. b lock d iagram of the XRT86SH328 t able 1: o rdering i nformation p roduct n umber p ackage t ype o perating t emperature r ange XRT86SH328ib 568 ball bga -40c to +85c sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
preliminary XRT86SH328 3 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications f igure 2. p in out of the XRT86SH328 ( bottom view ) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak
XRT86SH328 preliminary i 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 table of contents general description ......... ................ ................ ................. .............. .............. .......... 1 features ....................................................................................................................... .......................... 1 applications ........... ................ ................ ................ ................. ................ ............. .......... ....................... 1 f igure 1. b lock d iagram of the XRT86SH328 .................................................................................................................... ...... 2 t able 1: o rdering i nformation .............................................................................................................................. ..................... 2 f igure 2. p in out of the XRT86SH328 ( bottom view ) ............................................................................................................... 3 t able of c ontents ................. ................. ................ ................ ................. .............. ........... i 1.0 register map & description for the xrt8 6sh328 28-channel ds1/e1 framer/liu with ds3 mux and vt-mapper ic - sonet applications. ................. ................ ............. ............ ........ 4 1.1 register map of the XRT86SH328 ............................................................................................. ................ 4 t able 2: o peration c ontrol r egisters .............................................................................................................................. ....... 4 t able 3: liu c ommon c ontrol r egisters .............................................................................................................................. .... 5 t able 4: r eceive sts-1/sts-3 toh p rocessor b lock r egisters ........................................................................................... 6 t able 5: r eceive sts-1/sts-3 poh p rocessor b lock r egisters ......................................................................................... 10 t able 6: r eceive sts-1/sts-3 t ransport - r eceive s ection t race m essage b uffer ......................................................... 12 t able 7: r eceive sts-1/sts-3 p ath - r eceive p ath t race m essage b uffer ........................................................................ 12 t able 8: r eceive tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) ................................................ 12 t able 9: r eceive tu-3 poh p rocessor b lock - r eceive p ath t race m essage b uffer (sdh/tug-3 a pplications o nly ) 15 t able 10: t ransmit sts-1/sts-3 toh p rocessor b lock r egisters ..................................................................................... 15 t able 11: t ransmit sts-1/sts-3 poh p rocessor b lock r egisters ..................................................................................... 17 t able 12: t ransmit sts-1/sts-3 toh p rocessor b lock - t ransmit p ath t race m essage b uffer .................................... 18 t able 13: t ransmit sts-1/sts-3 poh p rocessor b lock - t ransmit p ath t race m essage b uffer ................................... 18 t able 14: t ransmit tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) ............................................ 19 t able 15: t ransmit tu-3 poh p rocessor b lock - t ransmit p ath t race m essage b uffer ................................................. 20 t able 16: vt m apper c ontrol r egisters .............................................................................................................................. .. 20 t able 17: ds3 m apper c ontrol r egisters .............................................................................................................................. 21 t able 18: ds3 f ramer and m13 mux b lock r egisters .......................................................................................................... 22 t able 19: t1/e1 liu c hannel c ontrol r egisters ( where n ranges from 0 x 01 to 0 x 1d) ................................................... 27 t able 20: t1/e1 f ramer b lock c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 38) ................................... 28 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) ...................................... 30 t able 22: r eceive s ignaling r egister a rray r egisters ( where n ranges in value from 0 x 01 to 0 x 38) ........................... 37 t able 23: t1/e1 p erformance m onitor r egister ( where n ranges value from 0 x 01 to 0 x 38) .......................................... 39 t able 24: t1/e1 f ramer b lock i nterrupt r egisters ( where n ranges in value from 0 x 01 to 0 x 38) ................................. 39 t able 25: vt m apper r egister ( where n ranges in value from 0 x 01 to 0 x 1c) .................................................................... 41 2.0 register descriptions...................................................................................................... ............ 42 t able 26: o peration c ontrol r egister - b yte 3 (a ddress = 0 x 0000) ................................................................................... 42 2.1 operation control registers................................................................................................ .............. 43 t able 27: o peration c ontrol r egister - b yte 3 (a ddress = 0 x 0000) ................................................................................... 43 t able 28: o peration c ontrol r egister - b yte 2 (a ddress = 0 x 0001) ................................................................................... 44 t able 29: o peration c ontrol r egister - b yte 0 (a ddress = 0 x 0003) ................................................................................... 45 t able 30: d evice id v alue r egister - b yte 3 (a ddress = 0 x 0004) ......................................................................................... 45 t able 31: r evision n umber v alue r egister - b yte 2 (a ddress = 0 x 0005) ............................................................................. 46 t able 32: o peration i nterrupt s tatus r egister - b yte 0 (a ddress = 0 x 000b) .................................................................... 46 t able 33: o peration i nterrupt e nable r egister - b yte 0 (a ddress = 0 x 000f) .................................................................... 46 t able 34: o peration b lock i nterrupt s tatus r egister - b yte 1 (a ddress = 0 x 0012) ......................................................... 47 t able 35: o peration b lock i nterrupt s tatus r egister - b yte 0 (a ddress = 0 x 0013) ......................................................... 48 t able 36: o peration b lock i nterrupt e nable r egister - b yte 1 (a ddress = 0 x 0016) ......................................................... 48 t able 37: o peration b lock i nterrupt e nable r egister - b yte 0 (a ddress = 0 x 0017) ......................................................... 50 t able 38: m ode c ontrol r egister - b yte 0 (a ddress = 0 x 001b) ........................................................................................... 51 t able 39: l oop - back c ontrol r egister - b yte 0 (a ddress = 0 x 001f) ................................................................................... 51 t able 40: sts-1/sts-3 t elecom b us c ontrol r egister - b yte 3 (a ddress = 0 x 0034) ........................................................ 52 t able 41: sts-1/sts-3 t elecom b us c ontrol r egister - b yte 2 (a ddress = 0 x 0035) ........................................................ 52 t able 42: sts-3/sts-1/sts-3 t elecom b us c ontrol r egister - b yte 1 (a ddress = 0 x 0036) ............................................. 53 t able 43: sts-3/sts-1/sts-3 t elecom b us c ontrol r egister - b yte 1 (a ddress = 0 x 0036) ............................................. 55 t able 44: sts-3/sts-1/sts-3 t elecom b us c ontrol r egister - b yte 0 (a ddress = 0 x 0037) ............................................. 57 t able 45: o peration b lock - i nterface c ontrol r egister (a ddress = 0 x 003c) .................................................................. 59 t able 46: o peration g eneral p urpose i nput /o utput r egister - b yte 0 (a ddress = 0 x 0047) ............................................ 59 t able 47: o peration g eneral p urpose i nput /o utput d irection r egister 0 (a ddress = 0 x 004b) ...................................... 60 t able 48: o peration i/o c ontrol r egister (a ddress = 0 x 004f) .......................................................................................... 60 t able 49: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0050) .......... 61 t able 50: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0051) .......... 62 t able 51: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0052) .......... 62
preliminary XRT86SH328 ii rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications t able 52: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0053) .......... 63 t able 53: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0054) ....... 63 t able 54: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0055) ....... 63 t able 55: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0056) ....... 64 t able 56: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0057) ....... 64 t able 57: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 0058) ................................. 65 t able 58: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 0059) ................................ 65 t able 59: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 005a) ................................ 65 t able 60: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 005b) ................................ 66 t able 61: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005c) ................................. 66 t able 62: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005d) ................................ 66 t able 63: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005e) ................................. 67 t able 64: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005f) ................................ 67 2.2 liu common control registers ............................................................................................... ............ 67 t able 65: liu c ommon c ontrol r egister 0 (a ddress = 0 x 0100) ........................................................................................... 67 t able 66: liu c ommon c ontrol r egister 1 (a ddress = 0 x 0101) ........................................................................................... 68 t able 67: liu c ommon c ontrol r egister 2 (a ddress = 0 x 0102) ........................................................................................... 69 t able 68: liu c ommon c ontrol r egister 3 (a ddress = 0 x 0103) ........................................................................................... 69 t able 69: liu c ommon c ontrol r egister 4 (a ddress = 0 x 0104) .......................................................................................... 70 t able 70: liu c ommon c ontrol r egister 5 (a ddress = 0 x 0105) ........................................................................................... 70 t able 71: liu c ommon c ontrol r egister 6 (a ddress = 0 x 0106) ........................................................................................... 70 2.3 receive sts-1/sts-3 toh processo r block registers ......... .............. .............. ............ ........... ..... 71 f igure 3. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the r eceive sts-1/sts-3 toh p rocessor b lock highlighted ............................................................................................................................... ....................... 71 t able 72: r eceive sts-1/sts-3 t ransport c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0202) .............................. 71 t able 73: r eceive sts-1/sts-3 t ransport c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0203) ............................. 72 t able 74: r eceive sts-1/sts-3 t ransport s tatus r egister - b yte 1 (a ddress l ocation = 0 x 0206) ................................. 73 t able 75: r eceive sts-1/sts-3 t ransport s tatus r egister - b yte 0 (a ddress l ocation = 0 x 0207) ............................... 74 t able 76: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 2 (a ddress l ocation = 0 x 0209) ................ 76 t able 77: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 1 (a ddress l ocation = 0 x 020a) ............... 77 t able 78: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 0 (a ddress l ocation = 0 x 020b) ............... 79 t able 79: r eceive sts-1/sts-3 t ransport i nterrupt e nable r egister - b yte 2 (a ddress l ocation = 0 x 020d) ............... 80 t able 80: r eceive sts-1/sts-3 t ransport i nterrupt e nable r egister - b yte 1 (a ddress l ocation = 0 x 020e) ............... 81 t able 81: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 0 (a ddress l ocation = 0 x 020f) ............... 83 t able 82: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 3 (a ddress l ocation = 0 x 0210) ...... 84 t able 83: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 2 (a ddress l ocation = 0 x 0211) ...... 84 t able 84: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 0212) ...... 85 t able 85: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 0213) ...... 85 t able 86: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 3 (a ddress l ocation = 0 x 0214) ...... 86 t able 87: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 2 (a ddress l ocation = 0 x 0215) ...... 86 t able 88: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 0216) ...... 86 t able 89: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 0217) ...... 87 t able 90: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 3 (a ddress l ocation = 0 x 0218) .......... 87 t able 91: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 2 (a ddress l ocation = 0 x 0219) ........... 88 t able 92: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 1 (a ddress l ocation = 0 x 021a) ........... 88 t able 93: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 0 (a ddress l ocation = 0 x 021b) ........... 88 t able 94: r eceive sts-1/sts-3 t ransport - r eceived k1 b yte v alue r egister (a ddress l ocation = 0 x 021f) ................ 89 t able 95: r eceive sts-1/sts-3 t ransport - r eceived k2 b yte v alue r egister (a ddress l ocation = 0 x 0223) ................. 89 t able 96: r eceive sts-1/sts-3 t ransport - r eceived s1 b yte v alue r egister (a ddress l ocation = 0 x 0227) ................. 89 t able 97: r eceive sts-1/sts-3 t ransport - r eceive i n -s ync t hreshold r egister (a ddress = 0 x 022b) .......................... 90 t able 98: r eceive sts-1/sts-3 t ransport - los t hreshold v alue - msb (a ddress l ocation = 0 x 022e) ......................... 90 t able 99: r eceive sts-1/sts-3 t ransport - los t hreshold v alue - lsb (a ddress l ocation = 0 x 022f) .......................... 90 t able 100: r eceive sts-1/sts-3 t ransport - r eceive sf set m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 0231) 90 t able 101: r eceive sts-1/sts-3 t ransport - r eceive sf set m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 0232) 91 t able 102: r eceive sts-1/sts-3 t ransport - r eceive sf set m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 0233) 91 t able 103: r eceive sts-1/sts-3 t ransport - r eceive sf set t hreshold - b yte 1 (a ddress l ocation = 0 x 0236) ........... 92 t able 104: r eceive sts-1/sts-3 t ransport - r eceive sf set t hreshold - b yte 0 (a ddress l ocation = 0 x 0237) ........... 92 t able 105: r eceive sts-1/sts-3 t ransport - r eceive sf clear t hreshold - b yte 1 (a ddress l ocation = 0 x 023a) ...... 92 t able 106: r eceive sts-1/sts-3 t ransport - r eceive sf clear t hreshold - b yte 0 (a ddress l ocation = 0 x 023b) ...... 93 t able 107: r eceive sts-1/sts-3 t ransport - r eceive sd s et m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 023d) 93 t able 108: r eceive sts-1/sts-3 t ransport - r eceive sd s et m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 023e) 94 t able 109: r eceive sts-1/sts-3 t ransport - r eceive sd s et m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 023f) 94 t able 110: r eceive sts-1/sts-3 t ransport - r eceive sd set t hreshold - b yte 1 (a ddress l ocation = 0 x 0242) ........... 95 t able 111: r eceive sts-1/sts-3 t ransport - r eceive sd set t hreshold - b yte 0 (a ddress l ocation = 0 x 0243) ........... 95 t able 112: r eceive sts-1/sts-3 t ransport - r eceive sd clear t hreshold - b yte 1 (a ddress l ocation = 0 x 0246) ...... 95 t able 113: r eceive sts-1/sts-3 t ransport - r eceive sd clear t hreshold - b yte 1 (a ddress l ocation = 0 x 0247) ...... 96
XRT86SH328 preliminary iii 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 t able 114: r eceive sts-1/sts-3 t ransport - f orce sef d efect c ondition r egister (a ddress l ocation = 0 x 024b) ...... 96 t able 115: r eceive sts-1/sts-3 t ransport - r eceive s ection t race m essage b uffer c ontrol r egister (a ddress l ocation = 0 x 024f) ......................................................................................................................... .............................................. 96 t able 116: r eceive sts-1/sts-3 t ransport - r eceive sd b urst e rror t olerance - b yte 1 (a ddress l ocation = 0 x 0252) 97 t able 117: r eceive sts-1/sts-3 t ransport - r eceive sd b urst e rror t olerance - b yte 0 (a ddress l ocation = 0 x 0253) 98 t able 118: r eceive sts-1/sts-3 t ransport - r eceive sf b urst e rror t olerance - b yte 1 (a ddress l ocation = 0 x 0256) 98 t able 119: r eceive sts-1/sts-3 t ransport - r eceive sf b urst e rror t olerance - b yte 0 (a ddress l ocation = 0 x 0257) 99 t able 120: r eceive sts-1/sts-3 t ransport - r eceive sd c lear m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 0259) 99 t able 121: r eceive sts-1/sts-3 t ransport - r eceive sd c lear m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 025a) 99 t able 122: r eceive sts-1/sts-3 t ransport - r eceive sd c lear m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 025b) 100 t able 123: r eceive sts-1/sts-3 t ransport - r eceive sf c lear m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 025d) 100 t able 124: r eceive sts-1/sts-3 t ransport - r eceive sf c lear m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 025e) . 101 t able 125: r eceive sts-1/sts-3 t ransport - r eceive sf c lear m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 025f) 101 t able 126: r eceive sts-1/sts-3 t ransport - a uto ais c ontrol r egister (a ddress l ocation = 0 x 0263) ...................... 102 t able 127: r eceive sts-1/sts-3 t ransport - a uto ais ( in d ownstream t1/e1 s ) c ontrol r egister (a ddress l ocation = 0 x 026b) ......................................................................................................................... ............................................ 104 t able 128: r eceive sts-1/sts-3 t ransport - a1, a2 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 026e) 105 t able 129: r eceive sts-1/sts-3 t ransport - a1, a2 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 026f) 105 2.4 receive sts-1 poh processor bl ock registers ......................................................................... 105 f igure 4. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the r eceive sts-1 poh p rocessor b lock highlighted ............................................................................................................................... ................................ 106 t able 130: r eceive sts-1 p ath - r eceive c ontrol r egister - b yte 2 (a ddress = 0 x 0281) ............................................... 106 t able 131: r eceive sts-1 p ath - r eceive c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0283) ................................ 107 t able 132: r eceive sts-1 p ath - c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0286) .............................................. 108 t able 133: r eceive sts-1 p ath - sonet r eceive poh s tatus - b yte 0 (a ddress l ocation = 0 x 0287) ............................ 108 t able 134: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt s tatus - b yte 2 (a ddress l ocation = 0 x 0289) .......... 110 t able 135: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt s tatus - b yte 1 (a ddress l ocation = 0 x 028a) .......... 111 t able 136: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt s tatus - b yte 0 (a ddress l ocation = 0 x 028b) .......... 113 t able 137: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt e nable - b yte 2 (a ddress l ocation = 0 x 028d) ......... 115 t able 138: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt e nable - b yte 1 (a ddress l ocation = 0 x 028e) .......... 116 t able 139: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt e nable - b yte 0 (a ddress l ocation = 0 x 028f) .......... 118 t able 140: r eceive sts-1 p ath - sonet r eceive rdi-p r egister (a ddress l ocation = 0 x 0293) ..................................... 119 t able 141: r eceive sts-1 p ath - r eceived p ath l abel v alue (a ddress l ocation = 0 x 0296) ............................................. 120 t able 142: r eceive sts-1 p ath - e xpected p ath l abel v alue (a ddress l ocation = 0 x 0297) ............................................ 120 t able 143: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 3 (a ddress l ocation = 0 x 0298) ...................... 120 t able 144: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 2 (a ddress l ocation = 0 x 0299) ...................... 121 t able 145: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 029a) ...................... 121 t able 146: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 029b) ...................... 121 t able 147: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 3 (a ddress l ocation = 0 x 029c) ........................... 122 t able 148: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 2 (a ddress l ocation = 0 x 029d) ........................... 122 t able 149: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 1 (a ddress l ocation = 0 x 029e) ........................... 122 t able 150: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 0 (a ddress l ocation = 0 x 029f) ............................ 123 t able 151: r eceive sts-1 p ath - r eceive p ath t race m essage b uffer c ontrol r egister (a ddress l ocation = 0 x 02a3) 123 t able 152: r eceive sts-1 p ath - p ointer v alue - b yte 1 (a ddress l ocation = 0 x 02a6) .................................................... 124 t able 153: r eceive sts-1 p ath - p ointer v alue - b yte 0 (a ddress l ocation = 0 x 02a7) .................................................... 125 t able 154: r eceive sts-1 p ath - r eceive a uto ais - c2 b yte v alue r egister (a ddress = 0 x 02b9) ................................ 125 t able 155: r eceive sts-1 p ath - r eceive a uto ais - c2 b yte c ontrol r egister (a ddress = 0 x 02ba) ........................... 125 t able 156: r eceive sts-1 p ath - auto ais c ontrol r egister (a ddress l ocation = 0 x 02bb) ......................................... 126 t able 157: r eceive sts-1 p ath - sonet r eceive a uto a larm r egister - b yte 0 (a ddress l ocation = 0 x 02c3) ............ 128 t able 158: r eceive sts-1 p ath - r eceive n egative p ointer a djustment c ount r egister - b yte 1 (a ddress = 0 x 02c4) 129 t able 159: r eceive sts-1 p ath - r eceive n egative p ointer a djustment c ount r egister - b yte 0 (a ddress = 0 x 02c5) 129 t able 160: r eceive sts-1 p ath - r eceive p ositive p ointer a djustment c ount r egister - b yte 1 (a ddress = 0 x 02c6) 130 t able 161: r eceive sts-1 p ath - r eceive p ositive p ointer a djustment c ount r egister - b yte 0 (a ddress = 0 x 02c7) 130 t able 162: r eceive sts-1 p ath - r eceive j1 b yte c apture r egister (a ddress l ocation = 0 x 02d3) ................................ 130 t able 163: r eceive sts-1 p ath - r eceive b3 b yte c apture r egister (a ddress l ocation = 0 x 02d7) ............................... 130 t able 164: r eceive sts-1 p ath - r eceive c2 b yte c apture r egister (a ddress l ocation = 0 x 02db) .............................. 131 t able 165: r eceive sts-1 p ath - r eceive g1 b yte c apture r egister (a ddress l ocation = 0 x 02df) .............................. 131 t able 166: r eceive sts-1 p ath - r eceive f2 b yte c apture r egister (a ddress l ocation =0 x 02e3) ................................ 131 t able 167: r eceive sts-1 p ath - r eceive h4 b yte c apture r egister (a ddress l ocation = 0 x 02e7) ............................... 131 t able 168: r eceive sts-1 p ath - r eceive z3 b yte c apture r egister (a ddress l ocation = 0 x 02eb) ............................... 132 t able 169: r eceive sts-1 p ath - r eceive z4 (k3) b yte c apture r egister (a ddress l ocation = 0 x 02ef) ....................... 132 t able 170: r eceive sts-1 p ath - r eceive z5 b yte c apture r egister (a ddress l ocation = 0 x 02f3) ................................ 132 2.5 receive tug-3 mapper/vc-4 poh processor bl ock registers (sdh/tug- 3 applications only)
preliminary XRT86SH328 iv rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 133 f igure 5. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the r eceive tug-3 m apper /vc-4 poh p rocessor block " highlighted " ..................................................................................................................... 133 2.6 transmit sts-1/sts-3 toh proc essor block registers ...... .............. .............. ............ ........... ... 133 f igure 6. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the t ransmit sts-1/sts-3 toh p roces - sor b lock highlighted ............................................................................................................................... ............. 134 t able 171: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 3 (a ddress l ocation = 0 x 0700) ...... 134 t able 172: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 2 (a ddress l ocation = 0 x 0701) ..... 135 t able 173: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0702) ...... 135 t able 174: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0703) ...... 136 t able 175: t ransmit sts-1/sts-3 t ransport - t ransmit a1 b yte e rror r egister (a ddress l ocation = 0 x 0717) ......... 138 t able 176: t ransmit sts-1/sts-3 t ransport - t ransmit a2 b yte e rror r egister (a ddress l ocation = 0 x 071f) ......... 138 t able 177: t ransmit sts-1/sts-3 t ransport - t ransmit b1 b yte e rror m ask r egister (a ddress l ocation = 0 x 0723) 138 t able 178: t ransmit sts-1/sts-3 t ransport - t ransmit b2 b yte e rror m ask r egister (a ddress l ocation = 0 x 0727) 139 t able 179: t ransmit sts-1/sts-3 t ransport - t ransmit b2 b it e rror m ask r egister (a ddress l ocation = 0 x 072b) ... 139 t able 180: t ransmit sts-1/sts-3 t ransport - k2 b yte v alue r egister - b yte 1 (a ddress l ocation = 0 x 072e) ............ 140 t able 181: t ransmit sts-1/sts-3 t ransport - k1 b yte v alue r egister - b yte 1 (a ddress l ocation = 0 x 072f) ............ 140 t able 182: t ransmit sts-1/sts-3 t ransport - rdi-l c ontrol r egister (a ddress l ocation = 0 x 0733) .......................... 140 t able 183: t ransmit sts-1/sts-3 t ransport - m0m1 b yte v alue r egister (a ddress l ocation = 0 x 0737) ..................... 141 t able 184: t ransmit sts-1/sts-3 t ransport - s1 b yte v alue r egister (a ddress l ocation = 0 x 073b) .......................... 141 t able 185: t ransmit sts-1/sts-3 t ransport - f1 b yte v alue r egister (a ddress l ocation = 0 x 073f) .......................... 142 t able 186: t ransmit sts-1/sts-3 t ransport - e1 b yte v alue r egister (a ddress l ocation = 0 x 0743) .......................... 142 t able 187: t ransmit sts-1/sts-3 t ransport - e2 b yte v alue r egister (a ddress l ocation = 0 x 0747) .......................... 142 t able 188: t ransmit sts-1/sts-3 t ransport - j0 b yte v alue r egister (a ddress l ocation = 0 x 074b) ........................... 143 t able 189: t ransmit sts-1/sts-3 t ransport - t ransmitter j0 b yte c ontrol r egister (a ddress l ocation = 0 x 074f) . 143 2.7 transmit sts-1/sts-3 poh processor block registers ............................................................ 145 f igure 7. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the t ransmit sts-1/sts-3 poh p roces - sor b lock highlighted ............................................................................................................................... ............. 145 t able 190: t ransmit sts-1/sts-3 p ath - t ransmit c ontrol r egister - b yte 2 (a ddress l ocation = 0 x 0781) ............... 145 t able 191: t ransmit sts-1/sts-3 p ath - t ransmit c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0782) ............... 146 t able 192: t ransmit sts-1/sts-3 p ath - t ransmit c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0783) ................ 147 t able 193: t ransmit sts-1/sts-3 p ath - t ransmitter j1 b yte v alue r egister (a ddress l ocation = 0 x 0793) ................ 148 t able 194: t ransmit sts-1/sts-3 p ath - t ransmit b3 b yte e rror m ask r egister (a ddress l ocation = 0 x 0797) .......... 148 t able 195: t ransmit sts-1/sts-3 p ath - t ransmit c2 b yte v alue r egister (a ddress l ocation = 0 x 079b) .................... 149 t able 196: t ransmit sts-1/sts-3 p ath - t ransmit g1 b yte v alue r egister (a ddress l ocation = 0 x 079f) .................... 149 t able 197: t ransmit sts-1/sts-3 p ath - t ransmit f2 b yte v alue r egister (a ddress l ocation = 0 x 07a3) ..................... 149 t able 198: t ransmit sts-1/sts-3 p ath - t ransmit h4 b yte v alue r egister (a ddress l ocation = 0 x 07a7) .................... 150 t able 199: t ransmit sts-1/sts-3 p ath - t ransmit z3 b yte v alue r egister (a ddress l ocation = 0 x 07ab) .................... 150 t able 200: t ransmit sts-1/sts-3 p ath - t ransmit z4 b yte v alue r egister (a ddress l ocation = 0 x n9af) .................... 150 t able 201: t ransmit sts-1/sts-3 p ath - t ransmit z5 b yte v alue r egister (a ddress l ocation = 0 x 07b3) ..................... 151 t able 202: t ransmit sts-1/sts-3 p ath - t ransmit p ath c ontrol r egister (a ddress l ocation = 0 x 07b7) ..................... 151 t able 203: t ransmit sts-1/sts-3 p ath - sonet p ath j1 c ontrol r egister (a ddress l ocation = 0 x 07bb) .................. 153 t able 204: t ransmit sts-1/sts-3 p ath - t ransmit a rbitrary h1 p ointer r egister (a ddress l ocation = 0 x 07bf) ........ 153 t able 205: t ransmit sts-1/sts-3 p ath - t ransmit a rbitrary h2 p ointer r egister (a ddress l ocation = 0 x 07c3) ........ 154 t able 206: t ransmit sts-1/sts-3 p ath - t ransmit c urrent p ointer b yte r egister - b yte 1 (a ddress l ocation = 0 x 07c6) 154 t able 207: t ransmit sts-1/sts-3 p ath - t ransmit c urrent p ointer b yte r egister - b yte 0 (a ddress l ocation = 0 x 07c7) 154 t able 208: t ransmit sts-1/sts-3 p ath - rdi-p c ontrol r egister - b yte 2 (a ddress l ocation = 0 x 07c9) ..................... 155 t able 209: t ransmit sts-1/sts-3 p ath - rdi-p c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 07ca) ..................... 155 t able 210: t ransmit sts-1/sts-3 p ath - rdi-p c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 07cb) ..................... 156 t able 211: t ransmit sts-1/sts-3 p ath - s erial p ort c ontrol r egister (a ddress l ocation = 0 x 07cf) ......................... 157 t able 212: t ransmit sts-1/sts-3 p ath - t ransmit n egative p ointer a djustment c ount r egister - b yte 1 (a ddress l oca - tion = 0 x 07d0) ......................................................................................................................... .................................. 157 t able 213: t ransmit sts-1/sts-3 p ath - t ransmit n egative p ointer a djustment c ount r egister - b yte 0 (a ddress l oca - tion = 0 x 07d1) ......................................................................................................................... .................................. 158 t able 214: t ransmit sts-1/sts-3 p ath - t ransmit p ositive p ointer a djustment c ount r egister - b yte 1 (a ddress l ocation = 0 x 07d2) ......................................................................................................................... ............................................ 158 t able 215: t ransmit sts-1/sts-3 p ath - t ransmit p ositive p ointer a djustment c ount r egister - b yte 1 (a ddress l ocation = 0 x 07d3) ......................................................................................................................... ............................................ 158 2.8 transmit tug-3 mapper/vc- 4 poh processor block register s (sdh/tug-3 applications only).......................................................................................................................... .................................. 158 f igure 8. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the t ransmit tug-3 m apper /vc- 4 poh p rocessor block " highlighted " .................................................................................................................. 159 2.9 global vt mapper block control registers .. .............. .............. .............. .............. .............. ...... 159 t able 216: g lobal c ontrol - vt-m apper b lock - vt m apper b lock c ontrol r egister (a ddress = 0 x 0c03) ................. 159
XRT86SH328 preliminary v 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 f igure 9. i llustration of the f unctional b lock d iagram of the XRT86SH328 with the vt-m apper sonet/sdh l oop - back path depicted ............................................................................................................................... ............................ 161 t able 217: g lobal c ontrol - vt-m apper b lock - t est p attern c ontrol r egister - b yte 1 (a ddress = 0 x 0c0e) ......... 161 t able 218: g lobal vt-m apper b lock - t est p attern c ontrol r egister - b yte 0 (a ddress = 0 x 0c0f) ........................... 162 t able 219: g lobal c ontrol - vt-m apper b lock - t est p attern d rop r egister - b yte 1 (a ddress = 0 x 0c12) ............... 163 t able 220: g lobal c ontrol - vt-m apper b lock - t est p attern d rop r egister - b yte 0 (a ddress = 0 x 0c13) ............... 165 t able 221: g lobal c ontrol - vt-m apper - t est p attern d etector e rror c ount r egister - u pper b yte (a ddress = 0 x 0c16) 166 t able 222: g lobal c ontrol - vt-m apper - t est p attern d etector e rror c ount r egister - l ower b yte (a ddress = 0 x 0c17) 167 t able 223: g lobal c ontrol - vt-m apper - t ransmit t ributary s ize s elect r egister (a ddress = 0 x 0c1a) ................... 167 t able 224: g lobal c ontrol - vt-m apper - t ransmit t ributary s ize s elect r egister (a ddress = 0 x 0c1b) ................... 168 t able 225: g lobal c ontrol - vt-m apper - r eceive t ributary s ize s elect r egister (a ddress = 0 x 0c1e) ..................... 170 t able 226: g lobal c ontrol - vt-m apper - r eceive t ributary s ize s elect r egister (a ddress = 0 x 0c1f) ..................... 171 2.10 ds3 mapper control registers.... .............. .............. .............. .............. ........... ........... ............ .......... 172 t able 227: ds3 m apper b lock - c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0d02) .............................................. 172 t able 228: ds3 m apper b lock - c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0d03) .............................................. 173 t able 229: ds3 m apper b lock - r eceive s tatus r egister - b yte 1 (a ddress l ocation = 0 x 0d06) .................................. 173 t able 230: ds3 m apper b lock - r eceive s tatus r egister - b yte 0 (a ddress l ocation = 0 x 0d07) .................................. 174 t able 231: ds3 m apper b lock - r eceive m apper i nterrupt s tatus r egister - b yte 0 (a ddress = 0 x 0d0b) ................... 175 t able 232: ds3 m apper b lock - r eceive m apper i nterrupt e nable r egister - b yte 0 (a ddress = 0 x 0d0e) ................... 176 t able 233: ds3 m apper b lock - p ointer j ustification s tatus r egister - b yte 2 (a ddress = 0 x 0d21) ........................... 176 t able 234: ds3 m apper b lock - p ointer j ustification s tatus r egister - b yte 1 (a ddress = 0 x 0d22) ........................... 177 t able 235: ds3 m apper b lock - p ointer j ustification s tatus r egister - b yte 0 (a ddress = 0 x 0d23) ........................... 177 t able 236: ds3 m apper b lock - p ointer j ustification j itter c ontrol r egister - b yte 1 (a ddress = 0 x 0d26) .............. 177 t able 237: ds3 m apper b lock - p ointer j ustification j itter c ontrol r egister - b yte 0 (a ddress = 0 x 0d27) .............. 177 2.11 ds3 framer and m13 mux block registers ................................................................................... 177 f igure 10. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the f unctional b locks ( which are con - trolled / monitored via the ds3 f ramer and m13 mux b lock registers ) highlighted . ..................................... 178 t able 238: ds3 f ramer b lock o perating m ode r egister (a ddress = 0 x 0e00) ................................................................. 178 t able 239: ds3 f ramer b lock - i/o c ontrol r egister (a ddress = 0 x 0e01) ...................................................................... 179 t able 240: ds3 f ramer b lock - b lock i nterrupt e nable r egister (a ddress = 0 x 0e04) .................................................. 180 t able 241: ds3 f ramer b lock - b lock i nterrupt s tatus r egister (a ddress = 0 x 0e05) .................................................. 181 t able 242: ds3 f ramer b lock - m23 c onfiguration r egister (a ddress = 0 x 0e07) .......................................................... 182 f igure 11. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever it has been configured to op - erate in the m13 l ocal l oop - back m ode .............................................................................................................. 183 t able 243: ds3 f ramer b lock - m23 t ransmit ds2 ais c ommand r egister (a ddress = 0 x 0e08) .................................... 184 f igure 12. a n illustration of the XRT86SH328, whenever the m12 mux has been configured to transmit the ds2 ais indi - cator towards both the m23 mux and the t ransmit ds3 f ramer block .......................................................... 184 t able 244: ds3 f ramer b lock - m23 - ds2 l oop - back r equest r egister (a ddress = 0 x 0e09) ........................................ 185 t able 245: ds3 f ramer b lock - m23 l oop - back a ctivation r egister (a ddress = 0 x 0e0a) .............................................. 186 f igure 13. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever a given ds2 c hannel has been configured to operate in the r emote ds2 l oop - back m ode .............................................................................. 186 t able 246: ds3 f ramer b lock - m23 mux f orce r eceive ds2 ais c ommand r egisters (a ddress = 0 x 0e0b) ............... 187 f igure 14. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever the m23 d e -mux has been con - figured to transmit the ds2 ais indicator in the e gress d irection of ds2 c hannel 0 .................................. 188 t able 247: ds3 f ramer and m13 mux b lock - ds3 t est r egister (a ddress = 0 x 0e0c) .................................................. 189 t able 248: ds3 f ramer and m13 mux b lock - ds3 t est r egister # 2 (a ddress = 0 x 0e0e) ............................................. 189 t able 249: ds3 f ramer b lock - r eceive ds3 c onfiguration & s tatus r egister (a ddress = 0 x 0e10) ............................ 190 t able 250: ds3 f ramer b lock - r eceive ds3 s tatus r egister (a ddress = 0 x 0e11) ......................................................... 191 t able 251: ds3 f ramer b lock - r eceive ds3 i nterrupt e nable r egister (a ddress = 0 x 0e12) ....................................... 192 t able 252: ds3 f ramer b lock - r eceive ds3 i nterrupt s tatus ........................................ r egister (a ddress = 0 x 0e13) 194 t able 253: ds3 f ramer b lock - r eceive ds3 s ync d etect r egister (a ddress = 0 x 0e14) ............................................... 195 t able 254: ds3 f ramer b lock - r eceive ds3 feac r egister (a ddress = 0 x 0e16) .......................................................... 195 t able 255: ds3 f ramer b lock - r eceive ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 0e17) ............... 196 t able 256: ds3 f ramer b lock - r eceive lapd c ontrol r egister (a ddress = 0 x 0e18) .................................................... 197 t able 257: ds3 f ramer b lock - r eceive ds3 lapd s tatus r egister (a ddress = 0 x 0e19) .............................................. 198 t able 258: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 1 (a ddress = 0 x 0e1a) .......................... 199 t able 259: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 2 (a ddress = 0 x 0e1b) .......................... 200 t able 260: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 3 (a ddress = 0 x 0e1c) ......................... 200 t able 261: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 4 (a ddress = 0 x 0e1d) .......................... 200 t able 262: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 5 (a ddress = 0 x 0e1e) .......................... 201 t able 263: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 6 (a ddress = 0 x 0e1f) ........................... 201 t able 264: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 7 (a ddress = 0 x 0e20) ........................... 201 t able 265: ds3 f ramer b lock - m12 d e -mux f orce ds1/e1 ais r egister - ds2 c hannel # 1 (a ddress = 0 x 0e21) ...... 201 f igure 15. a n i llustration of the f unctional b lock diagram of the XRT86SH328, whenever a given m12 d e -mux block has
preliminary XRT86SH328 vi rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications been configured to transmit the ds1/e1 ais indicator ( within a given ds1/e1 signal ) in the e gress d irection 202 t able 266: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 1 (a ddress = 0 x 0e22) .............................................. 203 t able 267: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 2 (a ddress = 0 x 0e23) .............................................. 203 t able 268: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 3 (a ddress = 0 x 0e24) .............................................. 203 t able 269: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 4 (a ddress = 0 x 0e25) .............................................. 204 t able 270: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 5 (a ddress = 0 x 0e26) .............................................. 204 t able 271: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 6 (a ddress = 0 x 0e27) .............................................. 204 t able 272: ds3 f ramer b lock - m12 l oop - back r egister - 1 (a ddress = 0 x 0e28) ............................................................ 205 f igure 16. i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever it has been configured to operate in the m12 r emote l oop - back m ode ...................................................................................................................... 205 t able 273: ds3 f ramer b lock - m12 l oop - back r egister - 2 (a ddress = 0 x 0e29) ............................................................ 206 t able 274: ds3 f ramer b lock - m12 l oop - back r egister - 3 (a ddress = 0 x 0e2a) ............................................................ 206 t able 275: ds3 f ramer b lock - m12 l oop - back r egister - 4 (a ddress = 0 x 0e2b) ............................................................ 207 t able 276: ds3 f ramer b lock - m12 l oop - back r egister - 5 (a ddress = 0 x 0e2c) ............................................................ 207 t able 277: ds3 f ramer b lock - m12 l oop - back r egister - 6 (a ddress = 0 x 0e2d) ............................................................ 207 t able 278: ds3 f ramer b lock - m12 l oop - back r egister - 7 (a ddress = 0 x 0e2e) ............................................................ 207 t able 279: ds3 f ramer b lock - t ransmit ds3 c onfiguration r egister (a ddress = 0 x 0e30) .......................................... 208 t able 280: ds3 f ramer b lock - t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 0e31) ............... 209 t able 281: ds3 f ramer b lock - t ransmit ds3 feac r egister (a ddress = 0 x 0e32) ......................................................... 210 t able 282: ds3 f ramer b lock - t ransmit ds3 lapd c onfiguration r egister (a ddress = 0 x 0e33) ................................ 211 t able 283: ds3 f ramer b lock - t ransmit ds3 lapd s tatus /i nterrupt r egister (a ddress = 0 x 0e34) ........................... 212 t able 284: ds3 f ramer b lock - t ransmit ds3 m-b it m ask r egister (a ddress = 0 x 0e35) ................................................ 212 t able 285: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egisters # 1 (a ddress = 0 x 0e36) ......................................... 213 t able 286: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egister # 2 (a ddress = 0 x 0e37) ........................................... 214 t able 287: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egister # 3 (a ddress = 0 x 0e38) ........................................... 215 t able 288: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egister # 4 (a ddress = 0 x 0e39) ........................................... 215 t able 289: ds3 f ramer b lock - m12 ds2 # 1 f ramer c onfiguration r egister (a ddress = 0 x 0e3a) .............................. 216 t able 290: ds3 f ramer b lock - m12 ds2 # 2 f ramer c onfiguration r egister (a ddress = 0 x 0e3b) .............................. 217 t able 291: ds3 f ramer b lock - m12 ds2 # 3 f ramer c onfiguration r egister (a ddress = 0 x 0e3c) .............................. 218 t able 292: ds3 f ramer b lock - m12 ds2 # 4 f ramer c onfiguration r egister (a ddress = 0 x 0e3d) .............................. 218 t able 293: ds3 f ramer b lock - m12 ds2 # 5 f ramer c onfiguration r egister (a ddress = 0 x 0e3e) .............................. 218 t able 294: ds3 f ramer b lock - m12 ds2 # 6 f ramer c onfiguration r egister (a ddress = 0 x 0e3f) .............................. 219 t able 295: ds3 f ramer b lock - m12 ds2 # 7 f ramer c onfiguration r egister (a ddress = 0 x 0e40) ............................... 219 t able 296: ds3 f ramer b lock - t ransmit ds3 p attern r egister (a ddress = 0 x 0e4c) .................................................... 219 t able 297: ds3 f ramer b lock - a uto t1/e1 ais upon ds3 d efect c ondition r egister (a ddress = 0 x 0e4d) ................ 220 t able 298: ds3 f ramer b lock - pmon e xcessive z ero (exz) e vent c ount r egister - msb (a ddress = 0 x 0e4e) ........ 221 t able 299: ds3 f ramer b lock - pmon e xcessive z ero (exz) e vent c ount r egister - lsb (a ddress = 0 x 0e4f) ......... 222 t able 300: ds3 f ramer b lock - pmon l ine c ode v iolation (lcv) e vent c ount r egister - msb (a ddress = 0 x 0e50) . 222 t able 301: ds3 f ramer b lock - pmon l ine c ode v iolation (lcv) e vent c ount r egister - lsb (a ddress = 0 x 0e51) .. 222 t able 302: ds3 f ramer b lock - pmon f raming b it e rror c ount r egister - msb (a ddress = 0 x 0e52) ......................... 222 t able 303: ds3 f ramer b lock - pmon f raming b it e rror c ount r egister - lsb (a ddress = 0 x 0e53) .......................... 223 t able 304: ds3 f ramer b lock - pmon p-b it e rror c ount r egister - msb (a ddress = 0 x 0e54) .................................... 223 t able 305: ds3 f ramer b lock - pmon p-b it e rror c ount r egister - lsb (a ddress = 0 x 0e55) ..................................... 223 t able 306: ds3 f ramer b lock - pmon febe e vent c ount r egister - msb (a ddress = 0 x 0e56) .................................... 224 t able 307: ds3 f ramer b lock - pmon febe e vent c ount r egister - lsb (a ddress = 0 x 0e57) ..................................... 224 t able 308: ds3 f ramer b lock - cp-b it e rror c ount r egister - msb (a ddress = 0 x 0e58) ............................................. 224 t able 309: ds3 f ramer b lock - cp-b it e rror c ount r egister - lsb (a ddress = 0 x 0e59) .............................................. 224 t able 310: ds3 f ramer b lock - pmon ds2 # 1 f raming b it e rror c ount r egister (a ddress = 0 x 0e5a) ..................... 225 t able 311: ds3 f ramer b lock - pmon ds2 # 2 f raming b it e rror c ount r egister (a ddress = 0 x 0e5b) ..................... 225 t able 312: ds3 f ramer b lock - pmon ds2 # 3 f raming b it e rror c ount r egister (a ddress = 0 x 0e5c) ..................... 225 t able 313: ds3 f ramer b lock - pmon ds2 # 4 f raming b it e rror c ount r egister (a ddress = 0 x 0e5d) ..................... 225 t able 314: ds3 f ramer b lock - pmon ds2 # 5 f raming b it e rror c ount r egister (a ddress = 0 x 0e5e) ..................... 226 t able 315: ds3 f ramer b lock - pmon ds2 # 6 f raming b it e rror c ount r egister (a ddress = 0 x 0e5f) ..................... 226 t able 316: ds3 f ramer b lock - pmon ds2 # 7 f raming b it e rror c ount r egister (a ddress = 0 x 0e60) ...................... 226 t able 317: ds3 f ramer b lock - pmon g.747 # 1 p arity b it e rror c ount r egister (a ddress = 0 x 0e61) ...................... 226 t able 318: ds3 f ramer b lock - pmon g.747 # 2 p arity b it e rror c ount r egister (a ddress = 0 x 0e62) ...................... 226 t able 319: ds3 f ramer b lock - pmon g.747 # 3 p arity b it e rror c ount r egister (a ddress = 0 x 0e63) ...................... 227 t able 320: ds3 f ramer b lock - pmon g.747 # 4 p arity b it e rror c ount r egister (a ddress = 0 x 0e64) ...................... 227 t able 321: ds3 f ramer b lock - pmon g.747 # 5 p arity b it e rror c ount r egister (a ddress = 0 x 0e65) ...................... 227 t able 322: ds3 f ramer b lock - pmon g.747 # 6 p arity b it e rror c ount r egister (a ddress = 0 x 0e66) ...................... 227 t able 323: ds3 f ramer b lock - pmon g.747 # 7 p arity b it e rror c ount r egister (a ddress = 0 x 0e67) ...................... 227 t able 324: ds3 f ramer b lock - prbs b it e rror c ount r egister - msb (a ddress = 0 x 0e68) ........................................ 228 t able 325: ds3 f ramer b lock - prbs b it e rror c ount r egister - lsb (a ddress = 0 x 0e69) ......................................... 228 t able 326: ds3 f ramer b lock - o ne s econd e rror s tatus r egister (a ddress = 0 x 0e6d) ............................................. 228 t able 327: ds3 f ramer b lock - lcv o ne s econd a ccumulator r egister - msb (a ddress = 0 x 0e6e) ........................... 229
XRT86SH328 preliminary vii 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 t able 328: ds3 f ramer b lock - lcv o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 0e6f) ............................ 229 t able 329: ds3 f ramer b lock - p-b it e rror o ne s econd a ccumulator r egister - msb (a ddress = 0 x 0e70) .............. 229 t able 330: ds3 f ramer b lock - p-b it e rror o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 0e71) ............... 230 t able 331: ds3 f ramer b lock - cp-b it e rror o ne s econd a ccumulator r egister - msb (a ddress = 0 x 0e72) ............ 230 t able 332: ds3 f ramer b lock - cp-b it e rror o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 0e73) ............. 230 t able 333: ds3 f ramer b lock - t ransmit lapd b yte c ount r egister (a ddress = 0 x 0e83) ............................................. 231 t able 334: ds3 f ramer b lock - r eceive lapd b yte c ount r egister (a ddress = 0 x 0e84) ............................................... 231 t able 335: ds3 f ramer b lock - r eceive ds2 l oop -b ack r equest i nterrupt e nable r egister (a ddress = 0 x 0e90) ..... 231 t able 336: ds3 f ramer b lock - r eceive ds2 l oop -b ack r equest i nterrupt s tatus r egister (a ddress = 0 x 0e91) ..... 232 t able 337: ds3 f ramer b lock - r eceive ds2 l oop - back r equest s tatus r egister (a ddress = 0 x 0e92) ....................... 233 t able 338: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 1 (a ddress = 0 x 0e93) ................. 234 t able 339: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 1 (a ddress = 0 x 0e94) ............................................. 235 t able 340: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 2 (a ddress = 0 x 0e95) ................. 235 t able 341: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 2 (a ddress = 0 x 0e96) ............................................. 236 t able 342: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 3 (a ddress = 0 x 0e97) ................. 236 t able 343: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 3 (a ddress = 0 x 0e98) ............................................. 236 t able 344: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 4 (a ddress = 0 x 0e99) ................. 237 t able 345: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 4 (a ddress = 0 x 0e9a) ............................................. 237 t able 346: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 5 (a ddress = 0 x 0e9b) ................. 237 t able 347: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 5 (a ddress = 0 x 0e9c) ............................................. 238 t able 348: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 6 (a ddress = 0 x 0e9d) ................ 238 t able 349: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 6 (a ddress = 0 x 0e9e) ............................................. 238 t able 350: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 7 (a ddress = 0 x 0e9f) ................. 239 t able 351: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 7 (a ddress = 0 x 0ea0) ............................................. 239 t able 352: ds3 f ramer b lock - ds2 # 1 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ea1) ................................. 239 t able 353: ds3 f ramer b lock - ds2 # 1 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0ea2) ................................. 241 t able 354: ds3 f ramer b lock - ds2 # 1 f ramer s tatus r egister (a ddress = 0 x 0ea3) ................................................... 242 t able 355: ds3 f ramer b lock - ds2 # 2 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ea4) ................................. 243 t able 356: ds3 f ramer b lock - ds2 # 2 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0ea5) ................................. 243 t able 357: ds3 f ramer b lock - ds2 # 2 f ramer s tatus r egister (a ddress = 0 x 0ea6) ................................................... 243 t able 358: ds3 f ramer b lock - ds2 # 3 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ea7) ................................. 244 t able 359: ds3 f ramer b lock - ds2 # 3 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0ea8) ................................. 244 t able 360: ds3 f ramer b lock - ds2 # 3 f ramer s tatus r egister (a ddress = 0 x 0ea9) ................................................... 244 t able 361: ds3 f ramer b lock - ds2 # 4 f ramer i nterrupt e nable r egister (a ddress = 0 x 0eaa) ................................. 245 t able 362: ds3 f ramer b lock - ds2 # 4 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eab) ................................. 245 t able 363: ds3 f ramer b lock - ds2 # 4 f ramer s tatus r egister (a ddress = 0 x 0eac) .................................................. 245 t able 364: ds3 f ramer b lock - ds2 # 5 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ead) ................................. 246 t able 365: ds3 f ramer b lock - ds2 # 5 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eae) ................................. 246 t able 366: ds3 f ramer b lock - ds2 # 5 f ramer s tatus r egister (a ddress = 0 x 0eaf) ................................................... 246 t able 367: ds3 f ramer b lock - ds2 # 6 f ramer i nterrupt e nable r egister (a ddress = 0 x 0eb0) ................................. 247 t able 368: ds3 f ramer b lock - ds2 # 6 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eb1) ................................. 247 t able 369: ds3 f ramer b lock - ds2 # 6 f ramer s tatus r egister (a ddress = 0 x 0eb2) ................................................... 247 t able 370: ds3 f ramer b lock - ds2 # 7 f ramer i nterrupt e nable r egister (a ddress = 0 x 0eb3) ................................. 248 t able 371: ds3 f ramer b lock - ds2 # 7 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eb4) ................................. 248 t able 372: ds3 f ramer b lock - ds2 # 7 f ramer s tatus r egister (a ddress = 0 x 0eb5) ................................................... 248 t able 373: ds3 f ramer b lock - m13 d e -mux r egister (a ddress = 0 x 0eb8) ..................................................................... 249 2.12 t1/e1 liu channel control registe rs .............. .............. .............. ............ ........... ........... ........... ..... 249 t able 374: liu c hannel c ontrol r egister 0 (a ddress = 0 x n000) ..................................................................................... 249 t able 375: liu c hannel c ontrol r egister 0 (a ddress = 0 x n001) ...................................................................................... 250 t able 376: liu c hannel c ontrol r egister 0 (a ddress = 0 x n002) ...................................................................................... 251 t able 377: liu c hannel c ontrol r egister 0 (a ddress = 0 x n003) ...................................................................................... 252 t able 378: liu c hannel c ontrol r egister 0 (a ddress = 0 x n004) ...................................................................................... 253 t able 379: liu c hannel c ontrol r egister 0 (a ddress = 0 x n005) ...................................................................................... 253 t able 380: liu c hannel c ontrol r egister 0 (a ddress = 0 x n006) ...................................................................................... 254 t able 381: liu c hannel c ontrol r egister 0 (a ddress = 0 x n007) ...................................................................................... 255 t able 382: liu c hannel c ontrol r egister 0 (a ddress = 0 x n008) ...................................................................................... 256 t able 383: liu c hannel c ontrol r egister 0 (a ddress = 0 x n009) ...................................................................................... 256 t able 384: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00a) ...................................................................................... 256 t able 385: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00b) ...................................................................................... 257 t able 386: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00c) ...................................................................................... 257 t able 387: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00d) ...................................................................................... 257 t able 388: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00e) ...................................................................................... 258 t able 389: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00f) ...................................................................................... 258 t able 390: liu c hannel c ontrol r egister 0 (a ddress = 0 x n010) ...................................................................................... 258 t able 391: liu c hannel c ontrol r egister 0 (a ddress = 0 x n011) ...................................................................................... 259 2.13 ds1/e1 framer block registers - ds1 applications ................................................................. 259
preliminary XRT86SH328 viii rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications f igure 17. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the t ransmit /r eceive ds1/e1 f ramer blocks highlighted ............................................................................................................................... ...... 259 t able 392: m emory m ap - t1/e1 f ramer b lock ..................................................................................................................... 260 f igure 18. i llustration of the f unctional b lock d iagram of the XRT86SH328 device with both the i ngress and e gress d i - rection t1/e1 f ramer blocks ( of a given t1/e1 c hannel ) highlighted .............................................................. 261 t able 393: r elationship between v alue of n and c hannel n umber , s ignal d irection - vt-m apper ( with t1/e1 f raming ) m ode a pplications .............................................................................................................................. ............................... 261 t able 394: r elationship between v alue of n and c hannel n umber , s ignal d irection - m13 mux ( with t1/e1 f raming ) m ode a pplications .............................................................................................................................. ............................... 262 t able 395: t1 f ramer b lock - c lock s elect r egister (a ddress = 0 x n100, where n ranges in value from 0 x 01 to 0 x 38) 263 t able 396: t1 f ramer b lock - l ine i nterface c ontrol r egister (a ddress = 0 x n101, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... .............................................. 264 t able 397: t1 f ramer b lock - f raming s elect r egister (a ddress = 0 x n107, where n ranges in value from 0 x 01 to 0 x 38) 265 t able 398: t1 f ramer b lock - a larm g eneration r egister (a ddress = 0 x n108, where n ranges in value from 0 x 01 to 0 x 38) 266 t able 399: t1 f ramer b lock - s ynchronization mux r egister (a ddress = 0 x n109, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... .............................................. 268 t able 400: t1 f ramer b lock - t ransmit d ata l ink s elect r egister (a ddress = 0 x n10a, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ......................................... 268 t able 401: t1 f ramer b lock - f raming c ontrol r egister (a ddress = 0 x n10b, where n ranges in value from 0 x 01 to 0 x 38) 270 t able 402: t1 f ramer b lock - r eceive s ignaling & d ata l ink s elect r egister (a ddress = 0 x n10c, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ....................... 270 t able 403: t1 f ramer b lock - r eceive s ignaling c hange r egister - 0 (a ddress = 0 x n10d, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ................................. 272 t able 404: t1 f ramer b lock - r eceive s ignaling c hange r egister - 1 (a ddress = 0 x n10e, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ................................. 272 t able 405: t1 f ramer b lock - r eceive s ignaling c hange r egister - 2 (a ddress = 0 x n10f, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ................................. 272 t able 406: t1 f ramer b lock - r eceive e xtra -b its r egister (a ddress = 0 x n112, where n ranges in value from 0 x 01 to 0 x 38) 273 t able 407: t1 f ramer b lock - d ata l ink c ontrol r egister (a ddress = 0 x n113, where n ranges in value from 0 x 01 to 0 x 38) 273 t able 408: t1 f ramer b lock - t ransmit d ata l ink c ontrol r egister (a ddress = 0 x n114, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ......................................... 274 t able 409: t1 f ramer b lock - r eceive d ata l ink c ontrol r egister (a ddress = 0 x n115, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ......................................... 275 t able 410: t1 f ramer b lock - c ustomer i nstallation a larm g eneration r egisters (a ddress = 0 x n11c, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ............. 275 t able 411: t1 f ramer b lock - ds1 t est r egister - 2 (a ddress = 0 x n121, where n ranges in value from 0 x 01 to 0 x 38) 276 t able 412: t1 f ramer b lock - ds1 t est r egister - 1 (a ddress = 0 x n123, where n ranges in value from 0 x 01 to 0 x 38) 277 t able 413: t1 f ramer b lock - l oop - back c ode c ontrol r egister - c ode 0(a ddress = 0 x n124, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ................................. 278 t able 414: t1 f ramer b lock - t ransmit l oop - back c ode r egister (a ddress = 0 x n125, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ......................................... 279 t able 415: r eceive t1 f ramer b lock - r eceive l oop - back a ctivation c ode r egister - c ode 0 (a ddress = 0 x n126, where n ranges in value from 0 x 01 to 0 x 38) ....................................................................................................................... 280 t able 416: r eceive t1 f ramer b lock - r eceive l oop -b ack d eactivation c ode r egister - c ode 0 (a ddress = 0 x n127, where n ranges in value from 0 x 01 to 0 x 38) ................................................................................................................... 281 t able 417: t1 f ramer b lock - l oop - back c ode c ontrol r egister - c ode 1 (a ddress = 0 x n12a, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ....................... 281 t able 418: r eceive t1 f ramer b lock - r eceive l oop - back a ctivation c ode r egister - c ode 1 (a ddress = 0 x n12b, where n ranges in value from 0 x 01 to 0 x 38) ....................................................................................................................... 282 t able 419: r eceive t1 f ramer b lock - r eceive l oop -b ack d eactivation c ode r egister - c ode 1 (a ddress = 0 x n12c, where n ranges in value from 0 x 01 to 0 x 38) ................................................................................................................... 283 t able 420: t1 f ramer b lock - l oop - back c ode c ontrol r egister - c ode 2 (a ddress = 0 x n12d, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ....................... 284 t able 421: r eceive t1 f ramer b lock - r eceive l oop - back a ctivation c ode r egister - c ode 2 (a ddress = 0 x n12e, where n ranges in value from 0 x 01 to 0 x 38) ....................................................................................................................... 285 t able 422: r eceive t1 f ramer b lock - r eceive l oop -b ack d eactivation c ode r egister - c ode 2 (a ddress = 0 x n12f, where n ranges in value from 0 x 01 to 0 x 38) ................................................................................................................... 285 t able 423: t1 f ramer b lock - t ransmit c hannel c ontrol r egister - t1 t ime s lot # 0 (a ddress = 0 x n300, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ......... 286 t able 424: t1 f ramer b lock - lapd b uffer 0 c ontrol r egister (a ddress = 0 x n600 - 0 x n640, where n ranges in value from
XRT86SH328 preliminary ix 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0 x 01 to 0 x 38) ........................................................................................................................... ................................. 287 t able 425: t1 f ramer b lock - lapd b uffer 1 c ontrol r egister (a ddress = 0 x n700 - 0 x n740, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ................................. 287 t able 426: t1 f ramer i nterrupt r egister - r eceive l oop - back c ode i nterrupt and s tatus r egister -c ode 0 (a ddress = 0 x nb0a, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................ 288 t able 427: t1 f ramer i nterrupt r egister - r eceive l oop -b ack c ode i nterrupt e nable r egister - c ode 0 (a ddress = 0 x nb0b, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................ 289 t able 428: t1 f ramer i nterrupt r egister - r eceive l oop - back c ode i nterrupt and s tatus r egister - c ode 1 (a ddress = 0 x nb14, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................ 290 t able 429: t1 f ramer i nterrupt r egister - r eceive l oop -b ack c ode i nterrupt e nable r egister - c ode 1 (a ddress = 0 x nb15, where n ranges in value from 0 x 01 to 0 x 38) ....................................................................................................... 291 t able 430: t1 f ramer i nterrupt r egister - r eceive l oop - back c ode i nterrupt and s tatus r egister - c ode 2 (a ddress = 0 x nb1a, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................ 292 t able 431: t1 f ramer i nterrupt r egister - r eceive l oop -b ack c ode i nterrupt e nable r egister - c ode 2 (a ddress = 0 x nb1b, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................ 293 2.14 ds1/e1 framer block registers - e1 applications ................................................................... 294 t able 432: e1 f ramer b lock - c lock s elect r egister (a ddress = 0 x n100, where n ranges in value from 0 x 01 to 0 x 38) 294 t able 433: e1 f ramer b lock - l ine i nterface c ontrol r egister (a ddress = 0 x n101, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ............................................... 295 t able 434: e1 f ramer b lock - f raming s elect r egister (a ddress = 0 x n107, where n ranges in value from 0 x 01 to 0 x 38) 296 t able 435: e1 f ramer b lock - a larm g eneration r egister (a ddress = 0 x n108, where n ranges in value from 0 x 01 to 0 x 38) 298 t able 436: e1 f ramer b lock - s ynchronization mux r egister (a ddress = 0 x n109, where n ranges in value from 0 x 01 to 0 x 38) ........................................................................................................................... ............................................... 299 2.15 channel control-vt mapper block re gisters........ .............. .............. .............. ........... ............. 300 f igure 19. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the vt-m apper block highlighted 301 t able 437: c hannel c ontrol - vt-m apper b lock - i ngress d irection ds1/e1 i nsertion c ontrol r egister - 2 (a ddress = 0 x nd41) ......................................................................................................................... ........................................... 301 t able 438: c hannel c ontrol - vt-m apper b lock - i ngress d irection - ds1/e1 i nsertion c ontrol r egister - 1 (a ddress = 0 x nd42, where n ranges from 0 x 01 to 0 x 1c) ...................................................................................................... 302 t able 439: c hannel c ontrol - vt-m apper b lock - i ngress d irection - ds1/e1 i nsertion c ontrol r egister - 0 (a ddress = 0 x nd43 , where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................... 303 f igure 20. a n i llustration of the f unctional b lock d iagram of the XRT86SH328 whenever the vt-m apper block ( associ - ated with a given channel ) has been configured to transmit the ais-v indicator towards down - stream circuitry 304 t able 440: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - ds1/e1 d rop c ontrol r egister - b yte 3 (a ddress = 0 x nd44, where n ranges in value from 0 x 01 to 0 x 1c) ..................................................................................... 306 t able 441: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - ds1/e1 d rop c ontrol r egister - b yte 2 (a ddress = 0 x nd45, where n ranges in value from 0 x 01 to 0 x 1c) ..................................................................................... 306 t able 442: c hannel c ontrol - vt-d e -m apper b lock - e ngress d irection - ds1/e1 d rop c ontrol r egister - b yte 1 (a ddress = 0 x nd46, where n ranges in value from 0 x 01 to 0 x 1c) ..................................................................................... 307 t able 443: c hannel c ontrol - vt-d e -m apper b lock - e ngress d irection - ds1/e1 d rop c ontrol r egister - b yt e 0 (a ddress = 0 x nd47, where n ranges in value from 0 x 01 to 0 x 1c) ..................................................................................... 307 f igure 21. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever the vt-d e -m apper block ( as - sociated with a given channel ) overwrites the contents of a de - mapped ds1/e1 signal with the ds1/e1 ais p at - tern ............................................................................................................................... ............................................ 308 t able 444: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - bip-2 e rror c ount r egister - b yte 1 (a ddress = 0 x nd4a, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................... 310 t able 445: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - bip-2 e rror c ount r egister - b yte 0 (a ddress = 0 x nd4b, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................... 311 t able 446: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - rei-v e vent c ount r egister - b yte 1 (a ddress = 0 x nd4e, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................... 311 t able 447: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - rei-v e vent c ount r egister - b yte 0 (a ddress = 0 x nd4f, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................... 312 t able 448: c hannel c ontrol - vt-m apper b lock - e gress d irection - r eceive aps r egister - b yte 0 (a ddress = 0 x nd53, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................................... 312 t able 449: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit aps r egister - b yte 2 (a ddress = 0 x nd56, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................................... 312 t able 450: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit aps/k4 r egister (a ddress = 0 x nd57, where n ranges in value from 0 x 01 to 0 x 1c) ................................................................................................................... 313 t able 451: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - j2 b yte s tatus r egister (a ddress = 0 x nd63, where n ranges in value from 0 x 01 to 0 x 1c) ................................................................................................................... 314 t able 452: c hannel c ontrol - vt-m apper b lock - e gress d irection - c omposite s tatus r egister - b yte 0 (a ddress =
preliminary XRT86SH328 x rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0 x nd64, where n ranges in value from 0 x 01 to 0 x 1c) ........................................................................................ 314 t able 453: c hannel c ontrol - vt-m apper b lock - e gress d irection - c omposite s tatus r egister - b yte 0 (a ddress = 0 x nd65, where n ranges in value from 0 x 01 to 0 x 1c) ........................................................................................ 315 t able 454: c hannel c ontrol - vt-m apper b lock - e gress d irection - i nterrupt s tatus r egister (a ddress = 0 x nd67, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................................................................. 317 t able 455: c hannel c ontrol - vt-m apper b lock - e gress d irection - i nterrupt e nable r egister (a ddress = 0 x nd68, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................................................................. 318 t able 456: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - i nterrupt e nable r egister (a ddress = 0 x nd69, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................................... 318 t able 457: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - i nterrupt e nable r egister (a ddress = 0 x nd6b, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................................... 320 t able 458: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - vt-p ath t race b uffer c ontrol r egister (a ddress = 0 x nd71, where n ranges in value from 0 x 01 to 0 x 1c) ................................................................................... 321 t able 459: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - a uto ais c ontrol r egister - b yte 1 (a ddress = 0 x nd72, where n ranges in value from 0 x 01 to 0 x 1c) ........................................................................................ 322 t able 460: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - a uto ais c ontrol r egister - b yte 0 (a ddress = 0 x nd73, where n ranges in value from 0 x 01 to 0 x 1c) ........................................................................................ 323 t able 461: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit j2 b yte v alue r egister (a ddress = 0 x nd76, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................................... 324 t able 462: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit n2 b yte v alue r egister (a ddress = 0 x nd77, where n ranges in value from 0 x 01 to 0 x 1c) ....................................................................................................... 324 t able 463: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit vt-p ath t race m essage c ontrol r egister (a ddress = 0 x nd79, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................... 325 t able 464: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 3 (a ddress = 0 x nd84, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................................... 326 t able 465: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 2 (a ddress = 0 x nd85, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................................... 326 t able 466: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 1 (a ddress = 0 x nd86, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................................... 327 t able 467: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 0 (a ddress = 0 x nd87, where n ranges in value from 0 x 01 to 0 x 1c) .................................................................................... 328 r evisions ............................................................................................................................... ................. 329
XRT86SH328 preliminary 4 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 1.0 register map & description for the xr t86sh328 28-channel ds1/e1 framer/liu with ds3 mux and vt-mapper ic - sonet applications 1.1 register map of the XRT86SH328 t able 2: o peration c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0000 operation control register - byte 3 r/w 0x00 0x0001 operation control register - byte 2 r/w 0x00 0x0002 reserved 0x0003 operation control register - byte 0 r/w 0x00 0x0004 device id register r/o 0x50 0x0005 revision id register r/o 0x01 0x0006 - 0x000a reserved 0x000b operation interrupt status register - byte 0 rur 0x00 0x000c - 0x000e reserved 0x000f operation interrupt enable register - byte 0 r/w 0x00 0x0010 - 0x0011 reserved 0x0012 operation block - interrupt status register - byte 1 r/o 0x00 0x0013 operation block - interrupt status register - byte 0 r/o 0x00 0x0014 - 0x0015 reserved 0x0016 operation block - interrupt enable register - byte 1 r/w 0x00 0x0017 operation block - interrupt enable register - byte 0 r/w 0x00 0x0018 - 0x001a reserved 0x001b operation block - mode control register - byte 0 r/w 0x00 0x001c - 0x001e reserved 0x001f operation block - loop-back control register - byte 0 r/w 0x00 0x0020 - 0x0033 reserved 0x0034 operation block - telecom bus control register - byte 3 r/w 0x00 0x0035 operation block - telecom bus control register - byte 2 r/w 0x00 0x0036 operation block - telecom bus control register - byte 1 r/w 0x00 0x0037 operation block - telecom bus control register - byte 0 r/w 0x00 0x0038 - 0x003b reserved 0x003c operation block - interface control register rur & r/w 0x00 0x003d - 0x0046 reserved 0x0047 operation block - general purpose input/output register - byte 0 r/w 0x00
preliminary XRT86SH328 5 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0048 - 0x004a reserved 0x004b operation block - general purpose input/output direction register - byte 0 rw 0x00 0x004c - 0x004e reserved 0x004f operation block - operation i/o control register r/w 0x00 0x0050 operation block - channel interrupt indication register - vt slot[27:24] r/o 0x00 0x0051 operation block - channel interrupt indicator register - vt slot[23:16] r/o 0x00 0x0052 operation block - channel interrupt indicator register - vt slot[15:8] r/o 0x00 0x0053 operation block - channel interrupt indicator register - vt slot[7:0] r/o 0x00 0x0054 operation block - channel interrupt indicator register - m13 slot[27:24] r/o 0x00 0x0055 operation block - channel interrupt indicator register - m13 slot[23:16] r/o 0x00 0x0056 operation block - channel interrupt indicator register - m13 slot[15:8] r/o 0x00 0x0057 operation block - channel interrupt indicator register - m13 slot[7:0] r/o 0x00 0x0058 operation block - channel interrupt indicator register - ds1e1 liu slot[27:24] r/o 0x00 0x0059 operation block - channel interrupt indicator register - ds1e1 liu slot[23:16] r/o 0x00 0x005a operation block - channel interrupt indicator register - ds1e1 liu slot[15:8] r/o 0x00 0x005b operation block - channel interrupt indicator register - ds1e1 liu slot[7:0] r/o 0x00 0x005c operation block - channel interrupt indicator register - vt-mapper slot[27:24] r/o 0x00 0x005d operation block - channel interrupt indicator register - vt-mapper slot[23:16] r/o 0x00 0x005e channel interrupt indication re gister - vt-mapper slot[15:8] r/o 0x00 0x005f channel interrupt indication re gister - vt-mapper slot[7:0] r/o 0x00 0x0060 - 0x00ff reserved t able 3: liu c ommon c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0100 liu common control register - 0 r/w 0x00 0x0101 liu common control register - 1 r/w 0x00 0x0102 liu common control register - 2 r/w 0x00 t able 2: o peration c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x0103 liu common control register - global ch annel interrupt status register - channels [6:0] rur 0x00 0x0104 liu common control register - global channel interrupt status register - channels [13:7] rur 0x00 0x0105 liu common control register - global channel interrupt status register - channels [20:14] rur 0x00 0x0106 liu common control register - global channel interrupt status register - channels [27:21] rur 0x00 0x0107 - 0x01ff reserved t able 4: r eceive sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0200 - 0x0201 reserved 0x0202 receive sts-1/sts-3 transport - control register - byte 1 r/w 0x00 0x0203 receive sts-1/sts-3 transport - control register - byte 0 r/w 0x00 0x0204 - 0x0205 reserved r/o 0x00 0x0206 receive sts-1/sts-3 transport - status register - byte 1 r/o 0x00 0x0207 receive sts-1/sts-3 transport - status register - byte 0 r/o 0x00 0x0208 reserved 0x0209 receive sts-1/sts-3 transport - interrupt status register - byte 2 rur 0x00 0x020a receive sts-1/sts-3 transport - interrupt status register - byte 1 rur 0x00 0x020b receive sts-1/sts-3 transport - interrupt status register - byte 0 rur 0x00 0x020c reserved 0x020d receive sts-1/sts-3 transport - interrupt enable register - byte 2 r/w 0x00 0x020e receive sts-1/sts-3 transport - interrupt enable register - byte 1 r/w 0x00 0x020f receive sts-1/sts-3 transport - interrupt enable register - byte 0 r/w 0x00 0x0210 receive sts-1/sts-3 transport - receiv e b1 byte error count register - byte 3 rur 0x00 0x0211 receive sts-1/sts-3 transport - receiv e b1 byte error count register - byte 2 rur 0x00 0x0212 receive sts-1/sts-3 transport - receiv e b1 byte error count register - byte 1 rur 0x00 0x0213 receive sts-1/sts-3 transport - receiv e b1 byte error count register - byte 0 rur 0x00 t able 3: liu c ommon c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 7 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0214 receive sts-1/sts-3 transport - receiv e b2 byte error count register - byte 3 rur 0x00 0x0215 receive sts-1/sts-3 transport - receiv e b2 byte error count register - byte 2 rur 0x00 0x0216 receive sts-1/sts-3 transport - receiv e b2 byte error count register - byte 1 rur 0x00 0x0217 receive sts-1/sts-3 transport - receiv e b2 byte error count register - byte 0 rur 0x00 0x0218 receive sts-1/sts-3 transport - rece ive rei-l event count register - byte 3 rur 0x00 0x0219 receive sts-1/sts-3 transport - rece ive rei-l event count register - byte 2 rur 0x00 0x021a receive sts-1/sts-3 transport - rece ive rei-l event count register - byte 1 rur 0x00 0x021b receive sts-1/sts-3 transport - rece ive rei-l event count register - byte 0 rur 0x00 0x021c - 0x021e reserved 0x021f receive sts-1/sts-3 transport - receive k1 byte value register r/o 0x00 0x0220 - 0x0222 reserved 0x0223 receive sts-1/sts-3 transport - receive k2 byte value register r/o 0x00 0x0224 -0x0226 reserved 0x0227 receive sts-1/sts-3 transport - receive s1 byte value register r/o 0x00 0x0228 - 0x022a reserved 0x022b receive sts-1/sts-3 transport - receive in-sync threshold register r/w 0x00 0x022c - 0x022d reserved 0x022e receive sts-1/sts-3 transport - receive los threshold register - msb r/w 0x00 0x022f receive sts-1/sts-3 transport - receive los threshold register - lsb r/w 0x00 0x0230 reserved 0x0231 receive sts-1/sts-3 transport - receive sf defect declare monitor interval register - byte 2 r/w 0x00 0x0232 receive sts-1/sts-3 transport - receive sf defect declare monitor interval register - byte 1 r/w 0x00 0x0233 receive sts-1/sts-3 transport - receive sf defect declare monitor interval register - byte 0 r/w 0x00 0x0234 - 0x0235 reserved 0x0236 receive sts-1/sts-3 transport - rece ive sf defect set threshold reg - ister - byte 1 r/w 0x00 t able 4: r eceive sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 8 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x0237 receive sts-1/sts-3 transport - rece ive sf defect set threshold reg - ister - byte 0 r/w 0x00 0x0238 - 0x0239 reserved 0x023a receive sts-1/sts-3 transport - receive sf defect clear threshold register - byte 1 r/w 0x00 0x023b receive sts-1/sts-3 transport - receive sf defect clear threshold register - byte 0 r/w 0x00 0x023c reserved 0x023d receive sts-1/sts-3 transport - receive sd defect declare monitor interval - byte 2 r/w 0x00 0x023e receive sts-1/sts-3 transport - receive sd defect declare monitor interval - byte 1 r/w 0x00 0x023f receive sts-1/sts-3 transport - receive sd defect declare monitor interval - byte 0 r/w 0x00 0x0240 - 0x0241 reserved 0x0242 receive sts-1/sts-3 transport - rece ive sd defect set threshold reg - ister - byte 1 r/w 0x00 0x0243 receive sts-1/sts-3 transport - rece ive sd defect set threshold reg - ister - byte 0 r/w 0x00 0x0244 - 0x0245 reserved 0x0246 receive sts-1/sts-3 transport - receive sd defect clear threshold register - byte 1 r/w 0x00 0x0247 receive sts-1/sts-3 transport - receive sd defect clear threshold register - byte 0 r/w 0x00 0x0248 - 0x024a reserved 0x024b receive sts-1/sts-3 transport - sef force register r/w 0x00 0x024c -0x024e reserved 0x024f receive sts-1/sts-3 transport - receive j0 byte/section trace mes - sage control register r/w 0x00 0x0250 - 0x0251 reserved 0x0252 receive sts-1/sts-3 transport - rece ive sd defect error burst toler - ance register - byte 1 r/w 0x00 0x0253 receive sts-1/sts-3 transport - rece ive sd defect error burst toler - ance register - byte 0 r/w 0x00 0x0254 - 0x0255 reserved 0x0256 receive sts-1/sts-3 transport - rece ive sf defect error burst toler - ance register - byte 1 r/w 0x00 t able 4: r eceive sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 9 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0257 receive sts-1/sts-3 transport - rece ive sf defect error burst toler - ance register - byte 0 r/w 0x00 0x0258 reserved 0x0259 receive sts-1/sts-3 transport - receive sd defect clear monitor inter - val - byte 2 r/w 0x00 0x025a receive sts-1/sts-3 transport - receive sd defect clear monitor inter - val - byte 1 r/w 0x00 0x025b receive sts-1/sts-3 transport - receive sd defect clear monitor inter - val - byte 0 r/w 0x00 0x025c reserved 0x025d receive sts-1/sts-3 transport - rece ive sf defect clear monitor inter - val - byte 2 r/w 0x00 0x025e receive sts-1/sts-3 transport - rece ive sf defect clear monitor inter - val - byte 1 r/w 0x00 0x025f receive sts-1/sts-3 transport - rece ive sf defect clear monitor inter - val - byte 0 r/w 0x00 0x0260 - 0x0262 reserved 0x0263 receive sts-1/sts-3 transport - auto ais control register r/w 0x00 0x0264 - 0x0266 reserved 0x0267 receive sts-1/sts-3 transport - serial port co ntrol register r/w 0x00 0x0268 - 0x026a reserved 0x026b receive sts-1/sts-3 transport - auto ais (in downstream t1/e1) regis - ter r/w 0x00 0x026c - 0x026d reserved 0x026e receive sts-1/sts-3 transport - a1, a2 byte error count register - byte 1 rur 0x00 0x026f receive sts-1/sts-3 transport - a1, a2 byte error count register - byte 0 rur 0x00 0x0270 - 0x0279 reserved 0x027a receive sts-1/sts-3 transport - receive toh capture buffer - indirect address register - byte 1 w 0x00 0x027b receive sts-1/sts-3 transport - receive toh capture buffer - indirect address register - byte 0 w 0x00 0x027c receive sts-1/sts-3 transport - receive toh capture buffer - indirect data register - byte 3 w 0x00 0x027d receive sts-1/sts-3 transport - receive toh capture buffer - indirect data register - byte 2 w 0x00 t able 4: r eceive sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 10 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x027e receive sts-1/sts-3 transport - receive toh capture buffer - indirect data register - byte 1 w 0x00 0x027f receive sts-1/sts-3 transport - receive toh capture buffer - indirect data register - byte 0 w 0x00 0x0280 reserved t able 5: r eceive sts-1/sts-3 poh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0281 receive sts-1/sts-3 path - rece ive control register - byte 2 r/w 0x00 0x0282 reserved 0x0283 receive sts-1/sts-3 path - rece ive control register - byte 0 r/w 0x00 0x0284 - 0x0285 reserved 0x0286 receive sts-1/sts-3 path - rece ive status register - byte 1 r/o 0x00 0x0287 receive sts-1/sts-3 path - rece ive status register - byte 0 r/o 0x00 0x0288 reserved 0x0289 receive sts-1/sts-3 path - receive interrupt status register - byte 2 rur 0x00 0x028a receive sts-1/sts-3 path - receive interrupt status register - byte 1 rur 0x00 0x028b receive sts-1/sts-3 path - receive interrupt status register - byte 0 rur 0x00 0x028c reserved 0x028d receive sts-1/sts-3 path - receive interrupt enab le register - byte 2 r/w 0x00 0x028e receive sts-1/sts-3 path - receive interrupt enab le register - byte 1 r/w 0x00 0x028f receive sts-1/sts-3 path - receive interrupt enab le register - byte 0 r/w 0x00 0x0290 - 0x0292 reserved 0x0293 receive sts-1/sts-3 path - receive rdi-p register r/o & r/w 0x00 0x0294 - 0x295 reserved 0x0296 receive sts-1/sts-3 path - receiv e c2 (path label) byte accepted register r/o 0xff 0x0297 receive sts-1/sts-3 path - receiv e c2 (path label) byte expected register r/w 0xff 0x0298 receive sts-1/sts-3 path - receive b3 byte error count register - byte 3 rur 0x00 0x0299 receive sts-1/sts-3 path - receive b3 byte error count register - byte 2 rur 0x00 0x029a receive sts-1/sts-3 path - receive b3 byte error count register - byte 1 rur 0x00 t able 4: r eceive sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 11 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x029b receive sts-1/sts-3 path - receive b3 byte error count register - byte 0 rur 0x00 0x029c receive sts-1/sts-3 path - receive re i-p event count register - byte 3 rur 0x00 0x029d receive sts-1/sts-3 path - receive re i-p event count register - byte 2 rur 0x00 0x029e receive sts-1/sts-3 path - receive re i-p event count register - byte 1 rur 0x00 0x029f receive sts-1/sts-3 path - receive re i-p event count register - byte 0 rur 0x00 0x02a0 - 0x02a2 reserved 0x02a3 receive sts-1/sts-3 path - receiv e j1 byte/path trace message con - trol register r/w 0x00 0x02a4 - 0x02a5 reserved 0x02a6 receive sts-1/sts-3 - receive po inter value register - byte 1 r/o 0x00 0x02a7 receive sts-1/sts-3 - receive po inter value register - byte 0 r/o 0x00 0x02a8 - 0x02aa reserved 0x02ab receive sts-1/sts-3 - receive lop-c status register r/o 0x00 0x02ac - 0x02b2 reserved 0x02b3 receive sts-1/sts-3 - rece ive ais-c status register r/o 0x00 0x02b4 - 0x02b8 reserved 0x02b9 receive sts-1/sts-3 - receive auto ais - c2 byte value register r/w 0x00 0x02ba receive sts-1/sts-3 - receive auto ais - c2 byte control register r/w 0x00 0x02bb receive sts-1/sts-3 - receiv e auto ais control register r/w 0x00 0x02bc - 0x02be reserved 0x02bf receive sts-1/sts-3 - receive serial port control register r/w 0x00 0x02c0 -0x02c2 reserved 0x02c3 receive sts-1/sts-3 - auto ais (in downstream t1/e1) register r/w 0x00 0x02c4 receive sts-1/sts-3 - receive negati ve pointer adjustment count reg - ister - byte 1 rur 0x00 0x02c5 receive sts-1/sts-3 - receive negati ve pointer adjustment count reg - ister - byte 0 rur 0x00 0x02c6 receive sts-1/sts-3 - receive positi ve pointer adjustment count regis - ter - byte 1 rur 0x00 0x02c7 receive sts-1/sts-3 - receive positi ve pointer adjustment count regis - ter - byte 0 rur 0x00 0x02c8 - 0x02d2 reserved 0x02d3 receive sts-1/sts-3 - receiv e j1 byte value register r/o 0x00 0x02d4 - 0x02d6 reserved t able 5: r eceive sts-1/sts-3 poh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 12 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x02d7 receive sts-1/sts-3 - receiv e b3 byte value register r/o 0x00 0x02d8 - 0x02da reserved 0x02db receive sts-1/sts-3 - receiv e c2 byte value register r/o 0x00 0x02dc - 0x02de reserved 0x02df receive sts-1/sts-3 - receive g1 byte value register r/o 0x00 0x02e0 - 0x02e2 reserved 0x02e3 receive sts-1/sts-3 - receive f2 byte value register r/o 0x00 0x02e4 - 0x02e6 reserved 0x02e7 receive sts-1/sts-3 - receiv e h4 byte value register r/o 0x00 0x02e8 - 0x02ea reserved 0x02eb receive sts-1/sts-3 - receive z3 byte value register r/o 0x00 0x02ec - 0x02ee reserved 0x02ef receive sts-1/sts-3 - receive z4 byte value register r/o 0x00 0x02f0 - 0x02f2 reserved 0x02f3 receive sts-1/sts-3 - receive z5 byte value register r/o 0x00 0x02f4 - 0x02ff reserved t able 6: r eceive sts-1/sts-3 t ransport - r eceive s ection t race m essage b uffer a ddress l ocation r egister n ame t ype d efault v alue 0x0300 - 0x033f receive sts-1/sts-3 transport - receive section trace message buffer r/o 0x00 0x0340 - 0x03ff reserved r/o 0x00 t able 7: r eceive sts-1/sts-3 p ath - r eceive p ath t race m essage b uffer a ddress l ocation r egister n ame t ype d efault v alue 0x0400 - 0x043f receive sts-1/sts-3 path - receive path trace message buffer r/o 0x00 0x0440 - 0x0580 reserved r/o 0x00 t able 8: r eceive tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue 0x0581 receive tu-3 path - receive control register - byte 2 r/w 0x00 0x0582 reserved t able 5: r eceive sts-1/sts-3 poh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 13 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0583 receive tu-3 path - receive control register - byte 0 r/w 0x00 0x0584 - 0x0585 reserved 0x0586 receive tu-3 path - receive status register - byte 1 r/o 0x00 0x0587 receive tu-3 path - receive status register - byte 0 r/o 0x00 0x0588 reserved 0x0589 receive tu-3 path - receive inte rrupt status register - byte 2 rur 0x00 0x058a receive tu-3 path - receive inte rrupt status register - byte 1 rur 0x00 0x058b receive tu-3 path - receive inte rrupt status register - byte 0 rur 0x00 0x058c reserved 0x058d receive tu-3 path - receive interrupt enable register - byte 2 r/w 0x00 0x058e receive tu-3 path - receive interrupt enable register - byte 1 r/w 0x00 0x058f receive tu-3 path - receive interrupt enable register - byte 0 r/w 0x00 0x0590 - 0x0592 reserved 0x0593 receive tu-3 path - receive rdi-p register r/o & r/w 0x00 0x0594 - 0x0595 reserved 0x0596 receive tu-3 path - receive c2 (path label) byte accepted register r/o 0xff 0x0597 receive tu-3 path - receive c2 (path label) byte expected register r/w 0xff 0x0598 receive tu-3 path - receive b3 byte error count register - byte 3 rur 0x00 0x0599 receive tu-3 path - receive b3 byte error count register - byte 2 rur 0x00 0x059a receive tu-3 path - receive b3 byte error count register - byte 1 rur 0x00 0x059b receive tu-3 path - receive b3 byte error count register - byte 0 rur 0x00 0x059c receive tu-3 path - receive rei-p event count register - byte 3 rur 0x00 0x059d receive tu-3 path - receive rei-p event count register - byte 2 rur 0x00 0x059e receive tu-3 path - receive rei-p event count register - byte 1 rur 0x00 0x059f receive tu-3 path - receive rei-p event count register - byte 0 rur 0x00 0x05a0 - 0x05a2 reserved 0x05a3 receive tu-3 path - receive j1 byte/path trace message control regis - ter r/w 0x00 0x05a4 - 0x05a5 reserved 0x05a6 receive tu-3 path - receive pointer value register - byte 1 r/o 0x00 0x05a7 receive tu-3 path - receive pointer value register - byte 0 0x05a8 - 0x05aa reserved 0x05ab receive tu-3 path - receive lop-c status register r/o 0x00 t able 8: r eceive tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 14 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x05ac - 0x05b2 reserved 0x05b3 receive tu-3 path - receive ais-c status register r/o 0x00 0x05b4 - 0x05b8 reserved 0x05b9 receive tu-3 path - receive auto ais - c2 byte value register r/w 0x00 0x05ba receive tu-3 path - receive auto ais - c2 byte control register r/w 0x00 0x05bb receive tu-3 path - receive auto ais control register r/w 0x00 0x05bc - 0x05be reserved 0x05bf receive tu-3 path - receive se rial port control register r/w 0x00 0x05c0 - 0x05c2 reserved 0x05c3 receive tu-3 path - auto ais (in downstream t1/e1) register r/w 0x00 0x05c4 receive tu-3 path - receive negative pointer adjustment count register - byte 1 rur 0x00 0x05c5 receive tu-3 path - receive negative pointer adjustment count register - byte 0 rur 0x00 0x05c6 receive tu-3 path - receive positive pointer adjustment count register - byte 1 rur 0x00 0x05c7 receive tu-3 path - receive positive pointer adjustment count register - byte 0 rur 0x00 0x05c8 - 0x05d2 reserved 0x05d3 receive tu-3 path - receive j1 byte value register r/o 0x00 0x05d4 - 0x05d6 reserved 0x05d7 receive tu-3 path - receive b3 byte value register r/o 0x00 0x05d8 - 0x05da reserved 0x05db receive tu-3 path - receive c2 byte value register r/o 0x00 0x05dc - 0x05de reserved 0x05df receive tu-3 path - receive g1 byte value register r/o 0x00 0x05e0 - 0x05e2 reserved 0x05e3 receive tu-3 path - receive f2 byte value register r/o 0x00 0x05e4 - 0x05e6 reserved 0x05e7 receive tu-3 path - receive h4 byte value register r/o 0x00 0x05e8 - 0x05ea reserved 0x05eb receive tu-3 path - receive z3 byte value register r/o 0x00 0x05ec - 0x05ee reserved 0x05ef receive tu-3 path - receive z4 byte value register r/o 0x00 t able 8: r eceive tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 15 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x05f0 - 0x05f2 reserved 0x05f3 receive tu-3 path - receive z5 byte value register r/o 0x00 0x05f4 - 0x05ff reserved t able 9: r eceive tu-3 poh p rocessor b lock - r eceive p ath t race m essage b uffer (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue 0x0600 - 0x063f receive tu-3 poh processor block - receive path trace message buffer r/o 0x00 0x0640 - 0x06ff reserved t able 10: t ransmit sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0700 transmit sts-1/sts-3 transport - transmit control register - byte 3 r/w 0x00 0x0701 transmit sts-1/sts-3 transport - transmit control register - byte 2 r/w 0x00 0x0702 transmit sts-1/sts-3 transport - transmit control register - byte 1 r/w 0x00 0x0703 transmit sts-1/sts-3 transport - transmit control register - byte 0 r/w 0x00 0x0704 - 0x0715 reserved 0x0716 transmit sts-1/sts-3 transport - transmit a1 byte error mask register - byte 1 r/w 0x00 0x0717 transmit sts-1/sts-3 transport - transmit a1 byte error mask register - byte 0 r/w 0x00 0x0718 - 0x071d reserved 0x071e transmit sts-1/sts-3 transport - transmit a2 byte error mask register - byte 1 r/w 0x00 0x071f transmit sts-1/sts-3 transport - transmit a2 byte error mask register - byte 0 r/w 0x00 0x0720 - 0x0722 reserved 0x0723 transmit sts-1/sts-3 transport - tran smit b1 byte error mask register r/w 0x00 0x0724 - 0x0725 0x0726 transmit sts-1/sts-3 transport - transmit b2 byte error mask register - byte 1 r/w 0x00 0x0727 transmit sts-1/sts-3 transport - transmit b2 byte error mask register - byte 0 r/w 0x00 0x0728 - 0x072a reserved t able 8: r eceive tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 16 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x072b transmit sts-1/sts-3 transport - tr ansmit b2 byte bit error mask regis - ter r/w 0x00 0x072c - 0x072d reserved 0x072e transmit sts-1/sts-3 transport - transmit k1 byte value register r/w 0x00 0x072f transmit sts-1/sts-3 transport - tr ansmit k2 byte value register r/w 0x00 0x0730 - 0x0732 reserved 0x0733 transmit sts-1/sts-3 transport - transmit rdi-l control register r/w 0x00 0x0734 transmit sts-1/sts-3 transport - tr ansmit m0/m1 byte control register r/w 0x00 0x0735 reserved 0x0736 transmit sts-1/sts-3 transport - tr ansmit m0/m1 byte pointer register r/w 0x00 0x0737 transmit sts-1/sts-3 transport - tr ansmit m0/m1 byte value register r/w 0x00 0x0738 transmit sts-1/sts-3 transport - tr ansmit s1 byte control register r/w 0x00 0x0739 reserved 0x073a transmit sts-1sts-3 transport - transmit s1 pointer register r/w 0x00 0x073b transmit sts-1/sts-3 transport - transmit s1 byte value register r/w 0x00 0x073c transmit sts-1/sts-3 transport - tr ansmit f1 byte control register r/w 0x00 0x073d reserved 0x073e transmit sts-1/sts-3 transport - tr ansmit f1 byte pointer register r/w 0x00 0x073f transmit sts-1/sts-3 transport - tr ansmit f1 byte value register r/w 0x00 0x0740 transmit sts-1/sts-3 transport - tr ansmit e1 byte control register r/w 0x00 0x0741 reserved 0x0742 transmit sts-1/sts-3 transport - transmit e1 pointer register r/w 0x00 0x0743 transmit sts-1/sts-3 transport - transmit e1 byte value register r/w 0x00 0x0744 transmit sts-1/sts-3 transport - tr ansmit e2 byte control register r/w 0x00 0x0745 reserved 0x0746 transmit sts-1/sts-3 transport - tr ansmit e2 byte pointer register r/w 0x00 0x0747 transmit sts-1/sts-3 transport - transmit e2 byte value register r/w 0x00 0x0748 - 0x074a reserved 0x074b transmit sts-1/sts-3 transport - transmit j0 byte value register r/w 0x00 0x074c -0x074e reserved 0x074f transmit sts-1/sts-3 transport - transmit j0 byte/section trace mes - sage control register r/w 0x00 0x0750 - 0x0780 reserved t able 10: t ransmit sts-1/sts-3 toh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 17 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications t able 11: t ransmit sts-1/sts-3 poh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0781 transmit sts-1/sts-3 path - transmit path control register - byte 2 r/w 0x00 0x0782 transmit sts-1/sts-3 path - transmit path control register - byte 1 r/w 0x00 0x0783 transmit sts-1/sts-3 path - transmit path control register - byte 0 r/w 0x00 0x0784 - 0x0792 reserved 0x0793 transmit sts-1/sts-3 path - tr ansmit j1 byte value register r/w 0x00 0x0794 - 0x0796 reserved 0x0796 transmit sts-1/sts-3 path - transm it b3 byte pass thru register r/w 0x00 0x0797 transmit sts-1/sts-3 path - tr ansmit b3 byte mask register r/w 0x00 0x0798 - 0x079a reserved 0x079b transmit sts-1/sts-3 path - tr ansmit c2 byte value register r/w 0x00 0x079c - 0x079e reserved 0x079f transmit sts-1/sts-3 path - tr ansmit g1 byte value register r/w 0x00 0x07a0 - 0x07a2 reserved 0x07a3 transmit sts-1/sts-3 path - tr ansmit f2 byte value register r/w 0x00 0x07a4 - 0x07a6 reserved 0x07a7 transmit sts-1/sts-3 path - tr ansmit h4 byte value register r/w 0x00 0x07a8 - 0x07aa reserved 0x07ab transmit sts-1/sts-3 path - tr ansmit z3 byte value register r/w 0x00 0x07ac - 0x07ae reserved 0x07af transmit sts-1/sts-3 path - tr ansmit z4 byte value register r/w 0x00 0x07b0 - 0x07b2 reserved 0x07b3 transmit sts-1/sts-3 path - tr ansmit z5 byte value register r/w 0x00 0x07b4 - 0x07b6 reserved 0x07b7 transmit sts-1/sts-3 path - transmit control register - byte 0 r/w 0x00 0x07b8 - 0x07ba reserved 0x07bb transmit sts-1/sts-3 path - transmit j1 byte/path trace message con - trol register r/w 0x00 0x07bc - 0x07be reserved 0x07bf transmit sts-1/sts-3 path - transmit arbitrary pointer (h1 byte) value register r/w 0x00 0x07c0 - 0x07c2 reserved 0x07c3 transmit sts-1/sts-3 path - transmit arbitrary pointer (h2 byte) value register r/w 0x00
XRT86SH328 preliminary 18 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x07c4 - 0x07c5 reserved 0x07c6 transmit sts-1/sts-3 path - current pointer value register - high-byte r/o 0x02 0x07c7 transmit sts-1/sts-3 path - current pointer value register - low-byte r/o 0x0a 0x07c8 reserved 0x07c9 transmit sts-1/sts-3 path - transmit rdi-p control register - byte 2 r/w 0x00 0x07ca transmit sts-1/sts-3 path - transmit rdi-p control register - byte 1 r/w 0x00 0x07cb transmit sts-1/sts-3 path - transmit rdi-p control register - byte 0 r/w 0x00 0x07ca - 0x07ce reserved 0x07cf transmit sts-1/sts-3 path - transmit path serial port control register r/w 0x00 0x07d0 transmit sts-1/sts-3 - transmit n egative pointer adjustment count register - byte 1 rur 0x00 0x07d1 transmit sts-1/sts-3 - transmit n egative pointer adjustment count register - byte 0 rur 0x00 0x07d2 transmit sts-1/sts-3 - transmit posi tive pointer adjustment count reg - ister - byte 1 rur 0x00 0x07d3 transmit sts-1/sts-3 - transmit posi tive pointer adjustment count reg - ister - byte 0 rur 0x00 0x07d4 - 0x07ff reserved t able 12: t ransmit sts-1/sts-3 toh p rocessor b lock - t ransmit p ath t race m essage b uffer a ddress l ocation r egister n ame t ype d efault v alue 0x0800 - 0x083f transmit sts-1/sts-3 transport - transmit section trace message buffer r/w 0x00 0x0840 - 0x08ff reserved t able 13: t ransmit sts-1/sts-3 poh p rocessor b lock - t ransmit p ath t race m essage b uffer a ddress l ocation r egister n ame t ype d efault v alue 0x0900 - 0x093f transmit sts-1/sts-3 path - transmit path trace message buffer r/w 0x00 0x0940 - 0x0a80 reserved r/o 0x00 t able 11: t ransmit sts-1/sts-3 poh p rocessor b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 19 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications t able 14: t ransmit tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue 0x0a81 transmit tu-3 path - transmit pa th control register - byte 2 r/w 0x00 0x0a82 transmit tu-3 path - transmit pa th control register - byte 1 r/w 0x00 0x0a83 transmit tu-3 path - transmit pa th control register - byte 0 r/w 0x00 0x0a84 -0x0a92 reserved 0x0a93 transmit tu-3 path - transmit j1 byte value register r/w 0x00 0x0a94 - 0x0a95 reserved 0x0a96 transmit tu-3 path - transmit b3 byte pass thru register r/w 0x00 0x0a97 transmit tu-3 path - transm it b3 byte mask register r/w 0x00 0x0a98 - 0x0a9a reserved 0x0a9b transmit tu-3 path - transm it c2 byte value register r/w 0x00 0x0a9c - 0x0a9e reserved 0x0a9f transmit tu-3 path - transm it g1 byte value register r/w 0x00 0x0aa0 - 0x0aa2 reserved 0x0aa3 transmit tu-3 path - transm it f2 byte value register r/w 0x00 0x0aa4 - 0x0aa6 reserved 0x0aa7 transmit tu-3 path - transm it h4 byte value register r/w 0x00 0x0aa8 - 0x0aaa reserved 0x0aab transmit tu-3 path - transm it z3 byte value register r/w 0x00 0x0aac - 0x0aae reserved 0x0aaf transmit tu-3 path - transm it z4 byte value register r/w 0x00 0x0ab0 - 0x0ab2 reserved 0x0ab3 transmit tu-3 path - transm it z5 byte value register r/w 0x00 0x0ab4 - 0x0ab6 reserved 0x0ab7 transmit tu-3 path - transmit control register - byte 0 r/w 0x00 0x0ab8 - 0x0aba reserved 0x0abb transmit tu-3 path - transmit j1 byte/path trace message control reg - ister r/w 0x00 0x0abc - 0x0abe reserved 0x0abf transmit tu-3 path - transmit arbitrary pointer (h1 byte) value register r/w 0x00 0x0ac0 -0x0ac2 reserved 0x0ac3 transmit tu-3 path - transmit arbitrary pointer (h2 byte) value register r/w 0x00 0x0ac4 - 0x0ac5 reserved
XRT86SH328 preliminary 20 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x0ac6 transmit tu-3 path - current po inter value register - high byte r/o 0x02 0x0ac7 transmit tu-3 path - current po inter value register - low byte r/o 0x0a 0x0ac8 reserved 0x0ac9 transmit tu-3 path - transmit rdi-p control register - byte 2 r/w 0x00 0x0aca transmit tu-3 path - transmit rdi-p control register - byte 1 r/w 0x00 0x0acb transmit tu-3 path - transmit rdi-p control register - byte 0 r/w 0x00 0x0acc - 0x0ace reserved 0x0acf transmit tu-3 path - transmit pa th serial port control register r/w 0x00 0x0ad0 transmit tu-3 path - transmit negati ve pointer adjustment count regis - ter - byte 1 rur 0x00 0x0ad1 transmit tu-3 path - transmit negati ve pointer adjustment count regis - ter - byte 0 rur 0x00 0x0ad2 transmit tu-3 path - transmit positive pointer adjustment count register - byte 1 rur 0x00 0x0ad3 transmit tu-3 path - transmit positive pointer adjustment count register - byte 0 rur 0x00 0x0ad4 - 0xaff reserved r/o 0x00 t able 15: t ransmit tu-3 poh p rocessor b lock - t ransmit p ath t race m essage b uffer a ddress l ocation r egister n ame t ype d efault v alue 0x0b00 - 0x0b3f transmit tu-3 poh processor block - transmit path trace message buffer r/w 0x00 0x0b40 - 0x0bff reserved r/o 0x00 t able 16: vt m apper c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0c00 - 0x0c02 reserved 0x0c03 global control - vt mapper control block - vt mapper block level con - trol register r/w 0x00 0x0c04 - 0x0c05 reserved 0x0c06 global control - vt mapper control block - composite status register r/o 0x00 0x0c07 global control - vt mapper control bl ock - composite status register r/o 0x00 0x0c08 - 0x0c09 reserved t able 14: t ransmit tu-3 poh p rocessor b lock r egisters (sdh/tug-3 a pplications o nly ) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 21 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0c0a global control - vt mapper control block - composite interrupt enable register r/w 0x00 0x0c0b global control - vt mapper control block - composite interrupt enable register r/w 0x00 0x0c0c - 0x0c0d reserved 0x0c0e global control - vt mapper control bloc k - test pattern control register - byte 1 r/w & r/o 0x00 0x0c0f global control - vt mapper control bloc k - test pattern control register - byte 0 r/o 0x00 0x0c10 - 0x0c11 reserved 0x0c12 global control - vt mapper control blo ck - test pattern drop register - byte 1 r/w 0x00 0x0c13 global control - vt mapper control blo ck - test pattern drop register - byte 0 r/w 0x00 0x0c14 - 0x0c15 reserved 0x0c16 global control - vt mapper control bl ock - test pattern detector error register - upper byte rur 0x00 0x0c17 global control - vt mapper control bl ock - test pattern detector error register - lower byte rur 0x00 0x0c18 - 0x0c19 reserved 0x0c1a global control - vt mapper control block - transmit tributary size select register - byte 1 r/w 0x00 0x0c1b global control - vt mapper control block - transmit tributary size select register - byte 0 r/w 0x00 0x0c1c - 0x0c1d reserved 0x0c1e global control - vt mapper control block - receive tributary size select register - byte 1 r/w 0x00 0x0c1f global control - vt mapper control block - receive tributary size select register - byte 0 r/w 0x00 0x0c20 - 0x0d01 reserved t able 17: ds3 m apper c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0d02 ds3 mapper block - control register - byte 1 r/w 0x03 0x0d03 ds3 mapper block - control register - byte 0 r/w 0x00 0x0d04 - 0x0d05 reserved 0x0d06 ds3 mapper block - receive mapper status register - byte 1 r/o 0x03 t able 16: vt m apper c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 22 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x0d07 ds3 mapper block - receive mapper status register - byte 0 r/o 0x00 0x0d08 - 0x0d0a reserved 0x0d0b ds3 mapper block - receive mapper interrupt status register - byte 0 rur 0x00 0x0d0c - 0x0d0d reserved 0x0d0e ds3 mapper block - receive mapper in terrupt enable register - byte 0 r/w 0x00 0x0d0f - 0x0d20 reserved 0x0d21 pointer justification status register - byte 2 r/o 0x00 0x0d22 pointer justification status register - byte 1 r/o 0x00 0x0d23 pointer justification status register - byte 0 r/o 0x00 0x0d24 - 0x0d25 reserved 0x0d26 pointer justification jitter control register - byte 1 r/w 0xc0 0x0d27 pointer justification jitter control register - byte 0 r/w 0x80 0x0d28 - 0x0dff reserved t able 18: ds3 f ramer and m13 mux b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue 0x0e00 ds3 framer and m13 mux block - operating mode register r/w 0x23 0x0e01 ds3 framer and m13 mux block - i/o control register r/w 0xc0 0x0e02 - 0x0e03 reserved 0x0e04 ds3 framer and m13 mux block - block interrupt enable register r/w 0x00 0x0e05 ds3 framer and m13 mux block - block interrupt status register r/o 0x00 0x0e06 reserved r/w 0x00 0x0e07 ds3 framer and m13 mux block - m23 configuration register r/w 0x00 0x0e08 ds3 framer and m13 mux block - m23 transmit ds2 ais register r/w 0x00 0x0e09 ds3 framer and m13 mux block - m23 ds2 loop-back request register r/w 0x00 0x0e0a ds3 framer and m13 mux block - m23 loop-back activation register r/w 0x00 0x0e0b ds3 framer and m13 mux block - m23 mux force ds2 ais command register r/w 0x00 0x0e0c ds3 framer and m13 mux block - ds3 test register # 1 r/w 0x00 0x0e0d reserved r/o 0x00 0x0e0e ds3 framer and m13 mux block - ds3 test register # 2 r/w 0x00 t able 17: ds3 m apper c ontrol r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 23 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0e10 ds3 framer and m13 mux block - receive ds3 configuration & status register r/w 0x10 0x0e11 ds3 framer and m13 mux block - receive ds3 status register r/w 0x00 0x0e12 ds3 framer and m13 mux block - receive ds3 interrupt enable register r/w 0x00 0x0e13 ds3 framer and m13 mux block - receive ds3 interrupt status register rur 0x00 0x0e14 ds3 framer and m13 mux block - receive ds3 sync detect register r/w 0x00 0x0e15 reserved r/o 0x00 0x0e16 s3 framer and m13 mux block - receive ds3 feac register r/o 0x7e 0x0e17 ds3 framer and m13 mux block - receive ds3 feac interrupt enable/status register r/w 0x00 0x0e18 ds3 framer and m13 mux block - receive ds3 lapd control register r/w 0x00 0x0e19 ds3 framer and m13 mux block - receive ds3 lapd status register r/w 0x00 0x0e1a m12 ds2 # 1 configuration register r/w 0x00 0x0e1b ds3 framer and m13 mux block - m 12 configuration register - ds2 channel # 2 r/w 0x00 0x0e1c ds3 framer and m13 mux block - m 12 configuration register - ds2 channel # 3 r/w 0x00 0x0e1d ds3 framer and m13 mux block - m 12 configuration register - ds2 channel # 4 r/w 0x00 0x0e1e ds3 framer and m13 mux block - m 12 configuration register - ds2 channel # 5 r/w 0x00 0x0e1f ds3 framer and m13 mux block - m 12 configuration register - ds2 channel # 6 r/w 0x00 0x0e20 ds3 framer and m13 mux block - m 12 configuration register - ds2 channel # 7 r/w 0x00 0x0e21 ds3 framer and m13 mux block - m12 de-mux force ds1/e1 ais reg - ister - ds2 # channel 1 r/w 0x00 0x0e22 ds3 framer and m13 mux block - m12 ds2 # 2 ais register r/w 0x00 0x0e23 ds3 framer and m13 mux block - m12 ds2 # 3 ais register r/w 0x00 0x0e24 ds3 framer and m13 mux block - m12 ds2 # 4 ais register r/w 0x00 0x0e25 ds3 framer and m13 mux block - m12 ds2 # 5 ais register r/w 0x00 0x0e26 ds3 framer and m13 mux block - m12 ds2 # 6 ais register r/w 0x00 0x0e27 ds3 framer and m13 mux block - m12 ds2 # 7 ais register r/w 0x00 0x0e28 m12 ds2 # 1 loop-back request register r/w 0x00 0x0e29 m12 ds2 # 2 loop- back request register r/w 0x00 0x0e2a m12 ds2 # 3 loop-back request register r/w 0x00 t able 18: ds3 f ramer and m13 mux b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 24 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x0e2b m12 ds2 # 4 loop-back request register r/w 0x00 0x0e2c m12 ds2 # 5 loop-back request register r/w 0x00 0x0e2d m12 ds2 # 6 loop-back request register r/w 0x00 0x0e2e m12 ds2 # 7 loop-back request register r/w 0x00 0x0e2f reserved r/o 0x00 0x0e30 transmit ds3 configuration register r/w 0x00 0x0e31 transmit ds3 feac configuration & status register r/w 0x00 0x0e32 transmit ds3 feac register r/w 0x7e 0x0e33 transmit ds3 lapd configuration register r/w 0x00 0x0e34 transmit ds3 lapd status/interrupt register r/w 0x00 0x0e35 transmit ds3 m-bit mask register r/w 0x00 0x0e36 transmit ds3 f-bit mask register # 1 r/w 0x00 0x0e37 transmit ds3 f-bit mask register # 2 r/w 0x00 0x0e38 transmit ds3 f-bit mask register # 3 r/w 0x00 0x0e39 transmit ds3 f-bit mask register # 4 r/w 0x00 0x0e3a m12 ds2 # 1 framer configuration register r/w 0x00 0x0e3b m12 ds2 # 2 framer configuration register r/w 0x00 0x0e3c m12 ds2 # 3 framer configuration register r/w 0x00 0x0e3d m12 ds2 # 4 framer configuration register r/w 0x00 0x0e3e m12 ds2 # 5 framer configuration register r/w 0x00 0x0e3f m12 ds2 # 6 framer configuration register r/w 0x00 0x0e40 m12 ds2 # 7 framer configuration register r/w 0x00 0x0e41 - 0x0e4b reserved r/o 0x00 0x0e4c transmit ds3 pattern register r/w 0x00 0x0e4d auto t1/e1 ais upon ds3 defect condition register r/w 0x00 0x0e4e pmon exz event count register - msb rur 0x00 0x0e4f pmon exz event count register - lsb rur 0x00 0x0e50 pmon lcv event count register - msb rur 0x00 0x0e51 pmon lcv event count register - lsb rur 0x00 0x0e52 pmon framing bit error count register - msb rur 0x00 0x0e53 pmon framing bit error count register - lsb rur 0x00 0x0e54 pmon p-bit error count register - msb rur 0x00 t able 18: ds3 f ramer and m13 mux b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 25 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0e55 pmon p-bit error count register - lsb rur 0x00 0x0e56 pmon febe count register - msb rur 0x00 0x0e57 pmon febe count register - lsb rur 0x00 0x0e58 pmon cp-bit error count register - msb rur 0x00 0x0e59 pmon cp-bit error count register - lsb rur 0x00 0x0e5a pmon ds2 # 1 framing bit error count register rur 0x00 0x0e5b pmon ds2 # 2 framing bit error count register rur 0x00 0x0e5c pmon ds2 # 3 framing bit error count register rur 0x00 0x0e5d pmon ds2 # 4 framing bit error count register rur 0x00 0x0e5e pmon ds2 # 5 framing bit error count register rur 0x00 0x0e5f pmon ds2 # 6 framing bit error count register rur 0x00 0x0e60 pmon ds2 # 7 framing bit error count register rur 0x00 0x0e61 pmon g.747 # 1 parity bit error count register rur 0x00 0x0e62 pmon g.747 # 2 parity bit error count register rur 0x00 0x0e63 pmon g.747 # 3 parity bit error count register rur 0x00 0x0e64 pmon g.747 # 4 parity bit error count register rur 0x00 0x0e65 pmon g.747 # 5 parity bit error count register rur 0x00 0x0e66 pmon g.747 # 6 parity bit error count register rur 0x00 0x0e67 pmon g.747 # 7 parity bit error count register rur 0x00 0x0e68 prbs bit error count register - msb rur 0x00 0x0e69 prbs bit error count register - lsb rur 0x00 0x0e6a - 0x0e6c reserved 0x0e6d one second error status register r/o 0x00 0x0e6e lcv one second accumulator register - msb r/o 0x00 0x0e6f lcv one second accumulator register - lsb r/o 0x00 0x0e70 frame parity error one second accumulator register - msb r/o 0x00 0x0e71 frame parity error one second accumulator register - lsb r/o 0x00 0x0e72 cp bit error one second accumulator register - msb r/o 0x00 0x0e73 cp bit error one second accumulator register - lsb r/o 0x00 0x0e74 - 0x0e7f reserved r/o 0x00 0x0e80 line interface drive register r/w 0x00 0x0e81 line interface scan register r/w 0x00 t able 18: ds3 f ramer and m13 mux b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 26 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0x0e82 reserved r/o 0x00 0x0e83 transmit ds3 lapd byte count register r/w 0x00 0x0e84 receive ds3 lapd byte count register r/o 0x00 0x0e85 - 0x0e8f reserved 0x0e90 m23 receive ds2 loop-back request interrupt enable register r/w 0x00 0x0e91 m23 receive ds2 loop-back request interrupt status register rur 0x00 0x0e92 m23 receive ds2 loop-back request status register r/o 0x00 0x0e93 m12 ds2 # 1 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0e94 m12 ds2 # 1 loop-back status register r/o 0x00 0x0e95 m12 ds2 # 2 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0e96 m12 ds2 # 2 loop-back status register r/o 0x00 0x0e97 m12 ds2 # 3 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0e98 m12 ds2 # 3 loop-back status register r/o 0x00 0x0e99 m12 ds2 # 4 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0e9a m12 ds2 # 4 loop-back status register r/o 0x00 0x0e9b m12 ds2 # 5 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0e9c m12 ds2 # 5 loop-back status register r/o 0x00 0x0e9d m12 ds2 # 6 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0e9e m12 ds2 # 6 loop-back status register r/o 0x00 0x0e9f m12 ds2 # 7 loop-back interrupt/interrupt enable register r/w, rur 0x00 0x0ea0 m12 ds2 # 7 loop-back status register r/o 0x00 0x0ea1 ds2 # 1 framer interrupt enable register r/w 0x00 0x0ea2 ds2 # 1 framer interrupt status register rur 0x00 0x0ea3 ds2 # 1 framer status register r/o 0x00 0x0ea4 ds2 # 2 framer interrupt enable register r/w 0x00 0x0ea5 ds2 # 2 framer interrupt status register rur 0x00 0x0ea6 ds2 # 2 framer status register r/o 0x00 0x0ea7 ds2 # 3 framer interrupt enable register r/w 0x00 0x0ea8 ds2 # 3 framer interrupt status register rur 0x00 0x0ea9 ds2 # 3 framer status register r/o 0x00 0x0eaa ds2 # 4 framer interrupt enable register r/w 0x00 0x0eab ds2 # 4 framer interrupt status register rur 0x00 t able 18: ds3 f ramer and m13 mux b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 27 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0x0eac ds2 # 4 framer status register r/o 0x00 0x0ead ds2 # 5 framer interrupt enable register r/w 0x00 0x0eae ds2 # 5 framer interrupt status register rur 0x00 0x0eaf ds2 # 5 framer status register r/o 0x00 0x0eb0 ds2 # 6 framer interrupt enable register r/w 0x00 0x0eb1 ds2 # 6 framer interrupt status register rur 0x00 0x0eb2 ds2 # 6 framer status register r/o 0x00 0x0eb3 ds2 # 7 framer interrupt enable register r/w 0x00 0x0eb4 ds2 # 7 framer interrupt status register rur 0x00 0x0eb5 ds2 # 7 framer status register r/o 0x00 0x0eb6 -0x0eb7 reserved 0x0eb8 m13 demux external alarm enable register r/w 0x00 0x0eb9 - 0x0ebf reserved 0x0ec0 lapd memory indirect address register r/w 0x00 0x0ec1 lapd memory indirect data register r/w 0x00 0x0ec2 - 0x0fff reserved r/o 0x00 t able 19: t1/e1 liu c hannel c ontrol r egisters ( where n ranges from 0 x 01 to 0 x 1d) a ddress l ocation r egister n ame t ype d efault v alue 0xn000 t1/e1 liu register - byte 0 - channel 0 r/w 0x00 0xn001 liu channel control register - byte 1 - channel 0 r/w 0x00 0xn002 liu channel control register - byte 2 - channel 0 r/w 0x00 0xn003 liu channel control register - byte 3 - channel 0 r/w 0x00 0xn004 liu channel control register - byte 4 - channel 0 r/w 0x00 0xn005 liu channel control register - byte 5 - channel 0 r/w 0x00 0xn006 liu channel control register - byte 6 - channel 0 r/w 0x00 0xn007 liu channel control register - byte 7 - channel 0 r/w 0x00 0xn008 liu channel control register - byte 8 - channel 0 r/w 0x00 0xn009 liu channel control register - byte 9 - channel 0 r/w 0x00 0xn00a liu channel control register - byte 10 - channel 0 r/w 0x00 0xn00b liu channel control register - byte 11 - channel 0 r/w 0x00 0xn00c liu channel control register - byte 12 - channel 0 r/w 0x00 t able 18: ds3 f ramer and m13 mux b lock r egisters a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 28 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xn00d liu channel control register - byte 13 - channel 0 r/w 0x00 0xn00e liu channel control register - byte 14 - channel 0 r/w 0x00 0xn00f liu channel control register - byte 15 - channel 0 r/w 0x00 0xn010 liu channel control register - byte 16 - channel 0 r/w 0x00 0xn011 liu channel control register - byte 17 - channel 0 r/w 0x00 0xn012 - 0xn0ff reserved t able 20: t1/e1 f ramer b lock c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue 0xn100 clock select register r/w 0x00 0xn101 line interface control register r/w 0x00 0xn102 - 0n106 reserved rur 0xn107 framing select register r/w 0x00 0xn108 alarm generation register r/w 0x00 0xn109 synchronization mux register r/w 0x00 0xn10a transmit signaling and data link select register r/w 0x00 0xn10b framing control register r/w 0x00 0xn10c receive signaling data link select register r/w 0x00 0xn10d receive signaling change register - 0framing control register (e1 appli - cations only) r/w 0x00 0xn10e receive signaling change register - 1 r/w 0x00 0xn10f receive signaling change register - 2 r/w 0x00 0xn110 reserved 0xn111 receive national bits register (e1 applications only) r/w 0x00 0xn112 receive extra bits (e1 applications)r eceive in-sync register (t1 applica - tions) r/w 0x00 0xn113 data link control register r/w 0x00 0xn114 transmit data link byte count register r/w 0x00 0xn115 receive data link byte count register r/w 0x00 0xn116 - 0xn117 reserved 0x1118 dma 0 write configuration register r/w 0x00 0x1119 dma 1 read configuration register r/w 0x00 t able 19: t1/e1 liu c hannel c ontrol r egisters ( where n ranges from 0 x 01 to 0 x 1d) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 29 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0xn11a reserved 0xn11b lapd channel select register (t1 applications) r/w 0x00 0xn11c customer installation alarm generation register r/w 0x00 0xn11d transmit performance report control register r/w 0x00 0xn11e - 0xn11 reserved 0xn120 transmit interface control register r/w 0x00 0xn121 ds1/e1 test register - 2 r/w 0x00 0xn122 receive interface control register r/w 0x00 0xn123 ds1/e1 test register - 1 r/w 0x00 0xn124 loop back code control register - code 0 r/w 0x00 0xn125 transmit loop back code control register r/w 0x00 0xn126 receive loop back code activation control register - code 0 r/w 0x00 0xn127 receive loop back code deactivation control register - code 0 r/w 0x00 0xn129 receive ds1 external alarm enable register r/w 0x00 0xn12a loop-back code control register - code 1 r/w 0x00 0xn12b receive loop back code activation control register - code 1 r/w 0x00 0xn12c receive loop back code deactivation control register - code 1 r/w 0x00 0xn12d loop-back code control register - code 2 r/w 0x00 0xn12e receive loop-back activation code control register - code 2 r/w 0x00 0xn12f receive loop-back deactivation code control register - code 2 r/w 0x00 0xn130 transmit sa select register (e1 applications only) r/w 0x00 0xn131 transmit sa auto control register - byte 1 (e1 applications only) r/w 0x00 0xn132 transmit sa auto control register - byte 2 (e1 applications only) r/w 0x00 0xn133 transmit sa4 register (e1 applications only) r/w 0x00 0xn134 transmit sa5 register (e1 applications only) r/w 0x00 0xn135 transmit sa6 register (e1 applications only) r/w 0x00 0xn136 transmit sa7 register (e1 applications only) r/w 0x00 0xn137 transmit sa8 register (e1 applications only) r/w 0x00 0xn138 - 0xn13a reserved 0xn13b receive sa4 register (e1 applications only) r/w 0x00 0xn13c receive sa5 register (e1 applications only) r/w 0x00 0xn13d receive sa6 register (e1 applications only) r/w 0x00 t able 20: t1/e1 f ramer b lock c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 30 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xn13e receive sa7 register (e1 applications only) r/w 0x00 0xn13f receive sa8 register (e1 applications only) r/w 0x00 0xn140 - 0xn142 reserved 0xn142 transmit sprm control register r/w 0x00 0xn143 - 0xn2ff reserved t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue 0xn300 transmit channel control register - channel 0 r/w 0x00 0xn301 transmit channel control register - channel 1 r/w 0x00 0xn302 transmit channel control register - channel 2 r/w 0x00 0xn303 transmit channel control register - channel 3 r/w 0x00 0xn304 transmit channel control register - channel 4 r/w 0x00 0xn305 transmit channel control register - channel 5 r/w 0x00 0xn306 transmit channel control register - channel 6 r/w 0x00 0xn307 transmit channel control register - channel 7 r/w 0x00 0xn308 transmit channel control register - channel 8 r/w 0x00 0xn309 transmit channel control register - channel 9 r/w 0x00 0xn30a transmit channel control register - channel 10 r/w 0x00 0xn30b transmit channel control register - channel 11 r/w 0x00 0xn30c transmit channel control register - channel 12 r/w 0x00 0xn30d transmit channel control register - channel 13 r/w 0x00 0xn30e transmit channel control register - channel 14 r/w 0x00 0xn30f transmit channel control register - channel 15 r/w 0x00 0xn310 transmit channel control register - channel 16 r/w 0x00 0xn311 transmit channel control register - channel 17 r/w 0x00 0xn312 transmit channel control register - channel 18 r/w 0x00 0xn313 transmit channel control register - channel 19 r/w 0x00 0xn314 transmit channel control register - channel 20 r/w 0x00 0xn315 transmit channel control register - channel 21 r/w 0x00 0xn316 transmit channel control register - channel 22 r/w 0x00 0xn317 transmit channel control register - channel 23 r/w 0x00 t able 20: t1/e1 f ramer b lock c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 31 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0xn318 transmit channel control register - channel 24 (e1 applications only) r/w 0x00 0xn319 transmit channel control register - channel 25 (e1 applications only) r/w 0x00 0xn31a transmit channel control register - channel 26 (e1 applications only) r/w 0x00 0xn31b transmit channel control register - channel 27 (e1 applications only) r/w 0x00 0xn31c transmit channel control register - channel 28 (e1 applications only) r/w 0x00 0xn31d transmit channel control register - channel 29 (e1 applications only) r/w 0x00 0xn31e transmit channel control register - channel 30 (e1 applications only) r/w 0x00 0xn31f transmit channel control register - channel 31 (e1 applications only) r/w 0x00 0xn320 user (idle) code register - channel 0 r/w 0x00 0xn321 user (idle) code register - channel 1 r/w 0x00 0xn322 user (idle) code register - channel 2 r/w 0x00 0xn323 user (idle) code register - channel 3 r/w 0x00 0xn324 user (idle) code register - channel 4 r/w 0x00 0xn325 user (idle) code register - channel 5 r/w 0x00 0xn326 user (idle) code register - channel 6 r/w 0x00 0xn327 user (idle) code register - channel 7 r/w 0x00 0xn328 user (idle) code register - channel 8 r/w 0x00 0xn329 user (idle) code register - channel 9 r/w 0x00 0xn32a user (idle) code register - channel 10 r/w 0x00 0xn32b user (idle) code register - channel 11 r/w 0x00 0xn32c user (idle) code register - channel 12 r/w 0x00 0xn32d user (idle) code register - channel 13 r/w 0x00 0xn32e user (idle) code register - channel 14 r/w 0x00 0xn32f user (idle) code register - channel 15 r/w 0x00 0xn330 user (idle) code register - channel 16 r/w 0x00 0xn331 user (idle) code register - channel 17 r/w 0x00 0xn332 user (idle) code register - channel 18 r/w 0x00 0xn333 user (idle) code register - channel 19 r/w 0x00 0xn334 user (idle) code register - channel 20 r/w 0x00 0xn335 user (idle) code register - channel 21 r/w 0x00 0xn336 user (idle) code register - channel 22 r/w 0x00 0xn337 user (idle) code register - channel 23 r/w 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 32 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xn338 user (idle) code register - c hannel 24 (e1 applications only) r/w 0x00 0xn339 user (idle) code register - c hannel 25 (e1 applications only) r/w 0x00 0xn33a user (idle) code register - c hannel 26 (e1 applications only) r/w 0x00 0xn33b user (idle) code register - c hannel 27 (e1 applications only) r/w 0x00 0xn33c user (idle) code register - c hannel 28 (e1 applications only) r/w 0x00 0xn33d user (idle) code register - c hannel 29 (e1 applications only) r/w 0x00 0xn33e user (idle) code register - c hannel 30 (e1 applications only) r/w 0x00 0xn33f user (idle) code register - c hannel 31 (e1 applications only) r/w 0x00 0xn340 transmit signaling control register - channel 0 r/w 0x00 0xn341 transmit signaling control register - channel 1 r/w 0x00 0xn342 transmit signaling control register - channel 2 r/w 0x00 0xn343 transmit signaling control register - channel 3 r/w 0x00 0xn344 transmit signaling control register - channel 4 r/w 0x00 0xn345 transmit signaling control register - channel 5 r/w 0x00 0xn346 transmit signaling control register - channel 6 r/w 0x00 0xn347 transmit signaling control register - channel 7 r/w 0x00 0xn348 transmit signaling control register - channel 8 r/w 0x00 0xn349 transmit signaling control register - channel 9 r/w 0x00 0xn34a transmit signaling control register - channel 10 r/w 0x00 0xn34b transmit signaling control register - channel 11 r/w 0x00 0xn34c transmit signaling control register - channel 12 r/w 0x00 0xn34d transmit signaling control register - channel 13 r/w 0x00 0xn34e transmit signaling control register - channel 14 r/w 0x00 0xn34f transmit signaling control register - channel 15 r/w 0x00 0xn350 transmit signaling control register - channel 16 r/w 0x00 0xn351 transmit signaling control register - channel 17 r/w 0x00 0xn352 transmit signaling control register - channel 18 r/w 0x00 0xn353 transmit signaling control register - channel 19 r/w 0x00 0xn354 transmit signaling control register - channel 20 r/w 0x00 0xn355 transmit signaling control register - channel 21 r/w 0x00 0xn356 transmit signaling control register - channel 22 r/w 0x00 0xn357 transmit signaling control register - channel 23 r/w 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 33 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0xn358 transmit signaling control register - channel 24 (e1 applications only) r/w 0x00 0xn359 transmit signaling control register - channel 25 (e1 applications only) r/w 0x00 0xn35a transmit signaling control register - channel 26 (e1 applications only) r/w 0x00 0xn35b transmit signaling control register - channel 27 (e1 applications only) r/w 0x00 0xn35c transmit signaling control register - channel 28 (e1 applications only) r/w 0x00 0xn35d transmit signaling control register - channel 29 (e1 applications only) r/w 0x00 0xn35e transmit signaling control register - channel 30 (e1 applications only) r/w 0x00 0xn35f transmit signaling control register - channel 31 (e1 applications only) r/w 0x00 0xn360 receive channel control register - channel 0 r/w 0x00 0xn361 receive channel control register - channel 1 r/w 0x00 0xn362 receive channel control register - channel 2 r/w 0x00 0xn363 receive channel control register - channel 3 r/w 0x00 0xn364 receive channel control register - channel 4 r/w 0x00 0xn365 receive channel control register - channel 5 r/w 0x00 0xn366 receive channel control register - channel 6 r/w 0x00 0xn367 receive channel control register - channel 7 r/w 0x00 0xn368 receive channel control register - channel 8 r/w 0x00 0xn369 receive channel control register - channel 9 r/w 0x00 0xn36a receive channel control register - channel 10 r/w 0x00 0xn36b receive channel control register - channel 11 r/w 0x00 0xn36c receive channel control register - channel 12 r/w 0x00 0xn36d receive channel control register - channel 13 r/w 0x00 0xn36e receive channel control register - channel 14 r/w 0x00 0xn36f receive channel control register - channel 15 r/w 0x00 0xn370 receive channel control register - channel 16 r/w 0x00 0xn371 receive channel control register - channel 17 r/w 0x00 0xn372 receive channel control register - channel 18 r/w 0x00 0xn373 receive channel control register - channel 19 r/w 0x00 0xn374 receive channel control register - channel 20 r/w 0x00 0xn375 receive channel control register - channel 21 r/w 0x00 0xn376 receive channel control register - channel 22 r/w 0x00 0xn377 receive channel control register - channel 23 r/w 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 34 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xn378 receive channel control register - channel 24 r/w 0x00 0xn379 receive channel control register - channel 25 r/w 0x00 0xn37a receive channel control register - channel 26 r/w 0x00 0xn37b receive channel control register - channel 27 r/w 0x00 0xn37c receive channel control register - channel 28 r/w 0x00 0xn37d receive channel control register - channel 29 r/w 0x00 0xn37e receive channel control register - channel 30 r/w 0x00 0xn37f receive channel control register - channel 31 r/w 0x00 0xn380 receive user code register - channel 0 r/w 0x00 0xn381 receive user code register - channel 1 r/w 0x00 0xn382 receive user code register - channel 2 r/w 0x00 0xn383 receive user code register - channel 3 r/w 0x00 0xn384 receive user code register - channel 4 r/w 0x00 0xn385 receive user code register - channel 5 r/w 0x00 0xn386 receive user code register - channel 6 r/w 0x00 0xn387 receive user code register - channel 7 r/w 0x00 0xn388 receive user code register - channel 8 r/w 0x00 0xn389 receive user code register - channel 9 r/w 0x00 0xn38a receive user code register - channel 10 r/w 0x00 0xn38b receive user code register - channel 11 r/w 0x00 0xn38c receive user code register - channel 12 r/w 0x00 0xn38d receive user code register - channel 13 r/w 0x00 0xn38e receive user code register - channel 14 r/w 0x00 0xn38f receive user code register - channel 15 r/w 0x00 0xn390 receive user code register - channel 16 r/w 0x00 0xn391 receive user code register - channel 17 r/w 0x00 0xn392 receive user code register - channel 18 r/w 0x00 0xn393 receive user code register - channel 19 r/w 0x00 0xn394 receive user code register - channel 20 r/w 0x00 0xn395 receive user code register - channel 21 r/w 0x00 0xn396 receive user code register - channel 22 r/w 0x00 0xn397 receive user code register - channel 23 r/w 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 35 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0xn398 receive user code register - channel 24 r/w 0x00 0xn399 receive user code register - channel 25 r/w 0x00 0xn39a receive user code register - channel 26 r/w 0x00 0xn39b receive user code register - channel 27 r/w 0x00 0xn39c receive user code register - channel 28 r/w 0x00 0xn39d receive user code register - channel 29 r/w 0x00 0xn39e receive user code register - channel 30 r/w 0x00 0xn39f receive user code register - channel 31 r/w 0x00 0xn3a0 receive signaling control register - channel 0 r/w 0x00 0xn3a1 receive signaling control register - channel 1 r/w 0x00 0xn3a2 receive signaling control register - channel 2 r/w 0x00 0xn3a3 receive signaling control register - channel 3 r/w 0x00 0xn3a4 receive signaling control register - channel 4 r/w 0x00 0xn3a5 receive signaling control register - channel 5 r/w 0x00 0xn3a6 receive signaling control register - channel 6 r/w 0x00 0xn3a7 receive signaling control register - channel 7 r/w 0x00 0xn3a8 receive signaling control register - channel 8 r/w 0x00 0xn3a9 receive signaling control register - channel 9 r/w 0x00 0xn3aa receive signaling control register - channel 10 r/w 0x00 0xn3ab receive signaling control register - channel 11 r/w 0x00 0xn3ac receive signaling control register - channel 12 r/w 0x00 0xn3ad receive signaling control register - channel 13 r/w 0x00 0xn3ae receive signaling control register - channel 14 r/w 0x00 0xn3af receive signaling control register - channel 15 r/w 0x00 0xn3b0 receive signaling control register - channel 16 r/w 0x00 0xn3b1 receive signaling control register - channel 17 r/w 0x00 0xn3b2 receive signaling control register - channel 18 r/w 0x00 0xn3b3 receive signaling control register - channel 19 r/w 0x00 0xn3b4 receive signaling control register - channel 20 r/w 0x00 0xn3b5 receive signaling control register - channel 21 r/w 0x00 0xn3b6 receive signaling control register - channel 22 r/w 0x00 0xn3b7 receive signaling control register - channel 23 r/w 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 36 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xn3b8 receive signaling control register - channel 24 r/w 0x00 0xn3b9 receive signaling control register - channel 25 r/w 0x00 0xn3ba receive signaling control register - channel 26 r/w 0x00 0xn3bb receive signaling control register - channel 27 r/w 0x00 0xn3bc receive signaling control register - channel 28 r/w 0x00 0xn3bd receive signaling control register - channel 29 r/w 0x00 0xn3be receive signaling control register - channel 30 r/w 0x00 0xn3bf receive signaling control register - channel 31 r/w 0x00 0xn3c0 receive substitution signaling register - channel 0 r/w 0x00 0xn3c1 receive substitution signaling register - channel 1 r/w 0x00 0xn3c2 receive substitution signaling register - channel 2 r/w 0x00 0xn3c3 receive substitution signaling register - channel 3 r/w 0x00 0xn3c4 receive substitution signaling register - channel 4 r/w 0x00 0xn3c5 receive substitution signaling register - channel 5 r/w 0x00 0xn3c6 receive substitution signaling register - channel 6 r/w 0x00 0xn3c7 receive substitution signaling register - channel 7 r/w 0x00 0xn3c8 receive substitution signaling register - channel 8 r/w 0x00 0xn3c9 receive substitution signaling register - channel 9 r/w 0x00 0xn3ca receive substitution signaling register - channel 10 r/w 0x00 0xn3cb receive substitution signaling register - channel 11 r/w 0x00 0xn3cc receive substitution signaling register - channel 12 r/w 0x00 0xn3cd receive substitution signaling register - channel 13 r/w 0x00 0xn3ce receive substitution signaling register - channel 14 r/w 0x00 0xn3cf receive substitution signaling register - channel 15 r/w 0x00 0xn3d0 receive substitution signaling register - channel 16 r/w 0x00 0xn3d1 receive substitution signaling register - channel 17 r/w 0x00 0xn3d2 receive substitution signaling register - channel 18 r/w 0x00 0xn3d3 receive substitution signaling register - channel 19 r/w 0x00 0xn3d4 receive substitution signaling register - channel 20 r/w 0x00 0xn3d5 receive substitution signaling register - channel 21 r/w 0x00 0xn3d6 receive substitution signaling register - channel 22 r/w 0x00 0xn3d7 receive substitution signaling register - channel 23 r/w 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 37 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0xn3d8 - 0xn3ff reserved 0xn400 - 0xn4ff reserved r/o 0x00 t able 22: r eceive s ignaling r egister a rray r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue 0xn500 receive signaling register array - channel 0 r/o 0x00 0xn501 receive signaling register array - channel 1 r/o 0x00 0xn502 receive signaling register array - channel 2 r/o 0x00 0xn503 receive signaling register array - channel 3 r/o 0x00 0xn504 receive signaling register array - channel 4 r/o 0x00 0xn505 receive signaling register array - channel 5 r/o 0x00 0xn506 receive signaling register array - channel 6 r/o 0x00 0xn507 receive signaling register array - channel 7 r/o 0x00 0xn508 receive signaling register array - channel 8 r/o 0x00 0xn509 receive signaling register array - channel 9 r/o 0x00 0xn50a receive signaling register array - channel 10 r/o 0x00 0xn50b receive signaling register array - channel 11 r/o 0x00 0xn50c receive signaling register array - channel 12 r/o 0x00 0xn50d receive signaling register array - channel 13 r/o 0x00 0xn50e receive signaling register array - channel 14 r/o 0x00 0xn50f receive signaling register array - channel 15 r/o 0x00 0xn510 receive signaling register array - channel 16 r/o 0x00 0xn511 receive signaling register array - channel 17 r/o 0x00 0xn512 receive signaling register array - channel 18 r/o 0x00 0xn513 receive signaling register array - channel 19 r/o 0x00 0xn514 receive signaling register array - channel 20 r/o 0x00 0xn515 receive signaling register array - channel 21 r/o 0x00 0xn516 receive signaling register array - channel 22 r/o 0x00 0xn517 receive signaling register array - channel 23 r/o 0x00 0xn518 receive signaling register array - channel 24 r/o 0x00 t able 21: t ransmit c hannel c ontrol r egisters ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 38 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xn519 receive signaling register array - channel 25 r/o 0x00 0xn51a receive signaling register array - channel 26 r/o 0x00 0xn51b receive signaling register array - channel 27 r/o 0x00 0xn51c receive signaling register array - channel 28 r/o 0x00 0xn51d receive signaling register array - channel 29 r/o 0x00 0xn51e receive signaling register array - channel 30 r/o 0x00 0xn51f receive signaling register array - channel 31 r/o 0x00 0xn520 - 0xn59f reserved 0xn5a0 receive signaling control registers - channel 0 r/w 0x00 0xn5a1 receive signaling control registers - channel 1 r/w 0x00 0xn5a2 receive signaling control registers - channel 2 r/w 0x00 0xn5a3 receive signaling control registers - channel 3 r/w 0x00 0xn5a4 receive signaling control registers - channel 4 r/w 0x00 0xn5a5 receive signaling control registers - channel 5 r/w 0x00 0xn5a6 receive signaling control registers - channel 6 r/w 0x00 0xn5a7 receive signaling control registers - channel 7 r/w 0x00 0xn5a8 receive signaling control registers - channel 8 r/w 0x00 0xn5a9 receive signaling control registers - channel 9 r/w 0x00 0xn5aa receive signaling control registers - channel 10 r/w 0x00 0xn5ab receive signaling control registers - channel 11 r/w 0x00 0xn5ac receive signaling control registers - channel 12 r/w 0x00 0xn5ad receive signaling control registers - channel 13 r/w 0x00 0xn5ae receive signaling control registers - channel 14 r/w 0x00 0xn5af receive signaling control registers - channel 15 r/w 0x00 0xn5b0 receive signaling control registers - channel 16 r/w 0x00 0xn5b1 receive signaling control registers - channel 17 r/w 0x00 0xn5b2 receive signaling control registers - channel 18 r/w 0x00 0xn5b3 receive signaling control registers - channel 19 r/w 0x00 0xn5b4 receive signaling control registers - channel 20 r/w 0x00 0xn5b5 receive signaling control registers - channel 21 r/w 0x00 0xn5b6 receive signaling control registers - channel 22 r/w 0x00 0xn5b7 receive signaling control registers - channel 23 r/w 0x00 t able 22: r eceive s ignaling r egister a rray r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 39 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 0xn5b8 - 0xn5ff reserved 0xn600 - 0xn640 lapd buffer 0 control register (64-bytes) r/w 0x00 0xn700 - 0xn740 lapd buffer 1 control register (64-bytes) r/w 0x00 0xn741 - 0xn8ff reserved t able 23: t1/e1 p erformance m onitor r egister ( where n ranges value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue 0xn900 t1 receive line code violation count register (msb) rur 0x00 0xn901 t1 receive line code violation count register (lsb) rur 0x00 0xn902 t1/e1 receive frame alignment error count register - msb rur 0x00 0xn903 t1/e1 receive frame alignment error count register (lsb) rur 0x00 0xn904 t1/e1 receive severely erred frame count register rur 0x00 0xn905 t1/e1 receive synchronization bi t error count register - msb rur 0x00 0xn906 t1/e1 receive synchronization bi t error count register - lsb rur 0x00 0xn907 t1/e1 receive febe event count register - msb rur 0x00 0xn908 t1/e1 receive febe event count register - lsb rur 0x00 0xn909 t1/e1 receive slip event count register rur 0x00 0xn90a t1/e1 receive loss of frame count register rur 0x00 0xn90b t1/e1 receive change of frame count register rur 0x00 0xn90c lapd frame check sequence error count register rur 0x00 0xn90d t1/e1 prbs bit error count register - msb rur 0x00 0xn90e t1/e1 prbs bit error count register - lsb rur 0x00 0xn90f t1/e1 transmit slip event count register rur 0x00 0xn910 - 0xnaff reserved t able 24: t1/e1 f ramer b lock i nterrupt r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue 0xnb00 t1/e1 framer block interrupt enable register r/w 0x00 0xnb01 t1/e1 framer block interrupt status register r/o 0x00 0xnb02 alarm and error status register rur 0x00 0xnb03 alarm and error interr upt enable register r/w 0x00 t able 22: r eceive s ignaling r egister a rray r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue
XRT86SH328 preliminary 40 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 0xnb04 framer interrupt enable register r/w 0x00 0xnb05 framer interrupt status register rur 0x00 0xnb06 data link interrupt status register rur 0x00 0xnb07 data link interrupt enable register 0xnb0a receive loop back code interrupt & status register - code 0 r/w 0x00 0xnb0b receive loop back code interrupt enable register - code 0 r/w 0x00 0xnb0c - 0xnb0d reserved 0xnb0e excessive zero interru pt status register rur 0x00 0xnb0f excessive zero interru pt enable register rur 0x00 0xnb10 receive sa interrupt enable register (e1 applications)ss7 interrupt sta - tus register - lapd # 1 (t1 applications) r/w 0x00 0xnb11 receive sa interrupt enable regist er (e1 applications)ss7 interrupt enable register - lapd # 1 (t1 applications) r/w 0x00 0xnb12 - 0xnb13 reserved 0xnb14 receive loop-back code interrupt status register - code 1 rur v0x00 oxnb15 receive loop-back code interrupt enable register - code 1 r/w 0x00v 0xnb16 - 0xnb17 reserved 0xnb18 ss7 interrupt status register - lapd # 2 (t1 applications) r/w 0x00 0xnb19 ss7 interrupt enable register - lapd # 2 (t1 applications) r/w 0xnb1a receive loop-back code interrupt status register - code 2 rur 0x00 0xnb1b receive loop-back code interrupt enable register - code 2 r/w 0x00 0xnb1c - 0xnb27 reserved 0xnb28 ss7 interrupt status register - lapd # 3 (t1 applications) r/w 0x00 0xnb29 ss7 interrupt enable register - lapd # 3 (t1 applicaions) r/w 0x00 0xnb30 - 0xnb3f reserved 0xnb40 customer installation alarm status register rur 0x00 0xnb41 customer installation alarm interrupt enable register r/w 0x00 0xnb42 - 0xncff reserved r/o 0x00 t able 24: t1/e1 f ramer b lock i nterrupt r egisters ( where n ranges in value from 0 x 01 to 0 x 38) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 41 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications t able 25: vt m apper r egister ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue 0xnd00 - 0xnd41 reserved 0xnd42 channel control - vt mapper block - ingress direction - ds1/e1 insertion control register - byte 1 r/o & r/w 0x00 0xnd43 channel control - vt-mapper block - i ngress direction - ds1/e1 insertion control register - byte 0 r/w 0x00 0xnd44 channel control - vt-de-mapper block - egress direction - ds1/e1 drop control register - byte 3 r/w 0x00 0xnd45 channel control - vt-de-mapper block - egress direction - ds1/e1 drop control register - byte 2 r/w 0x00 0xnd46 channel control - vt-de-mapper block - egress direction - ds1/e1 drop control register - byte 1 r/o 0x10 0xnd47 channel control - vt de-mapper block - egress direction - ds1/e1 drop control register - byte 0 r/o & r/w 0x00 0xnd48 - 0xnd49 reserved 0xnd4a channel control - vt de-mapper blo ck - egress direction - bip-2 error count register - byte 1 rur 0x00 0xnd4b channel control - vt de-mapper blo ck - egress direction - bip-2 error count register - byte 0 rur 0x00 0xnd4c - 0xnd4d reserved 0xnd4e channel control - vt de-mapper blo ck - egress direction - rei-v event count register - byte 1 rur 0x00 0xnd4f channel control - vt-de-mapper blo ck - egress direction - rei-v event count register - byte 0 rur 0x00 0xnd50 - 0xnd52 reserved 0xnd53 channel control - vt-de-mapper blo ck - egress direction - receive aps register - byte 0 r/w 0x00 0xnd54 - 0xnd55 reserved 0xnd56 channel control - vt-mapper block - ingress direction - transmit aps register - byte 1 r/w 0x00 0xnd57 channel control - vt-mapper block - ingress direction - transmit aps/k4 register - byte 0 r/w 0x00 0xnd58 - 0xnd62 reserved 0xnd63 channel control - vt-de-mapper block- egress direction - j2 byte status register - byte 0 r/o 0x00 0xnd64 channel control - vt-de-mapper blo ck - egress direction - composite status register - byte 1 rur 0x00 0xnd65 channel control - vt-de-mapper block - egress direction -composite sta - tus register - byte 0 rur 0x00
XRT86SH328 preliminary 42 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 2.0 register descriptions the remainder of this document use regist er descriptions with the folowing format: 8-bit register table bit descriptions bit 7 - bit name bit description ` 0 - logic low condition ` 1 - logic high condition n ote : speial notes bit [6:0] - bit name 0xnd66 reserved rur 0x00 0xnd67 channel control - vt-de-mapper block - egress direction - interrupt sta - tus register - byte 0 rur 0x00 0xnd68 channel control - vt-de-mapper block - egress direction - interrupt enable register r/w 0x00 0xnd69 channel control - vt-de-mapper - block - egress direction - interrupt enable register r/w 0x00 0xnd6a reserved r/w 0x00 0xnd6b channel control - vt-de-mapper block - egress direction -interrupt enable register - byte 0 r/w 0x00 0xnd6c - 0xnd70 reserved 0xnd71 channel control - vt-de-mapper block - egress direction - vt path trace buffer control register r/w 0x00 0xnd72 channel control - vt-de-mapper block - egress direction - auto ais con - trol register - byte 1 r/w 0x00 0xnd73 channel control vt de-mapper block - egress direction - auto ais con - trol register - byte 0 r/w 0x00 0xnd74 - 0xnd75 reserved 0xnd76 channel control - vt-mapper block - ingress direction - transmit j2 byte value register r/w 0x00 0xnd77 channel control - vt mapper block - ingress direction - transmit n2 byte value register r/w 0x00 t able 26: o peration c ontrol r egister - b yte 3 (a ddress = 0 x 0000) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name bit name bit name bit name bit name bit name bit name bit name r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 25: vt m apper r egister ( where n ranges in value from 0 x 01 to 0 x 1c) a ddress l ocation r egister n ame t ype d efault v alue
preliminary XRT86SH328 43 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 2.1 operation control registers bit7 - unused bit6 - ingress direction add-drop interface enable: this read/write bit-field is used to either enable or disable the ingress direction add-drop interface. if the ingress direction add-drop interface is enabled, then th e ingress direction drop port will drop out the entire traffic (of all 28 channels in the ingress direction) via the ig_te1r xdata[7:0] output pins. additi onally, the user can add in of the 28 ds1 or 21 e1 ingress direction signals via the ingress direction add port. ` 0 - disables the ingress dir ection add-drop interface. ` 1 - enables the ingress direction add-drop interface. n ote : this feature is only available if the XRT86SH328 has been configured to operate in either of the following modes. ? the vt-mapper mode (w/ t1/e1 framing) ? the m13 mux mode (w/ t1/e1 framing) ? the m13 mux to sts-1/sts-3 mode ? the transmux mode bit 5 - egress direction add-drop interface enable: this read/write bit-field is used to either enable or disable the egress direction add-drop interface. if the user enables the egress direction add-drop interface, then the egress direction drop port will drop out the entire traffic (of all 28 channels in the egress direction) via the eg_te1rxdata[7:0] output pins. additionally, the user can add in any of the 28 ds1 or 21 e1 egress direction signals via the egress direction add interface. ` 0 - disables the egress direction add-drop interface. ` 1 - enables the egress direction add-drop interface. n ote : this feature is only available if the XRT86SH328 has been configured to operate in either of the following modes. ? the vt-mapper mode (w/ t1/e1 framing) ? the m13 mux mode (w/ t1/e1 framing) ? the m13 mux to sts-1/sts-3 mode ? the transmux mode bit 4 - parallel interface enable n ote : this bit-field is only valid if the XRT86SH328 has been configured to operate in th e 28-channel ds1/e1 framer & liu mode. bit[3:0] - mode select bits[3:0]: these four read/write bit-fields are us ed to select the mode that the xrt86s h328 will operate in, as shown in the table below below. t able 27: o peration c ontrol r egister - b yte 3 (a ddress = 0 x 0000) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused ingress direction add-drop interface enable egress direction add-drop interface enable parallel interface enable mode_select[3:0] r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 44 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:3] - unused please set to 0 for normal operation. bit 2 - interrupt wr ite to clear/rur this read/write bit-field is used to configure all of the source-level interrupt status bits (within the XRT86SH328) to either be write to clear (wtc ) or reset-upon-read (rur) bits. ` 0 - configures all source-level interrupt status register bits to functi on as reset-upon-read (rur). ` 1 - configures all source-level in terrupt status register bits to function as write-to-clear (wtc) bit 1 - enable interrupt clear this read/write bit-field is used to c onfigure the xrt94l43 to aut omatically disable all inte rrupts that are activated. ` 0 - configures the chip to not automatically disable any interrupts following their activation. ` 1 - configures the chip to automatically disable all interrupts following their activation. bit 0 - interrupt enable this read/write bit-field is used to configure the xrt94l 43 to generate interrupt requests to the microprocessor. ` 0 - configures the chip to not gener ate interrupt to th e microprocessor. all interrupts are disabled and the micropr ocessor must poll the register bits. ` 1 - configures the chip to generate interrupts to the microprocessor. mode select bits m ode _s elect [3:0] r esulting m ode of o peration 0000 vt-mapper mode (w/ t1/e1 framing) 0001 m13 mux mode (w/ t1/e1 framing 0010 m13 mux to sts-1/sts-3 mode 0011 reserved 0100 28 channel t1/e1 framer & liu mode 0101 transmux mode (w/ t1/e1 framing) 0110 & 0111 reserved 1000 vt-mapper mode (w t1/e1 framers by-passed) 1001 m13 mux mode (w/ t1/e1 framers by-passed) 1010 m13 mux to sts-1/sts-3 mode (w/ t1/e1 framers by-passed) 1011 reserved 1100 28 channel t1/e1 liu mode 1101 transmux mode (w/ t1/e1 framers by-passed) t able 28: o peration c ontrol r egister - b yte 2 (a ddress = 0 x 0001) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused interrupt write clear/rur enable interrupt clear interrupt enable r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 45 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : to operate the xrt986sh328 in an interrupt-driven manner, this bit-field must be set to a logic 1. bit7 - reserved bit6 - receive clock detect this read/write bit-field is used to enable or disable the rece ive clock detect feature. if this feature is enabled, then the receive sts-1/sts-3 circuitry will check for the existenc e of the 6.48mhz or 19.44mhz clock signal (through the receive sts-1/sts-3 telecom bus interface). if none of t hese clock signals are present, then the receive sts-1/sts-3 toh processor block and each of the 1 (or 3) receive sonet poh processor block circuitry will automatically switch over and use the 19.44mhz clock signal that is applied to th e tx19_51mhz input pin (ball r3) as there timing source. ` 0 - disables the receive clock detect feature. ` 1 - enables the receive clock detect feature. bit [5:4] = reserved bit 3 - burst enable this read/write bit-field is used to either enable or di sable burst mode operation within the microprocessor interface. ` 0 - disables burst mode operation. ` 1 - enables burst mode operation bit 2 - bit 1 - reserved bit 0 - swreset - sonet block this read/write bit-field is used to command a software re set to the sonet/sdh block. if a software reset to the sonet/sdh blocks is invoked, then all of the internal state machines will be reset to their default conditions and each of the following blocks will undergo a re-frame operation. ? the receive sts-1/3 toh processor block ? each of the three (3) receiv e sonet poh processor blocks ? each of the three (3) vt mapper blocks a 0 to 1 transition, within this bit-field commands this software reset. n ote : this software reset does not reset the command registers to their default state. this can only be achieved by executing a hardware reset (e.g., by pu lling the reset_l* input pin low). bit [7:0] - device id value this read-only bit-field is set to the value 0x50 and is used' s software code to uniquely identify this device as being the XRT86SH328. t able 29: o peration c ontrol r egister - b yte 0 (a ddress = 0 x 0003) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved receive clock detect reserved burst enable reserved swreset r/w r/w r/o r/o r/w r/o r/o r/w 0 1 0 0 0 0 0 0 t able 30: d evice id v alue r egister - b yte 3 (a ddress = 0 x 0004) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device id value r/o r/o r/o r/o r/o r/o r/o r/o 0 1 0 1 0 0 0 0
XRT86SH328 preliminary 46 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - revisi on number value this read-only bit-field is set to the value that corresponds to its revision number. revision a silicon will be set to the value 0x01. this register is uses software code to uniquely identify the revision number of this device bit [7:1] - unused please set to 0 for normal operation bit 0 - telecom bus parity error interrupt status this reset-upon-read bit-field indicates whether or no t the detection of 51.84/155. 52mbps telecom bus - parity error interrupt has occurred since t he last read of this register bit. ` 0 - indicates that the detection of 51.84/155.52mbps telecom bus - parity error interrupt has not occurred since the last read of this register bit. ` 1 - indicates that the detection of 51. 84/155.52mbps telecom bus - parity error interrupt has occurred since the last of this register bit. n ote : this register bit is only active if the XRT86SH328 has been configured to operate in the telecom bus mode. bit [7:1] - unused please set to 0 for normal operation bit 0 - telecom bus parity error interrupt enable this read/write bit-field is used to either enable or disa ble the detection of 51.84/155.52mbps telecom bus - parity error interrupt. ` 0 - disables the detection of 51.84/155.52mbps telecom bus - parity error interrupt. ` 1 - enables the detection of 51.84/155.52mbps telecom bus - pa rity error interrupt.note: this register bit is only active if the XRT86SH328 has been config ured to operate in the telecom bus mode. t able 31: r evision n umber v alue r egister - b yte 2 (a ddress = 0 x 0005) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 revision number value r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 1 t able 32: o peration i nterrupt s tatus r egister - b yte 0 (a ddress = 0 x 000b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused tb parity error interrupt status r/o r/o r/o r/o r/o r/o r/o rur/wtc 0 0 0 0 0 0 0 0 t able 33: o peration i nterrupt e nable r egister - b yte 0 (a ddress = 0 x 000f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused telecom busparity error interrupt enable r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 47 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - operation control block interrupt status this read-only bit-field indicates whether or not an oper ation control block-related in terrupt is awaiting service. ` 0 - no operation control block interrupts are awaiting service. ` 1 - at least one operation control block interrupt is awaiting service. bit 6- ds3 mapper block interrupt status this read-only bit-field indicates whether or not a mapper block-related interrupt is awaiting service. ` 0 - no mapper block interrupt is awaiting service. ` 1 - at least one mapper block interrupt is awaiting service. bit 5 - vt mapper block interrupt status this read-only bit-field indicates whether or not a vt-mapper block interrupt is awaiting service. ` 0 - indicates that no vt mapper block interrupt is awaiting service. ` 1 - indicates that at least one vt mapper block interrupt is awaiting service. bit 4 - ds1/e1 framer/liu bl ock (vt side) interrupt status this read-only bit-field indicates whether or not a ds1/e1 framer/liu block (on the vt side) interrupt is awaiting service. ` 0 - indicates that no ds1/e1 framer block (vt side) interrupt is awaiting service. ` 1 - at least one ds1/e1 framer/liu block (vt side) interrupt is awaiting service. bit 3 - ds1/e1 framer/liu block (m13 side) interrupt status this read-only bit-field indicates whether or not a ds1/e1 framer/liu block (m13 side) interrupt is awaiting service. ` 0 - no ds1/e1 framer/liu block (m13 side) interrupt is awaiting service. ` 1 - at least one ds1/e1 framer/liu (m13 side) interrupt is awaiting service. bit 2 - ds3/e3 framer block interrupt status this read-only bit-field indicates whether or not a ds3/e3 framer block interrupt is awaiting service. ` 0 - no ds3/e3 framer block interrupt is awaiting service. ` 1 - at least one ds3/e3 framer block interrupt is awaiting service. bit 1:0 - unused t able 34: o peration b lock i nterrupt s tatus r egister - b yte 1 (a ddress = 0 x 0012) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op control block interrupt status ds3 mapper block interrupt status vt mapper block interrupt status ds1/e1 framer/liu block (vt side) interrupt status ds1/e1 framer/liu block (m13 side) interrupt status ds3/e3 framer block nterrupt status receive line interface block interrupt status transmit line interface block interrupt status r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 48 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - unused bit 6 - receive sts-1/st3-3toh processor block interrupt status this read-only bit-field indicates whether or not a receiv e sts-1/sts-3 toh processor block interrupt is awaiting service. ` 0 - no receive sts-1/sts-3 toh processor block interrupt is awaiting service. ` 1 - at least one receive sts-1/sts-3 toh proc essor block interrupt is awaiting service. bit 5 - receive sts-1/sts-3 poh pr ocessor block interrupt status this read-only bit-field indicates whether or not a rece ive sts-1/sts-3 poh processor block interrupt is awaiting service. ` 0 - no receive sts-1/sts-3 poh processo r block interrupt is awaiting service. ` 1 - at least one receive sts-1/sts-3 poh proc essor block interrupt is awaiting service. bit [4:3] - unused bit 2 - external interrupt in put pin # 1 - interrupt status this read-only bit-field indicates whether or not an external interrupt input pin # 1 interrupt is awaiting service, as described below. ` 0 - no external interrupt input pin # 1 interrupt is awaiting service. ` 1 - the external interrupt input pin # 1 interrupt is awaiting service. n ote : if this interrupt is enabled, then the XRT86SH328 will generate this interrupt anyt ime that the ext_int_1 input pin (ball t5) has been driven to the logic high level. bit [1:0] - unused bit 7 - operation control block interrupt enable this read/write bit-field is used to either enable or disabl e the operation control block fo r interrupt generation. if a 0 is written to this register bit and if the operation control block (for interrupt generation) is disabled, then all operation control block interrupts will be disabled for interrupt generation. if a 1 is written to this register bit, the individual operation control block inte rrupt(s) at the source level will still nee d t able 35: o peration b lock i nterrupt s tatus r egister - b yte 0 (a ddress = 0 x 0013) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused receive sts-1/sts-3 toh block interrupt status receive sts-1/sts-3 poh block interrupt status unused external interrupt sta - tus # 1 unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 36: o peration b lock i nterrupt e nable r egister - b yte 1 (a ddress = 0 x 0016) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op control block interrupt enable ds3mapper block interrupt enable vt mapper block interrupt enable ds1/e1 framer/liu block (vt side) interrupt enable ds1/e1 framer/liu block (m13 side) interrupt enable ds3framer block nterrupt enable unused r/w r/w r/w r/w r/w r/w r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 49 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications to be enabled in order to enable that particular interrupt ` .0 - disable all operation control block interrupts within the device. ` 1 - enables the operation control block at the block-level for interrupt generation bit 6 - ds3 mapper block interrupt enable this read/write bit is used to either enable or disable the ds 3 mapper block for interrupt generation. if a 0 is written to this register bit and if the ds3 mapper block (for interrupt generation) is disa bled, then all ds3 mapper block interrupts will be disabled for interrupt generation. if a 1is written to this register bit, the individual ds3 ma pper block interrupt(s) at the source levelwill still need to be enabled in order to enable that particular interrupt. ` 0 - disable all ds3 mapper block interrupts within the device. ` 1 - enables the ds3 mapper blo ck interrupts at the block-level bit 5 - vt mapper bl ock interrupt enable this read/write bit-field is used to ei ther enable or disable the vt-mapper block for interrupt generation. if the user writes a 0 into this register bit and disables the vt mapper block (for interrupt generation) then all vt-mapper block interrupts will be disabled for interrupt generation. if the user writes a 1 into this register bit, the user will still need to enable the individual vt-mapper block interrupt(s) at the source level in order to enable that particular interrupt. ` 0 - disables all vt mapper block interrupts within the device. ` 1 - enables the vt mapper block interrupts at the block-level bit 4- ds1/e1 framer/liu block (vt side) interrupt enable this read/write bit is used to either enable or disable the ds1/e1 framer/liu block (on the vt side) for interrupt generation. if the user writes a 0 to this regist er bit and disables the ds1/e1 framer/l iu block (on the vt side) for interrupt generation, then all ds1/e1 framer/liu block inte rrupts will be disabled for interrupt generation. if the user writes a 1 to this register bit, the user will still need to enable the individual ds1/e1 framer/liu block interrupt(s) at the source level in or der to enable that particular interrupt. ` 0 - disable all ds1/e1 framer/liu block interrupts within the device. ` 1 - enables the ds1/e1 framer/liu block at the block-level. bit 3 - ds1/e1 framer/liu block (m13 side) interrupt enable this read/write bit is used to either enable or disable th e ds1/e1 framer/liu block (on the m13 side) for interrupt generation. if the user writes a 0 to this register bit and disables the ds1/e1 framer/liu block (for interrupt generation), then all ds1/e1 framer/liu block interrupts will be disabled for interrupt generation. if the user writes a 1 to this register bit, the user will still need to enable the individual ds1/e1 framer/liu block interrupt(s) at the source level in or der to enable that particular interrupt. ` 0 - disable all ds1/e1 framer/liu block interrupts within the device, ` 1 - enables the ds1/e1 framer/liu block interrupts at the block-level. bit 2 - ds3 framer block interrupt enable this read/write bit is used to either enable or disable the ds3 framer block for interrupt generation. if the user writes a 0 to this register bit and disables the ds3 framer block (for inte rrupt generation), then all ds3 framer block interrupts will be disabled for interrupt generation. if the user writes a 1 to this register bit, the user will still need to enable the individual ds3 framer block interrupt(s ) at the source level in order to enable that particular interrupt. ` 0 - disable all ds3 framer block interrupts within the device. ` 1 - enables the ds3 framer block at the block-level. bit [1:0] - unused
XRT86SH328 preliminary 50 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - unused bit 6 - receive sts-1/sts-3 toh processor block interrupt enable this read/write bit-field is used to either enable or disable the receive sts-1/sts-3 toh processor block for interrupt generation. if the user writes a 0 to this regist er bit and disables the receive sts-1/st s-3 toh processor block (for interrupt generation), then all receive sts-1/sts-3 toh processor bl ock interrupts will be disabled for interrupt generation. if the user writes a 1 to this register bit, the user will still need to enabl e the individual receive sts-1/sts-3 toh processor block interrupt(s) at the source level in order to enable that particular interrupt. ` 0 - disables all receive sts-1/sts-3 toh pr ocessor block interrupts within the device. ` 1 - enables the receive sts-1/sts-3 toh processor block at the block level for interrupt generation. bit 5 - receive sts-1/sts-3 poh pr ocessor block interrupt enable this read/write bit-field is used to either enable or disable the receive sts-1/st s-3 poh processor block for interrupt generation. if the user writes a 0 into this register bit and disables the receive sts-1/sts-3 poh pr ocessor block (for interrupt generation), then all receive sts-1/sts-3 processor blo ck interrupts will be disabled for interrupt generation. if the user writes a 1 to this register bit, then the user will still need to en able the individual receive sts-1/sts-3 poh processor block interrupt(s) at the source level in order to enable that particular interrupt. ` 0 - disables all receive sts-1/sts-3 poh pr ocessor block interrupts within the device. ` 1 - enables the receive sts-1/sts-3 poh processor block at the block level for interrupt generation. bit [4:3] - unused bit 2 - external interrupt in put pin # 1 - interrupt enable this read/write bit-field is used to either enable or disable the external interrupt pin # 1 interrupt. if this interrupt is enabled, then the XRT86SH328 will generat e an interrupt anytime that the ext_int_1 input pin (ball t5) has been driven to the logic high level. ` 0 - disables the external interrupt input # 1 interrupt ` 1 - enables the external interrupt input # 1 interrupt. bit [1:0] - unused t able 37: o peration b lock i nterrupt e nable r egister - b yte 0 (a ddress = 0 x 0017) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused receive sts-1/sts-3 tohblock interrupt enable receive sts-1 poh block interrupt enable unused external interrupt enable # 1 unused r/o r/w r/w r/o r/o r/w r/w r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 51 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - t1/e1 de-sync disable this read/write bit-field is used to either enable or di sable the t1/e1 de-sync circuitry within the XRT86SH328. ` 0 - enables the t1/e1 de-sync circuitry. ` 1 - disables the t1/e1 de-sync circuitry. bit 6 - sts-1/sts-3 and ds3 share serial interface this read/write bit-field is used to configure the ds3 a nd sts-1/sts-3 circuitry to either share the same serial interface or not. to operate the XRT86SH328 in the tran smux mode, then the user mu st configure the ds3 and sts- 1/sts-3 circuitry to not share the same serial interface. ` 0 - configures the sts-1/sts-3 and ds3 circui try to not share the same serial interface. ` 1 - configures the sts-1/sts-3 and ds3 circ uitry to share the same serial interface. bit 5 - additional t1/e1 framer enabled this read/write bit-field is used to either enable or disable the m13 t1/e1 framers. if the user enables these additional t1/e1 framers, then the XRT86SH328 will be able to perform full-blown performance monitoring in both the ingress and egress directions .if the user disables the m13 t1/e1 framers, then the user will only be able to perform full-block performance monitoring on the ingress direction t1/e1 signals. ` 0 - disables the m13 t1/e1 framer blocks. ` 1 - enables the m13 t1/e1 framer blocks. n ote : this bit-field is only active if the XRT86SH328 has b een configured to operate in the 28-channel clear-channel t1/e1 framer mode. bit [4:1] - unused bit 0 - au-3/tug-3 mode select: this read/write bit-field is used to configure the xrt86s h328 to operate in either the au-3 or the tug-3 mapping mode. ` 0 - configures the XRT86SH328 to operate in the tug-3 mode. ` 1 - configures the XRT86SH328 to operate in the au-3 mode. n ote : this register bit is only active if the xrt86sh3 28 has been configured to operate in the sdh mode. bit [7:4]- unused bit [3:0] - loop-back mode[3:0] t able 38: m ode c ontrol r egister - b yte 0 (a ddress = 0 x 001b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1/e1 de-sync disable sts-1/sts-3 & ds3 share serial interface additional t1/e1 framers enabled unused au-3/tug_3* r/w r/w r/w r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 39: l oop - back c ontrol r egister - b yte 0 (a ddress = 0 x 001f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused loop-back[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 52 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 these four read/write bits-fields are used to configure the XRT86SH328 to operate in a variety of loop-back modes, as is tabulated below. bit [7:0] - transmit sts-1/sts-3 telecom bus - sync delay - upper byte the transmit sts-1/sts-3 telecom bus can be configured to alignment its transmission of sonet/sdh frames with 8khz pulses being applied to the txsbfp_in_out input pin. the user is expected to apply a pulse (wit h the period of either a 6.48mhz or a 19 .44mhz clock signal) at a rate of 8khz to the txsbfp_in_out input (pin number p5). the transmit sts-1/sts-3 telecom bus will align its transmission of the very first byte of a new sts-1/sts-3 frame, with a pulse at this input pin. these read/write bit-fields (along with that within the st s-1/sts-3 telecom bus control register - byte 2) are used to specify the amount of delay (in term s of either 6.48mhz or 19.44mhz clock periods) that will exist between the rising edge of txsbfp_in_out and the transmission of the very firs t byte, within a given sts-1/ sts-3 frame via the transmit sts-1/sts-3 telecom bus. ` 0x0000 - configures each of the transm it sts-1/sts-3 telecom bus interfaces to transmit the very first byte of a new sts-1/sts-3 frame, upon detection of the rising edge of the txsbfp_in_out. ` 0x0001 - configures each of t he transmit sts-1/sts-3 teleco m bus interfaces to delay its transmission of the very first byte of a new sts-1/sts-3 frame, by one 6.48mhz or 19.44mhz clock period, and so on. n ote : this register is only active if the sts-1/sts-3 telecom bus interface is enabled. loop back modes l oop - back [3:0] r esulting l oop - back m ode 0000 normal mode (e.g., no loop-back mode) 0001 remote line loop-back in this mode, all data that is received by the receive sts-1/sts-3 serial interface will be routed to the transmit sts-1/sts-3 serial interface. 0010 local transport loop-back in this mode, all data that is being output via the transmit sts-1/sts-3 toh processor block will also be routed to the rece ive sts-1/sts-3 toh processor block. 0011 local path loop-back in this mode, all data that is output by the transmit sts-1/sts-3 poh processor block (e.g., towards the transmit sts-1/sts-3 to h processor block) will be routed to the receive sts-1/sts-3 poh processor block. 0100 - 1111 reserved - do not use t able 40: sts-1/sts-3 t elecom b us c ontrol r egister - b yte 3 (a ddress = 0 x 0034) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hrsync_delay[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 41: sts-1/sts-3 t elecom b us c ontrol r egister - b yte 2 (a ddress = 0 x 0035) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hrsync_delay[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 53 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - transmit sts-1/sts-3 te lecom bus - sync delay - lower byte the transmit sts-1/sts-3 telecom bus is aligned to the tx sbfp_in_out input pin. the user is expected to apply a pulse (with the period of either a 6.48m hz or a 19.44mhz clock signal) at a rate of 8khz to the txsbfp_in_out input (pin number p5). the transmit sts-1/ sts-3 telecom bus will align its transmission of the very first byte of a new sts- 1/sts-3 frame, with a pulse at this input pin. these read/write bit-fields (along with that within the st s-1/sts-3 telecom bus control register - byte 3) are used to specify the amount of delay (in terms of either a 6.48mhz or a 19.44mhz cl ock periods) that will exist between the rising edge of txsbfp_in_out and the transmission of the ve ry first byte, within a given sts-1/sts-3 frame via the transmit sts-1/st s-3 telecom bus. ` 0x0000 - configures each of the transm it sts-1/sts-3 telecom bus interfaces to transmit the very first byte of a new sts-1/sts-3 frame, upon detection of the rising edge of the txsbfp_in_out. s ` 0x0001 - configures each of t he transmit sts-1/sts-3 teleco m bus interfaces to delay it s transmission of the very first byte of a new sts-1/sts-3 frame, by one 6.48mhz or 19.44mhz clock period, and so on. n ote : this register is only active if the sts-1/sts-3 telecom bus interface is enabled. bit 7 - set telecom bus to sts-1/sts-3 mode: this read/write bit-field is used to configure the sts-1/ sts-3 telecom bus interface to operate at either the sts- 1/sts-3 or sts-3 rates. ` .0 - configures the telecom bus interface to operate at th e sts-3/sts-1/sts-3 rate. in this case, the telecom bus interface will operate at a rate of 19.44mhz. ` 1 - configures the telecom bus interface to operate at the sts-1/sts-3 rate. in this ca se, the telecom bus interface will operate with a clock rate of 6.48mhz. n ote : this bit-field is only active if the XRT86SH328 has been configured to transmit/receive data (on the high-speed side) via the telecom bus interface. bit 6 - fractional bandwidth enable: if the XRT86SH328 is configured to transmit/receive data via the telecom bus interface as sts-3/sts-1/sts-3 rates, then this read/write bit-field can be used to configur e the XRT86SH328 to operate in the fractional bandwidth mode. if the XRT86SH328 is configured to operate in the fracti onal bandwidth mode, then it will only fill in the sts-1/sts-3 time-slot data (within this outbound sts- 3/sts-1 or sts-3 data-stream) that perta ins to this particular XRT86SH328. the XRT86SH328 will tri-state the transmit sts-1/sts-3 telecom bus interface co incident to whenever the other sts- 1/sts-3 time-slot data would ordinarily be output via the sts-3/sts-1/sts- 3 telecom bus interface. if the XRT86SH328 is not configured to operate in the fractional bandwidth mode , then it will fill in the sts-1/sts-3 time-slot data (within this outbound sts-3/sts-1/sts-3 data-str eam) that pertains to this particular XRT86SH328. the XRT86SH328 will automatically set the byte s (within all of the remaining sts-1/st s-3 time-slots) to 0x00 as it outputs this sts-3/sts-1/sts-3 data-stream via the transmit sts-3/sts-1/sts-3 telecom bus interface. ` 0 - configures the XRT86SH328 to not oper ate in the fractional bandwidth mode. ` 1 - configures the XRT86SH328 to operat e in the fractional bandwidth mode. n otes : 1. if the user wishes to design in three (3) XRT86SH328 s (into his/her system) such that they are sharing the same sts-3/sts-1/sts-3 te lecom bus, then the user must set this bit-field to 1. t able 42: sts-3/sts-1/sts-3 t elecom b us c ontrol r egister - b yte 1 (a ddress = 0 x 0036) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 set telecom bus to sts- 1/sts-3 mode fractional bandwidth enable slot_0 master slot[1:0] telecom bus parity include v1 signal framing pulse enable telecom bus - v1 signal support enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 54 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 2. this bit-field is only active if the telecom bus interface has been configured to operate in the sts- 3/sts-1/sts-3 mode. bit 5 - slot master designate this read/write bit-field is used to designate a given xr t86sh328 as being the slot mast er. if the user designates a given XRT86SH328 has being the slot master, then this device will be respon sible for sourcing the b1 byte, the rei- l and rdi-l indicators (within the outbo und sts-3/sts-1/sts-3 data-stream). additionally, if a given XRT86SH328 has been designated as the slot ma ster, then it will be responsible fo r generating an 8khz signal via its txsbfp_in_out input/output pin. if a given XRT86SH328 is not configured to function as th e slot master, then its txsbfp _in_out input/output pin will function as an input pin ` 0 - configures this particular xrt8 6sh328 to not be the slot master. ` 1 - configures this particular xrt86sh 328 to function as the slot master. n otes : 1. this bit-field is only value if (1) the telecom bus interface is configured to operate in the sts-3/sts- 1/sts-3 mode. 2. the XRT86SH328 has been configured to operate in the fractional bandwidth mode. 3. this particular XRT86SH328 has been assig ned the sts-1/sts-3 time slot of [0, 0]. bit [4:3] sts-1/sts-3 time slot assignment: this read/write bit-field is used to specify which sts-1/st s-3 time-slot that the XRT86SH328 will fill-in, if it has been configured to operate in the fractional bandwidth mode. ` valid values to write into these bit-fields are: [0, 0], [0, 1], and [1, 0]. n otes : 1. these bit-fields are only active if (1) the teleco m bus interface has been conf igured to operate in the sts-3/sts-1/sts-3 mode, and (2) if the user has conf igured the XRT86SH328 to operate in the fractional bandwidth mode. 2. if a given XRT86SH328 has been designed into a gi ven sts-3/sts-1/sts-3 application (which involves a total of three XRT86SH328s), for the XRT86SH328 (w hich has been designated as the slot master), the user must set these bi t-fields to [0, 0]. bit2 - telecom bus pari ty include v1 signal bit 1 - telecom bus interface - frame pulse mode: this read/write bit-field is used to configure the sts-1/ sts-3 telecom bus interface to operate in the frame pulse mode. if the sts-1/sts-3 telecom bus interface is configur ed to operate in the frame pulse mode, then all of the following will be true. ? the txa_c1j1v1_fp output pin will only pulse high coincident to whenever t he XRT86SH328 outputs the very first byte of a given sts-1/sts-3 frame via th e transmit sts-1/sts-3 telecom bus interface - output data bus (txa_d[7:0]). ? the rxd_c1j1v1_fp input pin will accept a pulse, coincident to whenever the very first byte of the incoming sts-1/sts-3 frame is being placed on the receive st s-1/sts-3 telecom bus inte rface - input data bus (rxd_d[7:0]). if the sts-1/sts-3 telecom bus interf ace is not configured to operate in the frame pulse mode, then the telecom bus interface will perform as configured in bits 0 (telecom bus - v1 signal support enable) within this register, and bit 3 (telecom bus j1 only) within the sts- 3/sts-1/sts-3 telecom bus control register - byte 0.0 - configures the sts- 1/sts-3 telecom bus interface to not operate in the fram e pulse mode.1 - configures the sts-1/sts-3 telecom bus interface to operate in the frame pulse mode. bit - 0 - transmit sts-1/sts-3 telecom bus - v1 pulse enable: this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 telecom bus interface to pulse the txa_c1j1v1_fp output pin high coincident to whenever the XRT86SH328 outputs a v1 byte via the transmit sts- 1/sts-3 telecom bus interface - output data bus (txa_d[7:0]). ` 0 - configures the transmit sts-1/sts-3 telecom bus inte rface to not denote the v1 byte via the txa_c1j1v1_fp output pin. ` 1 - configures the transmit sts-1/sts-3 telecom bus in terface to denote the v1 byte via the txa_c1j1v1_fp output pin.
preliminary XRT86SH328 55 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : this register bit is only active if the xrt86sh 328 has been configured to vt/tu map t1/e1 data into sonet/sdh. bit 7 - set telecom bus to sts-1/sts-3 mode this read/write bit-field is used to configure the sts-1/ sts-3 telecom bus interface to operate at either the sts- 1/sts-3 or sts-3 rates. ` 0 - configures the telecom bus interfac e to operate at the sts-3/sts-3 rate. in this case, the teleco m bus interface will operate at a rate of 19.44mhz. ` 1 - configures the telecom bus interface to operate at the sts-1/sts-3 rate. in this ca se, the telecom bus interface will operate with a clock rate of 6.48mhz. n ote : this bit-field is only active if the XRT86SH328 has been configured to transmit/receive data (on the high-speed side) via the telecom bus interface. bit 6 - fractional bandwidth enable if the XRT86SH328 is configured to transmit/receive data via the telecom bus interface as sts-3/sts-1/sts-3 rates, then this read/write bit-field is used to configure the XRT86SH328 to operate in the fractional bandwidth mode. if the user configures the XRT86SH328 to operate in the fr actional bandwidth mode, then it will only fill in the sts- 1/sts-3 time-slot data (within this outbound sts-3/sts- 1/sts-3 data-stream) that pertains to this particular XRT86SH328. the XRT86SH328 will tri-state the transm it sts-1/sts-3 telecom bus interface coincident to whenever the other sts-1/sts-3 time-s lot data would ordinarily be output vi a the sts-3/sts-1/sts-3 telecom bus interface. if the user configures the XRT86SH328 to not operate in the fractional bandwidth mode, then it will fill in the sts- 1/sts-3 time-slot data (within this outbound sts-3/sts- 1/sts-3 data-stream) that pertains to this particular XRT86SH328. the XRT86SH328 will automatically set the by tes (within all of the remain ing sts-1/sts-3 time-slots) to 0x00 as it outputs this sts-3/sts- 1/sts-3 data-stream via the transmit st s-3/sts-1/sts-3 telecom bus interface. ` 0 - configures the XRT86SH328 to not oper ate in the fractional bandwidth mode. ` 1 - configures the XRT86SH328 to operat e in the fractional bandwidth mode. n otes : 1. to design in three (3) XRT86SH328s (into the users system) such that they are sharing the same sts- 3/sts-1/sts-3 telecom bus, then the user must set this bit-field to 1. 2. this bit-field is only active if the telecom bus interface has been configured to operate in the sts- 3/sts-1/sts-3 mode. bit 5 - slot 0 master designate this read/write bit-field is used to designate a given xr t86sh328 as being the slot mast er. if the user designates a given XRT86SH328 has being the slot master, then this device will be responsi ble for sourcing the b1 byte, the rei- l and rdi-l indicators (within the outbo und sts-3/sts-1/sts-3 data-stream). additionally, if a given XRT86SH328 has been designated as the slot ma ster, then it will be responsible fo r generating an 8khz signal via its txsbfp_in_out input/output pin. if a given XRT86SH328 is not configured to function as the slot master, then its tx sbfp_in_out input/output pin will function as an input pin. ` 0 - configures this particular xrt8 6sh328 to not be the slot master. t able 43: sts-3/sts-1/sts-3 t elecom b us c ontrol r egister - b yte 1 (a ddress = 0 x 0036) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set telecom bus to sts-1/sts- 3 mode fractional bandwidth enable slot_0 master slot[1:0] telecom bus parity include v1 signal framing pulse enable telecom bus - v1 signa support enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 56 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 1 - configures this particular xrt86sh 328 to function as the slot master. n otes : 1. this bit-field is only value if (1) the telecom bus interface is configured to operate in the sts-3/sts- 1/sts-3 mode. 2. the XRT86SH328 has been configured to operate in the fractional bandwidth mode. 3. this particular XRT86SH328 has been assig ned the sts-1/sts-3 time slot of [0, 0]. bit [4:3] - sts-1/sts-3 time slot assignmen this read/write bit-field is used to specify which sts-1/st s-3 time-slot that the XRT86SH328 will fill-in, if it has been configured to operate in the fractional bandwidth mode. valid values to write into these bit-fields are: [0, 0], [0, 1], and [1, 0]. n otes : 1. these bit-fields are only active if (1) the teleco m bus interface has been conf igured to operate in the sts-3/sts-1/sts-3 mode, and (2) if the user has conf igured the XRT86SH328 to operate in the fractional bandwidth mode.2. 2. if a given XRT86SH328 has been designed into a gi ven sts-3/sts-1/sts-3 application (which involves a total of three XRT86SH328s), for the XRT86SH328 (w hich has been designated as the slot master), the user must set these bi t-fields to [0, 0]. bit 2 - telecom bus parity include v1 signal bit 1 - .telecom bus interface - frame pulse mode this read/write bit-field is used to configure the sts-1/ sts-3 telecom bus interface to operate in the frame pulse mode. if the user configures the sts- 1/sts-3 telecom bus interface to operate in the frame pulse mode, then all of the following will be true. ? the txa_c1j1v1_fp output pin will only pulse high coincident to whenever t he XRT86SH328 outputs the very first byte of a given sts-1/sts-3 frame via th e transmit sts-1/sts-3 telecom bus interface - output data bus (txa_d[7:0]) ? the rxd_c1j1v1_fp input pin will accept a pulse, coincident to whenever the very first byte of the incoming sts-1/sts-3 frame is being placed on the receive st s-1/sts-3 telecom bus inte rface - input data bus (rxd_d[7:0]). if the user does not configure the st s-1/sts-3 telecom bus interface to oper ate in the frame pulse mode, then the telecom bus interface will perform as config ured in bits 0 (telecom bus - v1 signal support enable) within this register, and bit 3 (telecom bus j1 only) within the sts-3/st s-1/sts-3 telecom bus cont rol register - byte 0. ` 0 - configures the sts-1/sts-3 telecom bus inte rface to not operate in the frame pulse mode ` 1 - configures the sts-1/sts-3 telecom bus in terface to operate in the frame pulse mode bit 0 - transmit sts-1/sts-3 telecom bus - v1 pulse enable this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 telecom bus interface to pulse the txa_c1j1v1_fp output pin high coincident to whenever the XRT86SH328 outputs a v1 byte via the transmit sts- 1/sts-3 telecom bus interface - output data bus (txa_d[7:0]) ` .0 - configures the transmit sts-1/sts-3 telecom bus interface to not denote the v1 byte via the txa_c1j1v1_fp output pin. ` 1 - configures the transmit sts-1/sts-3 telecom bus in terface to denote the v1 byte via the txa_c1j1v1_fp output pin. n ote : this register bit is only active if the xrt86sh 328 has been configured to vt/tu map t1/e1 data into sonet/sdh.
preliminary XRT86SH328 57 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - telecom bus enable this read/write is used to either enable or di sable the 51.84/155.52mbps telecom bus interface. ` 0 - telecom bus interface is disabl ed:sts-1/sts-3 data will output via the sts-1/sts-3 serial interface. ` 1 - telecom bus interface is enabled:in this selection, both the transmit and receive sts-1/sts-3 telecom bus interfaces will be enabled. bit 6 - telecom bus tri-state this read/write bit-field is used to tri-state the telecom bus interface. ` 0 - telecom bus interfac e is not tri-stated. ` 1 - telecom bus interf ace is tri-stated. n ote : this read/write bit-field is ignor ed if the sts-1/sts- 3 transmit and receive sts-1/ sts-3 telecom bus interfaces are disabled. bit 5 - unused bit 4- telecom bus parity type this read/write bit-field is used to define the parame ters, over which telecom bus parity will be computed. ` 0 - parity is computed/verified over the transmit sts-1/ sts-3 and receive telecom bus - data bus pins (e.g., txa_d[7:0] and rxd_d[7:0]).if the user implements this selection, then the following will happen. a. the transmit sts-1/sts-3 telecom bu s interface will compute and output pa rity (via the txa_dp output pin) based upon and coincident with the data being output via the txa_d[7:0] output pins. b. the sts-1/sts-3 receive telecom bus interface will com pute and verify the parity data (which is input via the rxd_dp input pin) based upon the data which is bei ng input (and latched) via the rxd_d[7:0] input pins. ` 1 - parity is computed/verified over the transmit sts-1/ sts-3 and receive telecom bus - data bus pins (e.g., txa_d[7:0] and rxd_d[7:0]), the c1j1 and pl input/output pins. ` if the user implements this select ion, then the following will happen. a. the transmit sts-1/sts-3 telecom bus interface will compute and output parity (via the txa_dp output) based upon and coincident with (1) the data being output vi a the txa_d[7:0] output pins, (2) the state of the txa_pl output pin, and (3) the st ate of the txa_c1j1 output pin. b. the receive sts-1/sts-3 telecom bus interface will compute and verify t he parity data (which is input via the rxd_dp input pin) based upon (1) the data which is being input (and latched) via the rxd_d[7:0] input pins, (2) the state of the rxd_pl input pin, and (3) the state of the rxd_c1j1 input pin. n otes : 1. this bit-field is disabled if th e sts-1/sts-3 telecom bus is disabled. 2. the user can configure the sts-1/sts-3 telecom bu s to compute with either even or odd parity, by writing the appropriate data into bit 2 (telec om bus parity - odd), within this register. bit 3 - telecom bus - j1 indicator only: this read/write bit-field is used to configure how the transmit sts-1/sts-3 and receive telecom bus interface handles the txa_c1j1 and rxd_c1j1 signals, as described below. ` 0 - c1 and j1 bytes this selection configures the following. a. the transmit sts-1/sts-3 telecom bus to pulse th e txa_c1j1v1_fp output coincident to whenever the c1 and j1 bytes are being output via the txa_d[7:0] output pins. t able 44: sts-3/sts-1/sts-3 t elecom b us c ontrol r egister - b yte 0 (a ddress = 0 x 0037) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 te l e c o m b u s on telecom bus disable unused telecom bus parity type telecom bus j1 only telecom bus parity odd telecom bus parity enable rephase sts-1 r/w r/w r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 1
XRT86SH328 preliminary 58 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 b. the sts-1/sts-3 receive telecom bu s will expect the rxd_c1j1v1_fp input to pulse high coincident to whenever the c1 and j1 bytes are being sampled via the rxd_d[7:0] input pins. ` 1 - j1 bytes only this selection configures the following. a. the transmit sts-1/sts-3 telecom bus interface to only pulse the txa_c1j1v1 _fp output pin coincident to whenever the j1 byte is being out put via the txa_d[7:0] output pins. n ote : the txa_c1j1v1_fp output pin will not be pulsed high whenever the c1 byte is being output via the txa_d[7:0] output pins. b. the sts-1/sts-3 receive telecom bus interface will expect the rxd_c1j1v1_fp input to only pulse high coincident to whenever the j1 byte is bei ng sampled via the rxd_d[7:0] input pins. n ote : the rxd_c1j1v1_fp input pin will not be pulsed high whenever the c1 byte is being input via the rxd_d[7:0] input pins bit 2 - telecom bus parity - odd parity select: this read/write bit-field is used to configure the st s-1/sts-3 telecom bus interface to do the following. a. in the transmit (drop) directionthe sts-1/sts-3 te lecom bus to compute either the even or odd parity over the contents of the (1) txd_d[7: 0] output pins, or (2) txd_d[7:0] ou tput pins, the states of the txd_pl and txd_c1j1 output pins (depend ing upon user setting for bit 3). b. in the receive (add) directionreceive sts-1/sts-3 telecom bus to compute and verify the even or odd parity over the contents of the (1) rxa_d[7:0] input pi ns, or (2) rxa_d[7:0] inpu t pins, the states of the rxa_pl and rxa_c1j1 input pins (depending upon user setting for bit 3). ` 0 - configures transmit (drop) telecom bus to compute e ven parity and configures the receive (add) telecom bus to verify even parity. ` 1 - configures transmit (drop) telecom bus to compute o dd parity and configures the receive (add) telecom bus to verify odd parity. bit 1 - telecom bus parity enable this read/write bit-field is used to either enable or disable parity calculation and placement via the txa_dp output pin. this bit field also is used to enable or di sable parity verification by the receive telecom bus. ` 0 - disables parity calculation (on the transmit telecom bus) and disables parity verification (on the receive telecom bus. ` 1 - enables parity calculation and verification bit 0 - telecom bus - rephase enable this read/write bit-field is used to configure the re ceive sts-1/sts-3 telecom bus to operate in either the rephase on or rephase off modes. if the user configures the receive sts-1/sts-3 teleco m bus interface to operate on th e rephase on mode, then the receive sts-1/sts-3/sts-1/st s-3 toh/poh processor blocks will interna lly compute the pointer bytes, based upon the data that it receives via the rxd_d[7:0] input pins. if the user configures the receive sts-1/sts-3 telecom bus interface to operate in the repha se off mode, then the receive sts-1/sts-3/sts-1/st s-3 toh/poh processor blocks will not internally compute the pointer bytes, based upon the data that it receives via the rx d_d[7:0] input pins. in this case, th e voyager device will rely upon the signaling via the telecom bus interface pins (e.g., via the rxd_pl and rxd_c1j1v1_fp pins) in order to compute these pointer bytes. n ote : if the receive sts-1/sts-3 telecom bu s is being provided with pulses denot ing the c1 and j1 bytes (via the rxd_c1j1v1_fp input pin), then this feature is unnecessary. ` 0 - configures the telecom bus interfac e to operate in the rephase off mode. ` 1 - configures the telecom bus interface to operate in the rephase on mode.
preliminary XRT86SH328 59 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:5] - unused bit 4- telecom bus interface - detect ion of parity error interrupt status this reset-upon-read bit-field indicates whether or not the receive sts-1/sts-3 telecom bus interface has detected a parity error within the incoming sts-1/sts-3 data-str eam since the last read of this register, as described below. ` 0 - indicates that the receive sts-1/st s-3 telecom bus interface has not detect ed a parity error since the last read of this register. ` 1 - indicates that the receive sts-1/sts-3 telecom bus in terface has detected a parity error (and has generated the detection of parity error interrupt) since the last read of this register. n ote : this register bit-field is only active if the XRT86SH328 has been configured to exchange sts-1/sts-3 data via the telecom bus interface. bit [3:1] - unused bit 0 - telecom bus interface - detection of parity error interrupt enable this read/write bit-field is used to either enable or disable the receive sts-1/sts-3 telecom bus interface - detection of parity error inte rrupt. if this interrupt is enabled, then t he receive sts-1/sts-3 telecom bus interface will generate this interrupt anytime it detects a parity error within t he incoming sts-1/sts-3 data-stream. ` 0 - disables the receive sts-1/sts-3 telecom bus interface - detection of parity error interrupt. ` 1 - enables the receive sts-1/sts- 3 telecom bus interface - detect ion of parity error interrupt. bits [7:0] - general purpose input/output pin # 7 thru 0 the function of this read/write bit-field depends upon w hether the gpio_[7:0] pins are configured to be an input or an output pin. if gpio_[7:0] is configured to be an input pin: these register bits operates as a read-only bit-fields that reflects the state of the gpio_[7:0] input pins. if the gpio_[7:0] input pins ar e pulled to a logic high, then this register bit will be set to 1. conversely, if the gpio_7 input pin is pulled to a logic low, then this register bit will be set to 0. if gpio_[7:0] is configured to be an output pin tthe user can control the logic leve l of gpio_[7:0] by writ ing the appropriate value into these bit-fields. ` 0 - causes the gpio_[7:0] output pins to be driven low. ` 1 - causes the gpio_[7:0] output pins to be driven high. t able 45: o peration b lock - i nterface c ontrol r egister (a ddress = 0 x 003c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused telecom bus parity error interrupt status unused telecom bus parity error interrupt enable r/o r/o r/o rur r/o r/o r/o r/w 0 0 0 0 0 0 0 0 t able 46: o peration g eneral p urpose i nput /o utput r egister - b yte 0 (a ddress = 0 x 0047) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpio_7 gpio_6 gpio_5 gpio_4 gpio_3 gpio_2 gpio_1 gpio_0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 60 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - gpio_[7:0] direction select these read/write bit-fields are used to configure the gpio _[7:0] pins to function as either input or output pins. ` 0 - configures gpio_[7:0] to function as input pins. ` 1 - configures gpio_[7:0] to function as output pins. bit [7:5] - unused bit [4:0] - recovered t1 /e1 clock select[4:0] th ese read/write bit-fields are used to select any one of 28 t1 or 21 e1 recovered clock signals, and do either of the following. output a replica of this selected clock si gnal via the rclkout output pins . synthesize a 19.44mhz clock signal (from this selected recovered t1/e1 clo ck) and output this signal via the rclkout output pin. the relationship between the conten ts within these bit-fields and the selected channel is tabulated below. t able 47: o peration g eneral p urpose i nput /o utput d irection r egister 0 (a ddress = 0 x 004b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpio_dir[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 48: o peration i/o c ontrol r egister (a ddress = 0 x 004f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused rxclk_select[4:0] r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit field contents r x clk_s elect [4:0] s elected c hannel c omment 00000 none rclkout pin is tri-stated 00001 channel 0 00010 channel 1 00011 channel 2 00100 channel 3 00101 channel 4 00110 channel 5 00111 channel 6 01000 channel 7 01001 channel 8 01010 channel 9 01011 channel 10
preliminary XRT86SH328 61 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:4]- unused bit [3:0] - ds1/e1 framer block (vt side) channels 27, 26, 25 & 24 these read-only bit-fields indicate whether or not th e ds1/e1 framer block (on the vt side) associated with channel [27:24] have a pending interrupt request. ` 0 - indicates that the ds1/e1 framer block sassociated with channel [27:24] (on the vt side) does not have a 01100 channel 11 01101 channel 12 01110 channel 13 01111 channel 14 10000 channel 15 10001 channel 16 10010 channel 17 10011 channel 18 10100 channel 19 10101 channel 20 10110 channel 21 10111 channel 22 11000 channel 23 11001 channel 24 11010 channel 25 11011 channel 26 11100 channel 27 11101 none rclkout is an input pin 11110 none rclkout is an input pin 11111 none rclkout is an input pin t able 49: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0050) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused ds1/e1 framer vt-side channel 27 ds1/e1 framer vt-side channel 26 ds1/e1 framer vt-side channel 25 ds1/e1 framer vt-side channel 24 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 bit field contents r x clk_s elect [4:0] s elected c hannel c omment
XRT86SH328 preliminary 62 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 pending interrupt request. ` 1 - indicates that the ds1/e1 framer blocks associated with channel [27:24] (on the vt side) does have a pending interrupt request. bit [7:0] - ds1/e1 framer block (vt side) channels [23:16] these read-only bit-field indicates whether or not the ds1/e1 framer block (on the vt side) associated with channel [23:16] have a pending interrupt request. ` 0 - indicates that the ds1/e1 framer blocks associated with channel [23:16] (on the vt side) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer blocks associated with channel [23:16] (on the vt side) does have a pending interrupt request. bit [7:0] - ds1/e1 framer block (vt side) channels [15:8] these read-only bit-field indicates whether or not the ds1/e1 framer block (on the vt side) associated with channel [15:8] have a pending interrupt request. ` 0 - indicates that the ds1/e1 framer blocks associated with channel [15:8] (on the vt side) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer blocks associated with channel [15:8] (on the vt side) does have a pending interrupt request. t able 50: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0051) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 framer vt-side channel 23 ds1/e1 framer vt-side channel 22 ds1/e1 framer vt-side channel 21 ds1/e1 framer vt- side chan - nel 20 ds1/e1 framer vt-side channel 19 ds1/e1 framer vt-side channel 18 ds1/e1 framer vt-side channel 17 ds1/e1 framer vt-side channel 16 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 51: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0052) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 framer vt-side channel 15 ds1/e1 framer vt-side channel 14 ds1/e1 framer vt-side channel 13 ds1/e1 framer vt-side channel 12 ds1/e1 framer vt-side channel 11 ds1/e1 framer vt-side channel 10 ds1/e1 framer vt-side channel 9 ds1/e1 framer vt-side channel 8 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 63 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - ds1/e1 framer bl ock (vt side) channels [7:0] these read-only bit-field indicates whether or not the ds1/e1 framer block (on the vt side) associated with channel [7:0] has a pending interrupt request. ` 0 - indicates that the ds1/e1 framer blocks associated with cha nnel [7:0] (on the vt side ) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer blocks associat ed with channel [7:0] (on the vt side) does have a pending interrupt request. bit 7 - bit 4 - unused bit [3:0] - ds1/e1 framer blo ck (m13 side) channels [27:24] these read-only bit-field indicate whether or not the ds1/e1 framer block (on t he m13 side) associated with channel [27:24] have a pending interrupt request. ` 0 - indicates that the ds1/e1 framer block associated with channel [27:24] (on th e m13 side) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer block associated with channel [27:24] ( on the m13 side) does have a pending interrupt request. t able 52: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (vt s ide ) b lock - b yte 3 (a ddress = 0 x 0053) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 framer vt-side channel 7 ds1/e1 framer vt-side channel 6 ds1/e1 framer vt-side channel 5 ds1/e1 framer vt-side channel 4 ds1/e1 framer vt-side channel 3 ds1/e1 framer vt-side channel 2 ds1/e1 framer vt-side channel 1 ds1/e1 framer vt-side channel 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 53: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0054) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused ds1/e1 framer m13-side channel 27 ds1/e1 framer m13-side channel 26 ds1/e1 framer m13-side channel 25 ds1/e1 framer m13-side channel 24 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 54: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0055) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 framer m13-side channel 23 ds1/e1 framer m13-side channel 22 ds1/e1 framer m13-side channel 21 ds1/e1 framer m13-side channel 20 ds1/e1 framer m13-side channel 19 ds1/e1 framer m13-side channel 18 ds1/e1 framer m13-side channel 17 ds1/e1 framer m13-side channel 16 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 64 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - ds1/e1 framer block (m13 side) channel [23:16] these read-only bit-fields indicates whether or not the ds1/e1 framer block (on the m13 side) associated with channel [23:16] has a pending interrupt request. ` 0 - indicates that the ds1/e1 framer block associated with channel [23:16] (on the m13 side) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer block associated with channel [23:16] (on the m13 side) does have a pending interrupt request. bit [7:0] - ds1/e1 framer block (m13 side) channels [15:8] these read-only bit-fields indicate whether or not th e ds1/e1 framer block (on the m13 side) associated with channels [15:8] have a pending interrupt request. ` 0 - indicates that the ds1/e1 framer block associated with channel [15:8] (on the m13 side) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer block associated with channel [15:8] (on the m13 side) does have a pending interrupt request. bit [7:0] - ds1/e1 framer block (m13 side) channels [7:0] these read-only bit-fields indicate whether or not th e ds1/e1 framer block (on the m13 side) associated with channels [7:0] have a pending interrupt request. ` 0 - indicates that the ds1/e1 framer block associated with channel [7:0] (on the m13 side) does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 framer block associat ed with channel [7:0] (on the m13 side) does have a pending interrupt request. t able 55: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0056) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 framer m13-side channel 15 ds1/e1 framer m13-side channel 14 ds1/e1 framer m13-side channel 13 ds1/e1 framer m13-side channel 12 ds1/e1 framer m13-side channel 11 ds1/e1 framer m13-side channel 10 ds1/e1 framer m13-side channel 9 ds1/e1 framer m13-side channel 8 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 56: c hannel i nterrupt i ndication r egister - ds1/e1 f ramer (m13 s ide ) b lock - b yte 3 (a ddress = 0 x 0057) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 framer m13- side chan - nel 7 ds1/e1 framer m13- side chan - nel 6 ds1/e1 framer m13- side chan - nel 5 ds1/e1 framer m13- side chan - nel 4 ds1/e1 framer m13- side chan - nel 3 ds1/e1 framer m13- side chan - nel 2 ds1/e1 framer m13- side chan - nel 1 ds1/e1 framer m13- side chan - nel 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 65 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:4] - unused bit [3:0] - ds1/e1 liu block channels [27:24] these read-only bit-fields indicate whether or not the ds1/e1 liu block associated with channels [27:24] have a pending interrupt request. ` 0 - indicates that the ds1/e1 liu block associated with channel [27:24] does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 liu block associated wi th channel [27:24] does have a pending interrupt request. bit[ 7:0] - ds1/e1 liu block channels [23:16] these read-only bit-fields indicate whether or not the ds1/e1 liu block associated with channels [23:16] have a pending interrupt request. ` 0 - indicates that the ds1/e1 liu block associated with channel [23:16] does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 liu block associated wi th channel [23:16] does have a pending interrupt request. bit [7:0] - ds1/e1 liu block channel [15:8] these read-only bit-fields indicate whether or not the ds1/e1 liu block associated with channels [15:8] have a pending interrupt request. ` 0 - indicates that the ds1/e1 liu block associated with channel [15:8] does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 liu block associated wi th channel [15:8] does have a pending interrupt request. t able 57: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 0058) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused ds1/e1 liu channel 27 ds1/e1 liu channel 26 ds1/e1 liu channel 25 ds1/e1 liu channel 24 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 58: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 0059) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 liu channel 23 ds1/e1 liu channel 22 ds1/e1 liu channel 21 ds1/e1 liu channel 20 ds1/e1 liu channel 19 ds1/e1 liu channel 18 ds1/e1 liu channel 17 ds1/e1 liu channel 16 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 59: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 005a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 liu channel 15 ds1/e1 liu channel 14 ds1/e1 liu channel 13 ds1/e1 liu channel 12 ds1/e1 liu channel 11 ds1/e1 liu channel 10 ds1/e1 liu channel 9 ds1/e1 liu channel 8 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 66 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - ds1/e1 liu block channels [7:0] these read-only bit-fields indicate whether or not the ds1/e1 liu block associated with channels [7:0] have a pending interrupt request. ` 0 - indicates that the ds1/e1 liu block associated with channel [7:0] does not have a pending interrupt request. ` 1 - indicates that the ds1/e1 liu block associated with channel [7:0] does have a pending interrupt request. bit [7:4] - unused bit [3:0] - vt-mapper block channels [27:24] these read-only bit-fields indicate whether or not the vt-mapper block associated with channels [27:24] have a pending interrupt request. ` 0 - indicates that the vt-mapper block associated with channel [27:24] does not have a pending interrupt request. ` 1 - indicates that the vt-mapper block associated wi th channel [27:24] does have a pending interrupt request. bit [7:0] - vt-mapper bl ock channels [23:16] these read-only bit-fields indicate whether or not the vt-mapper block associated with channels [23:16] have a pending interrupt request. ` 0 - indicates that the vt-mapper block associated with chan nel [23:16] does not have a pending interrupt request. ` 1 - indicates that the vt-mapper block associated with channel [23:16] does have a pending interrupt request. t able 60: c hannel i nterrupt i ndication r egister - ds1/e1 liu b lock - b yte 3 (a ddress = 0 x 005b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1/e1 liu channel 7 ds1/e1 liu channel 6 ds1/e1 liu channel 5 ds1/e1 liu channel 4 ds1/e1 liu channel 3 ds1/e1 liu channel 2 ds1/e1 liu channel 1 ds1/e1 liu channel 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 61: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused vt mapper block channel 27 vt mapper block channel 26 vt mapper block channel 25 vt mapper block channel 24 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 62: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005d) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-mapper channel 23 vt-mapper channel 22 vt-mapper channel 21 vt-mapper channel 20 vt-mapper channel 19 vt-mapper channel 18 vt-mapper channel 17 vt-mapper channel 16 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 67 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - vt-mapper block channels [15:8] these read-only bit-fields indicate whether or not the vt-mapper block associated with channels [15:8] have a pending interrupt request. ` 0 - indicates that the vt-mapper block associated with channel [15:8] does not have a pending interrupt request. ` 1 - indicates that the vt-mapper block associated with channel [15:8] does have a pending interrupt request. bit[ 7:0] - vt-mapper block channels [7:0] these read-only bit-fields indicate whether or not th e vt-mapper block associated with channels [7:0] have a pending interrupt request. ` 0 - indicates that the vt-mapper block associated with channel [7:0] does not have a pending interrupt request. ` 1 - indicates that the vt-mapper block associated wi th channel [7:0] does have a pending interrupt request. 2.2 liu common control registers bit 7 - reserved: bit 6 - ataos: automatic transmit all ones upon rlos condition if ataos is selected, an all ones pattern will be transmitted on any channel that experiences an rlos condition. if an rlos condition does not occur, taos will remain inactive. 0 = disabled 1 = enabled bits [5:2] - reserved: bit 1 - tclkcntl if tclkcntl is selected, and if the transmit clock to the ds-1 framer is missing, low, or high, then the transmitter outputs to the line interface will send an all ones signal. 0 = disabled t able 63: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-mapper channel 15 vt-mapper channel 14 vt-mapper channel 13 vt-mapper channel 12 vt-mapper channel 11 vt-mapper channel 10 vt-mapper channel 9 vt-mapper channel 8 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 64: c hannel i nterrupt i ndication r egister - vt-m apper b lock - b yte 3 (a ddress = 0 x 005f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-mapper channel 7 vt-mapper channel 6 vt-mapper channel 5 vt-mapper channel 4 vt-mapper channel 3 vt-mapper channel 2 vt-mapper channel 1 vt-mapper channel 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 65: liu c ommon c ontrol r egister 0 (a ddress = 0 x 0100) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ataos reserved tclkcntl liu soft - ware reset r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 68 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 1 = enabled bit 0 - liu software reset: writing a 1 to this bit for more than 10s initiates a device re set for all internal circuits except the microprocessor registe r bits. to reset the registers to their default setting, use th e hardware reset pin (see the pin description for more details) 0 = disabled 1 = enabled bit 7 - line code violation / counter overflow monitor select this bit is used to select the monitoring activity between the lcv and the counter overflow status. when the 16-bit lcv counter saturates, the counter overflow condition is activated. by default, the lcv activity is monitored by bit d4 in register 0xn005, where n is equal to the channel number. ` 0 - monitoring lcv ` 1 - monitoring the counter overflow status bit 6 - pll 19.44mhz disable this bit is used in conjunction with the ds-1/e1 recovered cl ock to synchronize to a 19.44mhz clock source. if this bit is set high, one of the 28 channel recovered line clocks, or an external line clock and be used to provide this synchronization. ` 0 - disabled ` 1 - enabled bit 5 - reserved bit [4:3] - slicer level select these bits are to used to select the amplitude level that is used by the receive line inte rface to determine whether the input data is high or low. 00 - 50% 01 - 45% 10 - 55% 11 - 68% bit 2 - rxmute this bit is used to force the receive ds-1/e1 signals low to prevent chattering any time that the ds-1/e1 receiver inputs at rtip/rring experience an rlos condition. ` 0 - disabled ` 1 - enabled bit 1 - exlos the number of zeros required to declare a dig ital loss of signal is extended to 4,096. ` 0 - normal rlos operation ` 1 - exlos enabled bit 0 - in circuit testing for internal use only. this bit should be set to low. t able 66: liu c ommon c ontrol r egister 1 (a ddress = 0 x 0101) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcvb_of pll19_dis reserved slicer level select[1:0] rxmute exlos ict r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 69 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:4] - reserved bit [3:0] - input clock selection these bits are used to select the frequency of the input cl ock source to the pll. any state not listed is reserved. 0000 = 2.048 mhz 0001 = 1.544 mhz 1000 = 4.096 mhz 1001 = 3.088 mhz 1010 = 8.192 mhz 1011 = 6.176 mhz 1100 = 16.384 mhz 1101 = 12.352 mhz 1110 = 2.048 mhz 1111 = 1.544 mhz bit 7 - reserved bit [6:0] - global ch annel interrupt status - channels 0 to 6 these rur bit fields are used to indicate which channel exper ienced a change in status relati ve to alarm indications. if a channel experiences a change in alarm st atus, the associated bit for that channel will be set high. once this register is read back, these bit fields will automatically return low. t able 67: liu c ommon c ontrol r egister 2 (a ddress = 0 x 0102) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved clksel[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 68: liu c ommon c ontrol r egister 3 (a ddress = 0 x 0103) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ds1/e1 liu global interrupt status channel 6 ds1/e1 liu global interrupt status channel 5 ds1/e1 liu global interrupt status channel 4 ds1/e1 liu global interrupt status channel 3 ds1/e1 liu global interrupt status channel 2 ds1/e1 liu global interrupt status channel 1 ds1/e1 liu global interrupt status channel 0 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 70 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - reserved bit [6:0] - global ch annel interrupt status - channels 7 to 13 these rur bit fields are used to indicate which channel exper ienced a change in status relati ve to alarm indications. if a channel experiences a change in alarm st atus, the associated bit for that channel will be set high. once this register is read back, these bit fields will automatically return low. bit 7 - reserved bit [6:0] - global chan nel interrupt status - channels 14 to 20 these rur bit fields are used to indicate which channel exper ienced a change in status relati ve to alarm indications. if a channel experiences a change in alarm st atus, the associated bit for that channel will be set high. once this register is read back, these bit fields will automatically return low. bit 7 - reserved bit [6:0] - global chan nel interrupt status - channels 21 to 27 these rur bit fields are used to indicate which channel exper ienced a change in status relati ve to alarm indications. if a channel experiences a change in alarm st atus, the associated bit for that channel will be set high. once this register t able 69: liu c ommon c ontrol r egister 4 (a ddress = 0 x 0104) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ds1/e1 liu global nterrupt status channel 13 ds1/e1 liu global nterrupt status channel 12 ds1/e1 liu global nterrupt status channel 11 ds1/e1 liu global nterrupt status channel 10 ds1/e1 liu global nterrupt status channel 9 ds1/e1 liu global nterrupt status channel 8 ds1/e1 liu global nterrupt status channel 7 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 70: liu c ommon c ontrol r egister 5 (a ddress = 0 x 0105) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ds1/e1 liu global nterrupt status channel 20 ds1/e1 liu global nterrupt status channel 19 ds1/e1 liu global nterrupt status channel 18 ds1/e1 liu global nterrupt status channel 17 ds1/e1 liu global nterrupt status channel 16 ds1/e1 liu global nterrupt status channel 15 ds1/e1 liu global nterrupt status channel 14 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 71: liu c ommon c ontrol r egister 6 (a ddress = 0 x 0106) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ds1/e1 liu global interrupt status channel 27 ds1/e1 liu global interrupt status channel 26 ds1/e1 liu global interrupt status channel 25 ds1/e1 liu global interrupt status channel 24 ds1/e1 liu global interrupt status channel 23 ds1/e1 liu global interrupt status channel 22 ds1/e1 liu global interrupt status channel 21 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 71 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications is read back, these bit fields will automatically return low. 2.3 receive sts-1/sts-3 toh processor block registers the register map for the receive sts-1/sts-3 toh processor block is presented in the table below. additionally, a detailed description of each of the re ceive sts-1/sts-3 toh proc essor block registers is presented below. in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328, with the receive sts-1/sts-3 toh processor block highlighted is presented below in figure 3 . bit [7:3] - unused bit 2 - sync on b1 f igure 3. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the r eceive sts- 1/sts-3 toh p rocessor b lock highlighted t able 72: r eceive sts-1/sts-3 t ransport c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0202) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused sync on b1 unused no oh extract r/o r/o r/o r/o r/o r/w r/o r/w 0 0 0 0 0 0 0 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
XRT86SH328 preliminary 72 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 1 - unused bit 0 - no overhead data extract bit 7 - unused bit 6 - signal failure (sf) defect condition detect enable this read/write bit-field is used to enable or disable sf defect detection and declaration by the receive sts- 1/sts-3 toh processor block. ` 0 - configures the receive sts-1/sts-3 toh processor block to not declare nor clear the sf defect condition per the user-specified sf defect decl aration and clearance criteria. ` 1 - configures the receive sts-1/sts- 3 toh processor block to declare and clear the sf defect condition per the user-specified sf defect declara tion and clearance criteria. bit 5 - signal degrade (sd) defect condition detect enable this read/write bit-field is used to enable or disable sd detection and declaration by the receive sts-1/sts-3 toh processor block. ` 0 - configures the receive sts-1/sts-3 toh processor blo ck to not declare nor clear the sd defect condition per the user-specified sd defect decl aration and clearance criteria. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to declare and clear the sd defect condition per the user-specified sd defect declar ation and clearance criteria. bit 4 - de-scramble disable this read/write bit-field is used to either enable or disable de-scrambling by the receive sts-1/sts-3 toh processor block, associated with channel n. ` 0 - de-scrambling is enabled. ` 1 - de-scrambling is disabled. bit 3 - unused bit 2 - rei-l error type this read/write bit-field is used to specify how the re ceive sts-1/sts-3 toh processo r block will count (or tally) rei-l events, for performance monitoring purposes. the user can configure the receiv e sts-1/sts-3 toh processor block to increment rei-l events on either a per-bit or per-frame basis. if the user configures the receive sts-1/sts-3 toh processor block to increment rei-l events on a per-bit basis, then it will incrememt the receive sts-1/ sts-3 transport rei-l error count regist er by the value of the lower nibble within the m0/m1 byte of the in coming sts-1/sts-3 data-stream. if the user configures the receive sts-1/sts-3 toh processor block to increment rei-l events on a per-frame basis, then it will increment the receive sts-1/sts-3 transport rei- l error count register each time it receives an sts- 1/sts-3 or sts-3 frame, in which the lower nibbl e of the m0/m1 byte is set to a non-zero value. ` 0 - configures the receive sts-1/sts- 3 toh processor block to count or tally rei-l events on a per-bit basis. ` 1 - configures the receive sts-1/sts-3 toh processor block to count or tall y rei-l events on a per-frame basis. bit 1 - b2 error type this read/write bit-field is used to specify how the re ceive sts-1/sts-3 toh processo r block will count (or tally) b2 byte errors, for performance moni toring purposes. the user can co nfigure the receive sts-1/sts-3 toh processor block to increment b2 byte errors on either a per-bit or a per-frame basis. t able 73: r eceive sts-1/sts-3 t ransport c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0203) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused sf defect condition detect enable sd defect condition detect enable descramble - disable unused rei-lerror type b2 errortype b1 error type r/o r/w r/w r/w r/o r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 73 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications if the user configures the re ceive sts-1/sts-3 toh processo r block to increment b2 byte errors on a per-bit basis, then it will increment the receive transport b2 byte error count register by the numbe r of bits (within the b2 byte value) that is in error. if the user configures the receive sts- 1/sts-3 toh processor block to increment b2 byte errors on a per-frame basis, then it will increment the receive transport b2 byte error co unt register each time it re ceives an sts-1/sts-3 frame that contains an erred b2 byte. ` 0 - configures the receive sts-1/sts- 3 toh processor block to count b2 byte errors on a per-bit basis. ` 1 - configures the receive sts-1/sts- 3 toh processor block to count b2 byte errors on a per-frame basis. bit 0 - b1 error type this read/write bit-field is used to specify how the re ceive sts-1/sts-3 toh processor block will count (or tally) b1 byte errors, for performance moni toring purposes. the user can co nfigure the receive sts-1/sts-3 toh processor block to increment b1 byte errors on either a per-bit or per-frame basis. if the user configures the re ceive sts-1/sts-3 toh processo r block to increment b1 byte errors on a per-bit basis, then it will increment the receive transport b1 byte error count register by the numbe r of bits (within the b1 byte value) that is in error. if the user configures the receive sts- 1/sts-3 toh processor block to increment b1 byte errors on a per-frame basis, then it will increment the receive transport b1 byte error count register each time it receives an sts-1/sts-3 frame that contains an erred b1 byte. ` 0 - configures the receive sts-1/st s-3 toh processor block to count b1 byte errors on a per-bit basis. ` 1 - configures the receive sts-1/sts- 3 toh processor block to count b1 byte errors on a per-frame basis. bit [7:3] - unused bit 2 - section trace message mismatch defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the section trace mismatch defect condition. the receive sts-1/sts-3 toh processor block will declare the section trace message mismatch defect condition, whenever it accepts a sect ion trace message (via the j0 byte, within the incoming sts-1/sts-3 data-stream) that di ffers from the expected section trace message. ` 0 - indicates that the receive sts-1/sts-3 toh processo r block is not currently declaring the section trace message mismatch defect condition. ` 1 - indicates that the receive sts-1/ sts-3 toh processor block is currently declaring the section trace message mismatch defect condition. bit 1 - section trace message unstable defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the section trace message unstable defect condi tion. the receive sts-1/st s-3 toh processor block will declare the section trace message unstable defect cond ition, whenever the "section trace message unstable" counter reaches the value 8. the receive sts-1/sts- 3 toh processor block will increment the "section trace message unstable" counter for each time that it receives a section trace message that differs from the "expected section trace message". the receive sts-1/sts-3 toh processor block will clear the "section trace message unstable" counter to "0" whenever it has received a given section trace message 3 (or 5) consecutive times n ote : the receive sts-1/sts-3 toh processor block will clear t he "section trace message unstable" defect condition whenever it receives a given section tr ace message 3 (or 5) consecutive times". ` 0 - indicates that the receive sts-1/sts-3 toh processo r block is not currently declaring the section trace t able 74: r eceive sts-1/sts-3 t ransport s tatus r egister - b yte 1 (a ddress l ocation = 0 x 0206) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused section trace message (j0) mismatch defect declared section trace message (j0) unstable defect declared ais-l defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 74 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 message unstable defect condition. ` 1 - indicates that the receive sts-1/ sts-3 toh processor block is currently declaring the section trace message unstable defect condition bit 0 - ais-l defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the ais-l (line ais) defect condition. the re ceive sts-1/sts-3 toh proce ssor block will declare the ais- l defect condition within the inco ming sts-1/sts-3data stream if bits 6, 7 and 8 (e.g., the least significant bits, within the k2 byte) are set to the value [1, 1, 1] for five consecutive sts-1/sts-3frames. ` 0 - indicates that the receive sts-1/sts-3 toh processo r block is not currently declaring the ais-l defect condition. ` 1 - indicates that the receive sts-1/sts-3 toh processor block is currently declaring the ais-l defect condition. bit 7 - rdi-l defect declared indicator this read-only bit-field indicates whether or not the re ceive sts-1/sts-3 toh processor block is detecting the rdi-l (line-remote defect indicator) defect condition, within the incoming sts-1/sts-3 signal. the receive sts- 1/sts-3 toh processor block will declare the rdi-l defect c ondition whenever bits 6, 7 and 8 (e.g., the three least significant bits) of the k2 byte contai ns the 1, 1, 0 pattern in 5 consecutiv e incoming sts-1/sts-3 or sts-3 frames. ` 0 - indicates that the receive sts-1/sts-3 toh processo r block is not currently declaring the ais-l defect condition. ` 1 - indicates that the receive sts-1/sts-3 toh processor block is currently declaring t he ais-l defect condition.. bit 6 - s1 byte unstable defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the s1 byte unstable defect condition. the re ceive sts-1/sts-3 toh processor block will declare the s1 byte unstable defect condition whenever the s1 byte un stable counter reaches the value 32. the receive sts- 1/sts-3 toh processor block will increment the "s1 byte unstable counter" each time that the it receives an sts- 1/sts-3 or sts-3 frame t hat contains an s1 byte that differs from the previously rece ived s1 byte. the receive sts- 1/sts-3 toh processor block will clear the "s1 byte unstable counter" to "0" when the same s1 byte is received for 8 consecutive sts-1/sts-3 frames. n ote : the receive sts-1/sts-3 toh processor block will clear the "s1 byte unstable" defect whenever it receives a given s1 byte, in 8 consecutive sts-1/sts-3 frames. 1. 0 - indicates that the receive sts-1/sts-3 toh processor block is not currently decla ring the s1 byte unstable defect condition. 1. 1 - indicates that the receive sts-1/st s-3 toh processor block is currently de claring the s1 byte unstable defect condition. bit 5 - k1, k2 byte unstable defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the k1, k2 byte unstable defect condition. the receive sts-1/sts-3 toh processor block will declare the k1, k2 byte unstable defect condition whenever it fails to receive the same set of k1, k2 bytes, in 12 consecutive incoming sts-1/sts-3 frames. the receive sts-1/sts-3 to h processor block will clear the "k1, k2 byte unstable" defect whenever it has received a given set of k1, k2 byte values within three consecutive incoming sts-1/sts-3 frames. ` 0 - indicates that the receive sts-1/sts-3 toh processo r block is not currently declaring the "k1, k2 byte t able 75: r eceive sts-1/sts-3 t ransport s tatus r egister - b yte 0 (a ddress l ocation = 0 x 0207) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdi-l defect declared s1 byte unstable defect declared k1, k2 byte unstable defect declared sf defect declared sd defect declared lofdefect detected sefdefect declared losdefect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 75 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications unstable defect" condition. ` 1 - indicates that the receive sts-1/sts-3 toh processor block is currently declaring the "k1, k2 byte unstable defect" condition. bit 4 - sf (signal failure) defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the sf defect condition. the receive sts-1/sts- 3 toh processor block will decl are the sf defect condition anytime it has determined that the number of b2 byte errors (measured over a user-selected period of time) exceeds a certain user-specified b2 byte error threshold. ` 0 - indicates that the receive sts-1/sts-3 toh processor block is not currently declari ng the sf defect condition. this bit is set to "0" when the number of b2 byte errors (accumulated over a given interval of time) does not exceed the "sf defect declaration" threshold. ` 1 - indicates that the receive sts-1/sts-3 toh processo r block is currently declaring the sf defect condition. this bit is set to "1" when the number of b2 errors (accumulated over a given interval of time) does exceed the "sf defect declaration" threshold bit 3 - sd (signal degrade) defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the sd defect condition. the receive sts-1/sts- 3 toh processor block will declare the sd defect condition anytime it has determined that the number of b2 byte errors (measured over a user-selected period of time) exceeds a certain user-specified b2 byte error threshold. ` 0 - indicates that the receive sts-1/sts-3 toh processor bl ock is not currently declarin g the sd defect condition. this bit is set to 0 when the number of b2 errors (accumula ted over a given interval of time) does not exceed the sd declaration threshold. ` 1 - indicates that the receive sts-1/sts-3 toh processo r block is currently declaring the sd defect condition. this bit is set to 1 when the number of b2 errors (accumulated over a given interval of time) does exceed the sd defect declaration threshold. bit 2 - lof (loss of frame) defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the lof defect c ondition. the receive sts-1/ sts-3 toh processor block will declare the lof defect condition if it has been declaring the sef condition for 24 consecutive sts-1/sts-3 frame periods. once the receive sts-1/sts-3 toh processor block has declared the lof defect condition, then th e receive sts-1/sts-3 toh processor block will clear the lof defect if it has not be en declaring the sef condition for 3ms (or 24 consecutive sts- 1/sts-3 frame periods). ` 0 - indicates that the receive sts-1/sts-3 toh processor block is not currently declar ing the lof defect condition. ` 1 - indicates that the receive sts-1/sts-3 toh processo r block is currently declari ng the lof defect condition. bit 1 - sef (severely errored frame) defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the sef defect condition. the receive sts-1/sts-3 toh processor block will declare the sef defect condition if it detects framing alignmen t byte errors in four consecutive sts- 1/sts-3 frames. once the receive toh processor block declares the sef defect condition, the re ceive sts-1/sts-3 toh processor block will then clear the sef defect condition if it detects two c onsecutive sts-1/sts-3 frames with un-e rred framing alignment bytes. if the receive toh processor block declares the sef defect condi tion for 24 consecutive sts-1/sts-3 frame periods, then it will declare the lof defect condition. ` 0 - indicates that the receive sts-1/sts-3 toh processor block is not currently declar ing the sef defect condition. ` 1 - indicates that the receive sts-1/sts-3 toh processo r block is currently declaring the sef defect condition. bit 0 - los (loss of signal) defect declared this read-only bit-field indicates whether or not the receive sts-1/sts-3 toh proc essor block is currently declaring the los (loss of signal) defec t condition. the receive sts-1/sts- 3 toh processor block will declare the los defect condition if it detects los_threshold[15:0] consecutive all zero bytes in the incoming sts-1/sts-3 data stream. n ote : the user can set the los_threshold[15:0] value by writing the appropriate data into the receive sts- 1/sts-3 transport - los threshold value regi ster (address location= 0x022e and 0x022f).
XRT86SH328 preliminary 76 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 0 - indicates that the receive sts-1/sts-3 toh proce ssor block is not currently declaring the los defect condition. ` 1 - indicates that the receive sts-1/sts-3 toh processo r block is currently declari ng the los defect condition. bit [7: 2] - unused bit 1 - change of ais-l (line ais) defect condition interrupt status this reset-upon-read bit-field indicates whether or not th e change of ais-l defect condition interrupt has occurred since the last read of this register. the receive sts-1/ sts-3 toh processor block will generate this interrupt in response to either of the following occurrences. whenever the receive sts-1/sts-3 toh processor block declares the ais-l defect condition. whenever the receive sts-1/sts-3 toh proce ssor block clears the ais-l defect condition. ` 0 - indicates that the change of ais-l de fect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change of ais-l defect condition interrupt has occurred since the last read of this register. n ote : the user can obtain the current state of the ais-l defect condition by reading the contents of bit 0 (ais-l defect declared) within the receive sts-1/sts-3 trans port status register - byte 1 (address location= 0x0206). bit 0 - change of rdi- l (line - remote defect indicator) defect condition interrupt status this reset-upon-read bit-field indicates whether or not th e change of rdi-l defect condition interrupt has occurred since the last read of this register. the receive sts-1/ sts-3 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the receive sts-1/sts-3 toh processo r block declares the rdi-l defect condition. ? whenever the receive sts-1/sts-3 toh processo r block clears the rdi-l defect condition. ` 0 - indicates that the change of rdi-l de fect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change of rdi-l defect condition interr upt has occurred since the last read of this register.note: n ote : the user can obtain the current state of the rdi-l defect condition by reading out the state of bit7 (rdi-l defect declared) within the receive sts-1/sts-3 trans port status register - byte 0 (address location= 0x0207). t able 76: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 2 (a ddress l ocation = 0 x 0209) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused change of ais-ldefect condition interrupt status change of rdi-l defect condition interrupt status r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 77 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - new s1 byte value interrupt status this reset-upon-read bit-field indicates whether or not the new s1 byte value interrupt has occurred since the last read of this register. the receive sts-1/sts-3 toh processor block will gener ate the new s1 byte value interrupt, anytime it has accepted a new s1 byte, fr om the incoming sts-1/sts-3 data-stream. ` 0 - indicates that the new s1 byte value interrupt ha s not occurred since the last read of this register. ` 1 - indicates that the new s1 byte value interrupt has occurred since the last read of this register. n ote : the user can obtain the value for this most recently a ccepted value of the s1 byte by reading the receive sts- 1/sts-3 transport s1 byte value r egister (address location= 0x0227). bit 6 - change in s1 byte unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or not th e change in s1 byte unstable defect condition interrupt has occurred since the last read of this register. the receive sts-1/sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh processor block declares the s1 byte unstable defect condition. ? whenever the receive sts-1/sts-3 toh processor block clears the s1 byte unstable defect condition. ` 0 - indicates that the change in s1 byte unstable defect co ndition interrupt has occurred since the last read of this register. ` 1 - indicates that the change in s1 byte unstable defect co ndition interrupt has not occu rred since the last read of this register. n ote : the user can obtain the current s1 byte unstable defe ct condition by reading the contents of bit6 (s1 byte unstable defect declared) within the receive sts-1/ sts-3 transport status register - byte 0 (address location= 0x0207). bit 5 - change in section trace message unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or no t the change in section trace message unstable defect condition interrupt has occurred since the last read of th is register. the receive sts-1/sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh processor bl ock declares the section trace message unstable defect condition. ? whenever the receive sts-1/sts-3 toh processor bloc k clear the section trace message unstable defect condition. ` indicates that the change in section trace message unst able defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in section trace message un stable defect condition interrupt has occurred since the last read of this register. bit 4 - new section trace message interrupt status this reset-upon-read bit-field indicates whether or not t he new section trace message interrupt has occurred since t able 77: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 1 (a ddress l ocation = 0 x 020a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new s1 byteinter - rupt status change in s1 byte unstablede - fect condi - tioninterrupt status change in section trace mes - sage unsta - ble defect condition interrupt sta - tus new section trace mes - sage inter - rupt status change in section trace mes - sage mis - matchdefect declared interrupt sta - tus unused change in k1, k2 byte unstable defect cond - tion interrupt status new k1k2 byte value interrupt sta - tus rur rur rur rur rur r/o rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 78 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 the last read of this register. the receive sts-1/sts-3 toh proc essor block will generate this interrupt anytime it has accepted a new section trace message withi n the incoming sts-1/sts-3 data-stream. ` 0 - indicates that the new section trace message interrupt has not occurred since the last read of this register. ` 1 - indicates that the new section trace message interrupt has occurred since the last read of this register. n ote : the user can read out the contents of the receive sect ion trace message buffer, which is located at address locations 0x0400 through 0x04ff). bit 3 - change in section trace message mi smatch defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in section trace mismatch defect condition interrupt has occurred since the last read of this register . the receive sts-1/sts-3 toh processor block will generate this interrupt in response to either of the following events. whenever the receive sts-1/sts-3 toh processor block declares the section trace message mismatch defect cond ition whenever the receiv e sts-1/sts-3 toh processor block clears the section trace mismatch defect condition. ` 0 - indicates that the change in section trace message mi smatch defect condition inte rrupt has not occurred since the last read of this register. ` 1 - indicates that the change in section trace message mi smatch defect condition interrupt has occurred since the last read of this register. n ote : the user can determine whether the section trace me ssage mismatch condition is currently cleared or declared by reading the stat e of bit 2 (section trace message mismat ch defect declared) within the receive sts-1/sts-3 transport status register - byte 1 (address location= 0x0206). bit 2 - unused bit 1 - change in k1, k2 byte unstab le defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in k1, k2 byte unstable defect condition interrupt has occurred since the last read of this register . the receive sts-1/sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh processor bl ock declares the k1, k2 byte unstable defect condition. ? whenever the receive sts-1/sts-3 toh processor block clears the k1, k2 byte unstable defect condition. ` 0 - indicates that the change of k1, k2 byte unstable defe ct condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change of k1, k2 byte unstable defect condition interrupt has occurr ed since the last read of this register. n ote : the user can determine whether the k1, k2 byte unstab le defect condition is currently being declared or cleared by reading out the contents of bit 5 (k1, k2 byte unstable defect declared), within the receive sts- 1/sts-3 transport status register - byte 0 (address location= 0x0207). bit 0 - new k1, k2 byte value interrupt status this reset-upon-read bit-fiel d indicates whether or not the new k1, k2 byte value interrupt has occurred since the last read of this register. the rece ive sts-1/sts-3 toh processor block will generate this interrupt whenever its has accepted a new set of k1, k2 byte values from the incoming sts-1/sts-3 data-stream ` 0 - indicates that the new k1, k2 byte value interrupt has not occurred since the last read of this register. ` 1 - indicates that the new k1, k2 by te value interrupt has occurred since the last read of this register. n ote : the user can obtain the contents of the new k1 byte by reading out the contents of the receive sts-1/sts-3 transport k1 byte value register (address location= 0xn1 1f). further, the user ca n also obtain the contents of the new k2 byte by reading out the contents of the receiv e sts-1/sts-3 transport k2 byte value register (address location= 0x0223).
preliminary XRT86SH328 79 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - change of signal failure (sf) defect condition interrupt status this reset-upon-read bit-field indicates whether or not th e change of sf defect condition interrupt has occurred since the last read of this register. the receive sts-1/sts-3 toh proc essor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh proce ssor block declares the sf defect condition. ? whenever the receive sts-1/sts-3 toh processo r block clears the sf defect condition. ` 0 - indicates that the change of sf defect condition interru pt has not occurred since the last read of this register. ` 1 - indicates that the change of sf defect condition inte rrupt has occurred since the last read of this register. n ote : the user can determine whether or not the sf defect co ndition is currently being de clared by reading out the state of bit 4( sf defect declared) within the rece ive sts-1/sts-3 transport st atus register - byte 0 (address location= 0x0207). bit 6 - change of signal degrade (sd) defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change of sd defect cond ition interrupt has occurred since the last read of this register. the receive sts-1/sts-3 toh proc essor block will generate this interrupt in response to either of the following events. ? whenver the receive sts-1/sts-3 toh proce ssor block declares the sd defect condition. ? whenever the receive sts-1/sts-3 toh processo r block clears the sd defect condition. ` 0 - indicates that the change of sd defect condition interr upt has not occurred since the la st read of this register. ` 1 - indicates that the change of sd defect condition inte rrupt has occurred since the last read of this register. n ote : the user can determine whether or not the sd defect condition is current ly being declareds by reading out the state of bit 3 (sd defect declared) within the rece ive sts-1/sts-3 transport status register - byte 0 (address location= 0x0207). bit 5 - detection of rei-l (line - remote error indicator) ev ent interrupt status this reset-upon-read bit-field indicates whether or not the detection of rei-l event inte rrupt has occurred since the last read of this register. the receiv e sts-1/sts-3 toh processor block will gener ate this interrupt anytime it detects an rei-l event within the inco ming sts-1/sts-3 data-stream. ` 0 - indicates that the detection of rei-l event interrupt has not occurred since the la st read of this register. ` 1 - indicates that the detection of rei-l event interr upt has occurred since the la st read of this register. bit 4 - detection of b2 by te error interrupt status this reset-upon-read bit-field indicates whether or not th e detection of b2 byte error interrupt has occurred since the last read of this register. the receive sts-1/sts-3 toh processor block will generate this interrupt anytime it detects a b2 byte error within the incoming sts-1/sts-3 data-stream. ` 0 - indicates that the detection of b2 byte error interrupt has no t occurred since the last read of this register. ` 1 - indicates that the detection of b2 byte error interrupt has occurred since the last read of this register. bit 3 = detection of b1 byte error interrupt status this reset-upon-read bit-field indicates whether or not th e detection of b1 byte error interrupt has occurred since the last read of this register. the receive sts-1/sts-3 toh processor block will generate this interrupt anytime it t able 78: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 0 (a ddress l ocation = 0 x 020b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of sf defect conditionin - terrupt sta - tus change of sd defect condition interrupt sta - tus detection of rei-l event error inter - rupt status detection of b2 byte error inter - rupt status detection of b1 byte error inter - rupt status change of lof defect condition interrupt sta - tus change of sef defect interrupt sta - tus change of los defect condition interrupt sta - tus rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 80 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 detects a b1 byte error within the incoming sts-1/sts-3 data-stream. ` 0 - indicates that the detection of b1 byte error interrupt has no t occurred since the last read of this register. ` 1 - indicates that the detection of b1 byte error interrupt has occurred since the last read of this register bit 2 - change of loss of frame (lof) defect condition interrupt status this reset-upon-read bit-field indicates whether or not t he change of lof defect condition interrupt has occurred since the last read of this register. the receive sts-1/ sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh proce ssor block declares the lof defect condition. ? whenever the receive sts-1/sts-3 toh processo r block clears the lof defect condition. ` 0 - indicates that the change of lof defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change of lof defect condition inte rrupt has occurred since the last read of this register. n ote : the user can determine whether or not the receive st s-1/sts-3 toh processor block is currently declaring the lof defect condition by reading out the state of bit 2 (lof defect declared) within the receive sts- 1/sts-3 transport status register - byte 0 (address location= 0x0207). bit 1 - change of sef defect condition interrupt status this reset-upon-read bit-fiel d indicates whether or not the change of sef defect co ndition interrupt has occurred since the last read of this register. the receive sts-1/ sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh processo r block declares the sef defect condition. ? whenever the receive sts-1/sts-3 toh processo r block clears the sef defect condition. ` 0 - indicates that the change of sef defect condition interru pt has not occurred since the last read of this register. ` 1 - indicates that the change of sef defect condition inte rrupt has occurred since the last read of this register. n ote : the user can determine whether or not the receive st s-1/sts-3 toh processor block is currently declaring the sef defect condition by reading out the state of bit 1 (sef defect declared) within the receive sts- 1/sts-3 transport status register - byte 0 (address location= 0x0207). bit 0 - change of loss of signal (los) defect condition interrupt status this reset-upon-read bit-fiel d indicates whether or not th e change of los defect cond ition interrupt has occurred since the last read of this register. the receive sts-1/ sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh processo r block declares the los defect condition. ? whenever the receive sts-1/sts-3 toh proce ssor block clears the los defect condition. ` 0 - indicates that the change of los defect condition interr upt has not occurred since the last read of this register. ` 1 - indicates that the change of los defect condition inte rrupt has occurred since the la st read of this register. n ote : the user can determine whether or not the receive st s-1/sts-3 toh processor block is currently declaring the los defect condition by reading out the contents of bit 0 (los defect declared) within the receive sts- 1/sts-3 transport status register - byte 0 (address location= 0x0207). bit [7:2] - unused t able 79: r eceive sts-1/sts-3 t ransport i nterrupt e nable r egister - b yte 2 (a ddress l ocation = 0 x 020d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused change of ais-ldefect condition interrupt enable change of rdi-ldefect condition interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 81 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 1- change of ais-l (line ais) defect condition interrupt enable this read/write bit-field is used to either enable or disabl e the change of ais-l defect condition interrupt. if this interrupt is enabled, then the XRT86SH328 will generate an inte rrupt in response to either of the following conditions. ? when the receive sts-1/sts-3 toh processor block declares the ais-l defect condition. ? when the receive sts-1/sts-3 toh processor block clears the ais-l defect condition. ` 0 - disables the change of ais- l defect condition interrupt. ` 1 - enables the change of ais-l defect condition interrupt. bit 0 - change of rdi- l (line remote defect indicator) defect condition interrupt enable this read/write bit-field is used to either enable or disabl e the change of rdi-l defect condition interrupt. if this interrupt is enabled, then the XRT86SH328 will generate an interr upt in response to either of the following conditions. when the receive sts-1/sts-3 toh processor block declare s the rdi-l defect condition. when the receive sts- 1/sts-3 toh processor block clea rs the rdi-l defect condition. ` 0 - disables the change of rdi-l defect condition interrupt. ` 1 - enables the change of rdi-l defect conditi on interrupt. bit 7 - new s1 byte value interrupt enable this read/write bit-field is used to enable or disable the new s1 byte value interrupt. if this interrupt is enabled, then the receive sts-1/sts-3 toh processor block will generate this interrupt anytime it receives and accepts a new s1 byte value. the receive sts-1/sts-3 toh processor block will accept a new s1 byte after it has received it for 8 consecutive sts-1/sts-3 frames. ` 0 - disables the new s1 byte value interrupt. ` 1 - enables the new s1 byte value interrupt. bit 6 - change in s1 byte unstable defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in s1 byte unstable defect condition interrupt.. if the user enables this bit-field, th en the receive sts-1/sts-3 toh processor block will generate an interrupt in response to either of the following conditions ? when the receive sts-1/sts-3 toh processor block declares the s1 byte unstable defect condition ? when the receive sts-1/sts-3 toh processor block clears the s1 byte unstable defect condition. ` 0 - disables the change in s1 byte unstable defect condition interrupt. ` 1 - enables the change in s1 byte unstable defect condition interrupt. bit 5 - change in section trace message unstable defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in section trace message unstable defect condition interrupt. t able 80: r eceive sts-1/sts-3 t ransport i nterrupt e nable r egister - b yte 1 (a ddress l ocation = 0 x 020e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new s1 byte interrupt enable change in s1 byte unstable defect con - ditioninter - rupt enable change in section trace mes - sage unsta - ble defect condition interrupt enable new section trace mes - sage inter - rupt enable change in section trace mes - sage mis - match defect condition interrupt enable unused change in k1, k2 byte unstable defect con - ditioninter - rupt enable new k1k2 byte value interrupt enable r/w r/w r/w r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 82 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 if this interrupt is enabled, then the receive sts-1/sts-3 toh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-1/sts-3 toh processor bl ock declares the section trace message unstable defect condition. ? whenever the receive sts-1/sts-3 toh processor bl ock clears the section trace message unstable defect condition. ` 0 - disable the change of section trace me ssage unstable defect condition interrupt. ` 1 - enables the change of section trace message unstable defect condition interrupt. bit 4 - new section trace message interrupt enable this read/write bit-field is used to enable or disable the new section trace message interrupt. if this interrupt is enabled, then the receive sts-1/sts-3 toh processor block will generate this interrupt anytime it receives and accepts a new section trace message within t he incoming sts-1/sts-3 data-stream. the receive sts- 1/sts-3 toh processor block will accept a new section trace message after it has received it 3 (or 5) consecutive times. ` 0 - disables the new section trace message interrupt. ` 1 - enables the new section trace message interrupt. bit 2 - unused bit 3 - change in section trace mismatch defect condition interrupt enable: this read/write bit-field is used to either enable or di sable the change in section trace mismatch defect condition interrupt. if this interrupt is enabled, then the receive sts-1/sts-3 toh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh processor bl ock declares the section trace message mismatch defect condition. ? whenever the receive sts-1/sts-3 toh processor block clears the section trace message mismatch defect condition. n ote : the user can determine whether or not the receive st s-1/sts-3 toh processor block is currently declaring the section trace message mismatch defect condition by reading the state of bit 2 (section trace message mismatch defect condition declared) within the receiv e sts-1/sts-3 transport status register - byte 1 (address location= 0x0206). bit 1 - change of k1, k2 byte unstable defect condition - interrupt enable this read/write bit-field is used to either enable or di sable the change of k1, k2 byte unstable defect condition interrupt. if this interrupt is enabled, then the receiv e sts-1/sts-3 toh processor bloc k will generate an interrupt in response to either of the following ev ents.a.whenever the receive sts-1/sts-3 toh processor block declares the k1, k2 byte unstable defect condition. b. whenever the receive sts-1/sts-3 toh pr ocessor block clears the k1, k2 byte unstable defect condition. ` 0 - disables the change of k1, k2 byte unstable defect condition interrupt. ` 1 - enables the change of k1, k2 byte unstable defect condition interrupt. bit 0 - new k1, k2 byte value interrupt enable this read/write bit-field is used to either enable or disable the new k1, k2 byte value interrupt. if this interrupt is enabled, then the receive st s-1/sts-3 toh processor block will generate this interrupt anytime it receives and accepts a new k1, k2 byte value. the receive sts-1/sts-3 toh processor block will accept a new k1, k2 byte value, after it has received it within 3 (o r 5) consecutive sts-1/sts-3 frames. ` 0 - disables the new k1, k2 byte value interrupt. ` 1 - enables the new k1, k2 byte value interrupt.
preliminary XRT86SH328 83 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - change of signal failure (sf) defect condition interrupt enable this read/write bit-field is used to either enable or di sable the change of signal failure (sf) defect condition interrupt. if this interrupt is enabled, then the XRT86SH328 will generate an interrupt in response to any of the following events. ? whenever the receive sts-1/sts-3 toh proce ssor block declares the sf defect condition. ? whenever the receive sts-1/sts-3 toh processo r block clears the sf defect condition. ` 0 - disables the change of sf defect condition interrupt. ` 1 - enables the change of sf defect condition interrupt. bit 6 - change of signal degrade (sd) defect condition interrupt enable this read/write bit-field is used to either enable or disable the change of signal degrade (sd) defect condition interrupt. if this interrupt is enabled, then the xrt86sh 328 will generate an interrupt in response to either of the following events. ? whenever the receive sts-1/sts-3 toh proce ssor blolck declares the sd defect condition. ? whenever the receive sts-1/sts-3 toh processor block clears the sd defect condition. ` 0 - disables the change of sd defect condition interrupt. ` 1 - enables the change of sd defect conditi on interrupt. bit 5 - detection of rei-l (line - remote error indicator) ev ent interrupt enable this read/write bit-field is used to either enable or disabl e the detection of rei-l event in terrupt. if this interrupt is enabled, then the XRT86SH328 will generate an interrupt anytime the receive sts-1/sts-3 toh processor block detects an rei-l condition within th e incoming sts-1/sts-3 data-stream. ` 0 - disables the detection of rei-l event interrupt. ` 1 - enables the detection of rei-l event interrupt. bit 4 - detection of b2 by te error interrupt enable this read/write bit-field is used to either enable or disable t he detection of b2 byte error interrupt. if this interrupt is enabled, then the XRT86SH328 will ge nerate an interrupt anytime the rece ive sts-1/sts-3 toh processor block detects a b2 byte error within the incoming sts-1/sts-3 data-stream. ` 0 - disables the detection of b2 byte error interrupt. ` 1 - enables the detection of b2 byte error interrupt. bit 3 - detection of b1 by te error interrupt enable: this read/write bit-field is used to either enable or disable t he detection of b1 byte error interrupt. if this interrupt is enabled, then the XRT86SH328 will ge nerate an interrupt anytime the rece ive sts-1/sts-3 toh processor block detects a b1 byte error within the incoming sts-1/sts-3 data-stream. ` 0 - disables the detection of b1 byte error interrupt. ` 1 - enables the detection of b1 byte error interrupt. bit 2 - change of loss of frame (lof) defect condition interrupt enable this read/write bit-field is used to either enable or dis able the change of lof defect condition interrupt. if this t able 81: r eceive sts-1/sts-3 t ransport i nterrupt s tatus r egister - b yte 0 (a ddress l ocation = 0 x 020f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of sf defect - condition interrupt enable change of sd defect condition interrupt enable detection of rei-l event interrupt enable detection of b2 byte error inter - rupt enable detection of b1 byte error inter - rupt enable change of lof defect condition interrupt enable change of sef defect condition interrupt enable change of los defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 84 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 interrupt is enabled, then the XRT86SH328 will generate an in terrupt in response to either of the following conditions ? when the receive sts-1/sts-3 toh processor block declares the lof defect condition ? when the receive sts-1/sts-3 toh proce ssor block clears the lof defect condition. ` 0 - disables the change of lof defect condition interrupt. ` 1 - enables the change of lo f defect condition interrupt. bit 1 - change of sef defect condition interrupt enable this read/write bit-field is used to either enable or dis able the change of sef defect condition interrupt. if this interrupt is enabled, then the XRT86SH328 will generate an inte rrupt in response to either of the following conditions. ? when the receive sts-1/sts-3 toh processor block declares the sef defect condition. ? when the receive sts-1/sts-3 toh proce ssor block clears the sef defect condition. ` 0 - disables the change of sef defect condition interrupt. ` 1 - enables the change of sef defect condition interrupt. bit 0 - change of loss of signal (los) defect condition interrupt enable this read/write bit-field is used to either enable or dis able the change of lof defect condition interrupt. if this interrupt is enabled, then the XRT86SH328 will generate an inte rrupt in response to either of the following conditions. ? when the receive sts-1/sts-3 toh processor block declares the lof defect condition. ? when the receive sts-1/sts-3 toh processo r block clears the lof defect condition. ` 0 - disables the change of lof defect condition interrupt. ` 1 - enables the change of lo f defect condition interrupt. bit [7:0] - b1 byte error count - msb this reset-upon-read register, along with receive sts-1/ sts-3 transport - b1 byte error count register - bytes 2 through 0, function as a 32 bit counter, which is incr emented anytime the receive sts-1/sts-3 toh processor block detects a b1 byte errorwithin the incoming sts-1/sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is configured to count b1 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b1 byte (of each incoming sts-1/sts-3 frame) that are in error 2. if the receive sts-1/sts-3 toh processor block is configured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b1 byte. t able 82: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 3 (a ddress l ocation = 0 x 0210) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 83: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 2 (a ddress l ocation = 0 x 0211) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 85 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - b1 byte error count (bits 23 through 16) this reset-upon-read register, along with receive sts-1/ sts-3 transport - b1 byte error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incr emented anytime the receive sts-1/sts-3 toh processor block detects a b1 byte error. n otes : 1. if the receive sts-1/sts-3 toh pr ocessor block is configured to count b1 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b1 byte (of each incoming sts-1/sts-3 frame) that are in error. 2. if the receive sts-1/sts-3 toh processor block is configured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b1 byte. bit [7:0] - b1 byte error count - (bits 15 through 8) this reset-upon-read register, along with receive sts-1/ sts-3 transport - b1 byte error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incr emented anytime the receive sts-1/sts-3 toh processor block detects a b1 byte error. n otes : 1. if the receive sts-1/sts-3 toh pr ocessor block is configured to count b1 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b1 byte (of each incoming sts-1/sts-3 frame) that are in error 2. if the receive sts-1/sts-3 toh proc essor block is configured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b1 byte. bit [7:0] - b1 byte error count - lsb this reset-upon-read register, along with receive sts-1/ sts-3 transport - b1 byte error count register - bytes 3 through 1, function as a 32 bit counter, which is incr emented anytime the receive sts-1/sts-3 toh processor block detects a b1 byte error. n otes : 1. if the receive sts-1/sts-3 toh pr ocessor block is configured to count b1 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b1 byte (of each incoming sts-1/sts-3 frame) that are in error. 2. if the receive sts-1/sts-3 toh proc essor block is configured to count b1 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b1 byte. t able 84: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 0212) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 85: r eceive sts-1/sts-3 t ransport - b1 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 0213) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 86 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - b2 byte error count - msb this reset-upon-read register, along with receive sts-1/ sts-3 transport - b2 byte error count register - bytes 2 through 0, function as a 32 bit counter, which is incr emented anytime the receive sts-1/sts-3 toh processor block detects a b2 byte (or bip-24) error withi n the incoming sts-1/sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is configured to count b2 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b2 byte (of each incoming sts-1/sts-3 frame) that are in error. 2. if the receive sts-1/sts-3 toh processor block is configured to count b2 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b2 byte or errered bip-24. bit [7:0] - b2 byte error count (bits 23 through 16) this reset-upon-read register, along with receive transpor t - b2 byte error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremented anytime the receive sts- 1/sts-3 toh processor block detects a b2 byte or bip-24 error within t he incoming sts-1/sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is configured to count b2 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b2 byte (of each incoming sts-1/sts-3 frame) that are in error. 2. if the receive sts-1/sts-3 toh processor block is configured to count b2 byte errors on a per-bit basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b2 byte or erred bip-24. bit [7:0] - b2 byte error count - (bits 15 through 8) t able 86: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 3 (a ddress l ocation = 0 x 0214) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 87: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 2 (a ddress l ocation = 0 x 0215) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 88: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 0216) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 87 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this reset-upon-read register, along with receive transpor t - b2 byte error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremented anytime the receive sts- 1/sts-3 toh processor block detects a b2 byte or bip-24 error within t he incoming sts-1/sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh proc essror block is configured to count b2 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b2 byte (of each incoming sts-1/sts-3 frame) that are in error. 2. if the receive sts-1/sts-3 toh proc essor block is configured to count b2 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b2 byte or erred bip-24. bit [7:0] - b2 byte error count - lsb this reset-upon-read register, along with receive transpor t - b2 byte error count regi ster - bytes 3 through 1, function as a 32 bit counter, which is incremented anytime the receive sts- 1/sts-3 toh processor block detects a b2 byte or bip-24 error within t he incoming sts-1/sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh pr ocessor block is configured to count b2 byte errors on a per-bit basis, then it will increment this 32 bit counter by the nu mber of bits, within the b2 byte (of each incoming sts-1/sts-3 frame) that are in error. 2. if the receive sts-1/sts-3 toh pr ocessor block is configured to count b2 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts- 1/sts-3 frame that contains an erred b2 byte or erred bip-24. bit [7:0] - rei-l event count - msb this reset-upon-read regist er, along with receive sts-1/sts-3 transport - rei-l event count register - bytes 2 through 0, function as a 32 bit counter, which is increm ented anytime the receive sts-1/sts-3 toh processor block detects a line - remote error indicator event wi thin the incoming sts- 1 or sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is co nfigured to count rei-l events on a per-bit basis, then it will increment this 32 bit counter by the nibble-v alue within the rei-l field of the m0 byte within each incoming sts-1/sts-3 frame. 2. if the receive sts-1/sts-3 toh pr ocessor block is configured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each time that it receives an st s-1 or sts-3 frame that contains a non-zero rei-l value. t able 89: r eceive sts-1/sts-3 t ransport - b2 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 0217) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b2_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 90: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 3 (a ddress l ocation = 0 x 0218) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 88 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - rei-l event count (bits 23 through 16) this reset-upon-read register, along with receive sts-1/st s-3 transport - rei-l event count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremen ted anytime the receive sts-1/sts-3 toh processor block detects a line - remote error indicator event wi thin the incoming sts-1 or sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is co nfigured to count rei-l events on a per-bit basis, then it will increment this 32 bit counter by the nibble -value within the rei-l field of the m0 byte (or the contents within the m1 byte) within each incoming sts-1 (or sts-3) frame. 2. if the receive sts-1/sts-3 toh processor block is configured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each time that it receives an st s-1 or sts-3 frame that contains a non-zero rei-l value. bit [7:0] - rei-l event count - (bits 15 through 8) this reset-upon-read register, along with receive sts-1/st s-3 transport - rei-l event count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremen ted anytime the receive sts-1/sts-3 toh processor block detects a line -remote error indicator event wit hin the incoming sts-1 or sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is co nfigured to count rei-l events on a per-bit basis, then it will increment this 32 bit counter by the nibble -value within the rei-l field of the m0 byte (or the contents within the m1 byte) within each incoming sts-1 (or sts-3) frame. 2. if the receive sts-1/sts-3 toh processor block is configured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each time that it receives an st s-1 or sts-3 frame that contains a non-zero rei-l value. bit [7:0] - rei-l event count - lsb this reset-upon-read regist er, along with receive sts-1/sts-3 transport - rei-l event count register - bytes 3 t able 91: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 2 (a ddress l ocation = 0 x 0219) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 92: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 1 (a ddress l ocation = 0 x 021a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 93: r eceive sts-1/sts-3 t ransport - rei-l e vent c ount r egister - b yte 0 (a ddress l ocation = 0 x 021b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-l_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 89 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications through 1, function as a 32 bit counter, which is increm ented anytime the receive sts-1/sts-3 toh processor block detects a line - remote error indicator event wi thin the incoming sts- 1 or sts-3 data-stream. n otes : 1. if the receive sts-1/sts-3 toh processor block is co nfigured to count rei-l events on a per-bit basis, then it will increment this 32 bit counter by the nibble -value within the rei-l field of the m0 byte (or the contents within the m1 byte) within each incoming sts-1 (or sts-3) frame. 2. if the receive sts-1/sts-3 toh pr ocessor block is configured to count rei-l events on a per-frame basis, then it will increment this 32 bit counter each time that it receives an st s-1 or sts-3 frame that contains a non-zero rei-l value. bit [7:0]filtered/acce pted k1 byte value these read-only bit-fields contain the value of the most re cently filtered k1 byte valu e that the receive sts-1/sts- 3 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive sts-1 or sts-3 frames. this register should be polled by software in order to determine various aps codes. bit [7:0]filtered/acce pted k2 byte value these read-only bit-fields contain the value of the most re cently filtered k2 byte valu e that the receive sts-1/sts- 3 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive sts-1 or sts-3 frames. this register should be polled by software in order to determine various aps codes. bit [7:0] - filtered/acc epted s1 byte value these read-only bit-fields contain the value of the most re cently filtered s1 byte valu e that the receive sts-1/sts- 3 toh processor block has received. these bit-fields are va lid if it has been received for 8 consecutive sts-1 or sts- 3 frames. t able 94: r eceive sts-1/sts-3 t ransport - r eceived k1 b yte v alue r egister (a ddress l ocation = 0 x 021f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filtered_k1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 95: r eceive sts-1/sts-3 t ransport - r eceived k2 b yte v alue r egister (a ddress l ocation = 0 x 0223) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filtered_k2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 96: r eceive sts-1/sts-3 t ransport - r eceived s1 b yte v alue r egister (a ddress l ocation = 0 x 0227) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filtered_s1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 90 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:5] - unused bit [4:3] - frpatout[1:0] bit [2:1] - frpatin[1:0] bit 0 - unused bit [7:0] - los threshold value - msb these read/write bits, along the contents of the rece ive sts-1/sts-3 transport - los threshold value - lsb register is used specify the number of consecutive (all zero) bytes that the receive sts-1/sts-3 toh processor block must detect (within the incoming sts- 1/sts-3 data-stream) before it c an declare the los defect condition. n ote : this register contains the msb (most sign ificant byte) of this 16-bit expression. bit [7:0] - los threshold value - lsb these read/write bits, along the contents of the rece ive sts-1/sts-3 transport - los threshold value - msb register is used to specify the number of consecutive (all zero) bytes that the receive sts-1/st s-3 toh processor block must detect (within the incoming sts-1/sts-3 data- stream) before it can declare the los defect condition. n ote : this register contains the lsb (least significant byte) of this 16-bit expression. bit [7:0] - sf_set_monitor_interval - msb these read/write bits, along the contents of the receive sts-1/sts-3 transport - sf set monitor interval - byte t able 97: r eceive sts-1/sts-3 t ransport - r eceive i n -s ync t hreshold r egister (a ddress = 0 x 022b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused frpatout[1:0] frpatin[1:0] unused r/o r/o r/o r/w r/w r/w r/w r/o 0 0 0 0 0 0 0 0 t able 98: r eceive sts-1/sts-3 t ransport - los t hreshold v alue - msb (a ddress l ocation = 0 x 022e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 los_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 99: r eceive sts-1/sts-3 t ransport - los t hreshold v alue - lsb (a ddress l ocation = 0 x 022f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 los_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 100: r eceive sts-1/sts-3 t ransport - r eceive sf set m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 0231) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH328 91 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 1 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-1/sts-3 toh processor block is ch ecking the incoming sts-1/sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte (or bip-24) errors throughout the user- specified sf defect declaration monitori ng period. if, during this sf defect declaration monitoring period, the receive sts-1/sts-3 toh processor blo ck accumulates more b2 byte (or bip-24) errors than that specified within the receive transport sf set threshold register, then the receive sts- 1/sts-3 toh processor block will declare the sf defect condition. n otes : 1. the value that the user writes into these three (3) sf set monitor window registers, specifies the duration of the sf defect declarati on monitoring period, in terms of ms. 2. this particular register byte contains the msb (mos t significant byte) value of the three registers that specify the sf defect declaration monitoring period. bit [7:0] - sf_set_monitor_i nterval (bits 15 through 8) these read/write bits, along the contents of the receive sts-1/sts-3 transport - sf set monitor interval - byte 2 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-1/sts-3 toh processor block is ch ecking the incoming sts-1/sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte (or bip-24) errors throughout the user- specified sf defect declaration monitoring period. if, duri ng this sf defect declaration monitoring period the receive sts-1/sts-3 toh processor block accumulate more b2 byte (or bip-24) errors than that specified within the receive sts-1/sts-3 transport sf set threshold register, then th e receive sts-1/sts-3 toh processor block will declare the sf defect condition. n ote : the value that the user writes into these three (3) sf set monitor window registers, specifies the duration of the sf defect declaration monitoring period, in terms of ms. bit [7:0] - sf_set_monitor_interval - lsb these read/write bits, along the contents of the receive sts- 1/sts-3 transport - sf set monitor interval - byte 2 and byte 1 registers are used to specify the length of the monito ring period (in terms of ms) for sf (signal failure) defect dec - laration. when the receive sts-1/sts-3 toh processor block is checki ng the incoming sts-1/sts-3 signal in order to determine if it should declare the sf defect condit ion, it will accumulate b2 byte (or bip-24) errors throughout the user-specified sf defect declaration monitoring period. if, during this sf de fect declaration monitoring period, the receive sts-1/sts-3 toh processor block accumulates more b2 byte (or bip-24) errors than that specified wi thin the receive sts-1/sts-3 transport sf set threshold register, then the receive sts- 1/sts-3 toh processor block will declare the sf defect con - dition. t able 101: r eceive sts-1/sts-3 t ransport - r eceive sf set m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 0232) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 102: r eceive sts-1/sts-3 t ransport - r eceive sf set m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 0233) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH328 preliminary 92 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 n otes : 1. the value that the user writes into these three (3) sf set monitor window registers, specifies the duration of the sf defect declarati on monitoring period, in terms of ms. 2. this particular register byte contains the lsb (leas t significant byte) value of the three registers that specify the sf defect declaration monitoring period. bit [7:0] - sf_set _threshold - msb these read/write bits, along the contents of the rece ive sts-1/sts-3 transport - sf set threshold - byte 0 registers are used to specif y the number of b2 byte (or bip-24) errors that will cause the receive sts-1/sts-3 toh processor block to declare the sf (signal failure) defect condition. when the receive sts-1/sts-3 toh processor block is ch ecking for declaring the sf defect condition, it will accumulate b2 byte (or bip-24) errors throughout the sf defect declaration monitoring period. if the number of accumulated b2 byte (or bip-24) errors exceeds that value, which is programmed into this and the receive sts-1/sts- 3 transport sf set threshold - byte 0 register, then the receive sts-1/sts- 3 toh processor block will declare the sf defect condition. n ote : this particular register byte contains the msb (most significant byte) value of this 16-bit expression. bit [7:0] - sf_set_threshold - lsb these read/write bits, along the contents of the rece ive sts-1/sts-3 transport - sf set threshold - byte 1 registers are used to specif y the number of b2 byte (or bip-24) errors that will cause the receive sts-1/sts-3 toh processor block to declare the sf (signal failure) defect condition. when the receive sts-1/sts-3 toh processor block is ch ecking for declaring the sf defect condition, it will accumulate b2 byte (or bip-24) errors throughout the sf de fect monitoring period. if the number of accumulated b2 byt (or bip-24)e errors exceeds that which has been progra mmed into this and the receive sts-1/sts-3 transport sf set threshold - byte 1 register, then the receive sts-1/sts-3 toh processor block will declare the sf defect condition. t able 103: r eceive sts-1/sts-3 t ransport - r eceive sf set t hreshold - b yte 1 (a ddress l ocation = 0 x 0236) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 104: r eceive sts-1/sts-3 t ransport - r eceive sf set t hreshold - b yte 0 (a ddress l ocation = 0 x 0237) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 105: r eceive sts-1/sts-3 t ransport - r eceive sf clear t hreshold - b yte 1 (a ddress l ocation = 0 x 023a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH328 93 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - sf_clear_threshold - msb these read/write bits, along the contents of the receiv e sts-1/sts-3 transport - sf clear threshold - byte 0 registers are used to specify the upper li mit for the number of b2 byte (or bip- 24) errors that w ill cause the receive sts-1/sts-3 toh processor block to clear the sf (signal failure) defect condition. when the receive sts-1/sts-3 toh processor block is checking for clearing the sf defect condition, it will accumulate b2 byte (or bip-24) errors th roughout the sf defect clearance monitoring pe riod. if the number of accumulated b2 byte (or bip-24) errors is less than that programmed in to this and the receive sts-1/sts-3 transport sf clear threshold - byte 0 register, then t he receive sts-1/sts-3 toh processor block clear the sf defect condition. bit [7:0] - sf_clear_threshold - lsb these read/write bits, along the contents of the receiv e sts-1/sts-3 transport - sf clear threshold - byte 1 registers are used to specify the upper li mit for the number of b2 byte (or bip- 24) errors that w ill cause the receive sts-1/sts-3 toh processor block to clear the sf (signal failure) defect condition. when the receive sts-1/sts-3 toh processor block is checking for clearing the sf defect condition, it will accumulate b2 byte (or bip-24) errors th roughout the sf defect clearance monitoring pe riod. if the number of accumulated b2 byte (or bip-24) errors is less than that programmed in to this and the receive sts-1/sts-3 transport sf clear threshold - byte 1 register, then t he receive sts-1/sts-3 toh processor bl ock will clear the sf defect condition. bit [7:0] - sd_set_monitor_interval - msb these read/write bits, along the contents of the receive sts-1/sts-3 transport - sd set monitor interval - byte 1 and byte 0 registers are used to specify the length of the monitoring period (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-1/sts-3 toh processor block is checking the incoming sts-1 or sts-3 signal in order to deter - mine if it should declare the sd defect c ondition, it will accumulate b2 byte (or bip-24) errors throughout the user-specified sd defect declaration monitoring period. if, during this sd defect declaration monitoring period, the receive sts-1/sts- 3 toh processor block accumulates more b2 byte (or bip-24) errors than that specified wi thin the receive sts-1/sts-3 transport sd set threshold register, then the receive sts- 1/sts-3 toh processor block w ill declare the sd defect con - dition. n otes : 1. the value that the user writes into these three (3) sd set monitor window registers, specifies the duration of the sd defect declaration monitoring period, in terms of ms. 2. this particular register byte contains the msb (mos t significant byte) value of the three registers that specify the sd defect declaration monitoring period. t able 106: r eceive sts-1/sts-3 t ransport - r eceive sf clear t hreshold - b yte 0 (a ddress l ocation = 0 x 023b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 107: r eceive sts-1/sts-3 t ransport - r eceive sd s et m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 023d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 94 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - sd_set_monitor_i nterval - bits 15 through 8 these read/write bits, along the contents of the receive sts-1/sts-3 transport - sd set monitor interval - byte 2 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-1/sts-3 toh proc essor block is checking the incoming sts-1 or sts-3 signal in order to determine it it should declare the sd defe ct condition, it will accumulate b2 byte (or bip-24) errors throughout the user- specified sd defect declaration monitoring period. if, during this sd defect declaration monitoring period the receive sts-1/sts-3 toh processor blo ck accumulates more b2 byte (or bip-24) errors than that specified within the receive sts-1/sts-3 transport sd set threshol d register, then the receive sts-1/sts-3 toh processor block will declare the sd defect condition. n ote : the value that the user writes into these three (3) sd set monitor window registers, specifies the duration of the sd defect declaration monitoring period, in terms of ms. bit [7:0] - sd_set_monitor_interval - lsb these read/write bits, along the contents of the receive sts-1/sts-3 transport - sd set monitor interval - byte 2 and byte 1 registers are used to specif y the length of the monitoring period (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-1/sts-3 toh proc essor block is checking the incoming sts-1 or sts-3 signal in order to determine if it should declare the sd defe ct condition, it will accumulate b2 byte (or bip-24) errors throughout the user- speciifed sd defect declaration monitoring period. if, durin g this sd defect declaration monitoring period, the receive sts-1/sts-3 toh processor block accmula ttes more b2 byte (or bip-24) errors than that specified within the receive sts-1/sts-3 transport sd set threshol d register, then the receive sts-1/sts-3 toh processor block will declare the sd defect condition. n otes : 1. the value that the user writes into these three (3) sd set monitor window registers, specifies the duration of the sd defect declaration monitoring period, in terms of ms. 2. this particular register byte contains the lsb (leas t significant byte) value of the three registers that specify the sd defect declaration monitoring period. t able 108: r eceive sts-1/sts-3 t ransport - r eceive sd s et m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 023e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 109: r eceive sts-1/sts-3 t ransport - r eceive sd s et m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 023f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 95 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - sd_set_threshold - msb these read/write bits, along the contents of the rece ive sts-1/sts-3 transport - sd set threshold - byte 0 registers are used to specif y the number of b2 byte (or bip-24) errors that will cause the receive sts-1/sts-3 toh processor block to declare the sd (signal degrade) defect condition. when the receive sts-1/sts-3 toh processor block is ch ecking for declaring the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the sd defect declaration monitoring period. if the number of accumulated b2 byte (or bip-24) errors exceeds that value, which is programmed into this and the receive sts-1/sts- 3 transport sd set threshold - byte 0 register, then th e receive sts-1/sts-3 toh processor block will declare the sd defect condition. bit [7:0] - sd_set_threshold - lsb these read/write bits, along the contents of the rece ive sts-1/sts-3 transport - sd set threshold - byte 1 registers are used to specif y the number of b2 byte (or bip-24) errors that will cause the receive sts-1/sts-3 toh processor block to declare an sd (signal degrade) defect condition. when the receive sts-1/sts-3 toh processor block is ch ecking for declaring the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the sd defect monitoring period. if the number of accumulated b2 byte (or bip-24) errors exceeds that which has been progra mmed into this and the receive sts-1/sts-3 transport sd set threshold - byte 1 register, then the receive sts- 1/sts-3 toh processor block will declare the sd defect condition. bit [7:0] - sd_clear_threshold - msb these read/write bits, along the contents of the receiv e sts-1/sts-3 transport - sd clear threshold - byte 0 registers are used to specify the upper li mit for the number of b2 byte (or bip- 24) errors that w ill cause the receive sts-1/sts-3 toh processor block to clear t he sd (signal degrade) defect condition. when the receive sts-1/sts-3 toh processor block is che cking for clearing the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the sd defect clearance monitoring period. if the number of accumulated b2 byte (or bip-24) errors is less than that programmed into this and the receive sts-1/sts-3 transport t able 110: r eceive sts-1/sts-3 t ransport - r eceive sd set t hreshold - b yte 1 (a ddress l ocation = 0 x 0242) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 111: r eceive sts-1/sts-3 t ransport - r eceive sd set t hreshold - b yte 0 (a ddress l ocation = 0 x 0243) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 112: r eceive sts-1/sts-3 t ransport - r eceive sd clear t hreshold - b yte 1 (a ddress l ocation = 0 x 0246) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH328 preliminary 96 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 sd clear threshold - byte 0 register, then the receive st s-1/sts-3 toh processor block will clear the sd defect condition. bit [7:0] - sd_clear_threshold - lsb these read/write bits, along the contents of the receiv e sts-1/sts-3 transport - sd clear threshold - byte 1 registers are used to specify the upper li mit for the number of b2 byte (or bip- 24) errors that w ill cause the receive sts-1/sts-3 toh processor block to clear t he sd (signal degrade) defect condition. when the receive sts-1/sts-3 toh proc essor block is checking for clearing the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the sd defect clearance monitoring period. if the number of accumulated b2 byte (or bip-24) errors is less than that programmed into this and the receive sts-1/sts-3 transport sd clear threshold - byte 1 register, then the receive st s-1/sts-3 toh processor block will clear the sd defect condition. bit [7:1] - unused bit 0 - sef defect condition force this read/write bit-field is used to force the receive sts-1/sts-3 toh processor block (within the corresponding channel) to declare the sef defect condition. the rece ive sts-1/sts-3 toh processor block will then attempt to reacquire framing. writing a 1 into this bit-field configures the receive sts- 1/sts-3 toh processor block to declare the sef defect. the receive sts-1/sts-3 toh processor block w ill automatically set this bit-field to 0 once it has reacquired framing (e.g., has detected two consecutive sts-1 or sts-3 frames with the correct a1 and a2 bytes). bit [7:5] - unused t able 113: r eceive sts-1/sts-3 t ransport - r eceive sd clear t hreshold - b yte 1 (a ddress l ocation = 0 x 0247) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 114: r eceive sts-1/sts-3 t ransport - f orce sef d efect c ondition r egister (a ddress l ocation = 0 x 024b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused sef force r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 t able 115: r eceive sts-1/sts-3 t ransport - r eceive s ection t race m essage b uffer c ontrol r egister (a ddress l ocation = 0 x 024f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused receive sec - tion trace message buffer read select receive sec - tion trace message accept threshold section trace message alignment type receive section trace mes - sage length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 97 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 4receive section trace message buffer read selection this read/write bit-field is used to specify which of th e following receive section trace message buffer segments to read. ? the actual receive section trace message buffer which contains the contents of the most recently received (and accepted) section trace message via the incoming sts-1 or sts-3 data-stream. ? the expected receive section trace message buffer which contains the contents of the section trace message that the user expects to receive. the contents of this particular buffer are usually specified by the user. ` 0 - executing a read to the receive section trace message buffer address space, will return contents within the actual receive section trace message buffer. ` 1 - executing a read to the receive section trace message buffer address space will return contents within the expected receive section trace message buffer. n ote : in the case of the receive sts-3 toh processor block, the receive section trace message buffer is located at address location 0x0400 through 0x043f. bit 3 - receive section trace message accept threshold this read/write bit-field is used to select the number of consecutive times that the receive sts-1/sts-3 toh processor block must receive a given section trace message, before it is accepted, as de scribed below. once a given section trace message has been accepted then it can be read out of the actual receive se ction trace message buffer. ` 0 - the receive sts-1/sts-3 toh processor block accepts t he section trace message after it has received it the third time in succession. ` 1 - the receive sts-1/sts-3 toh processor block accepts the section trace message after it has received in the fifth time in succession. bit 2 - section trace message alignment type this read/write bit-field is used to specify how the receive sts-1/sts-3 toh processor block will locate the boundary of the section trace message within the inco ming sts-1 or sts-3 data-stream, as indicated below. ` 0 - message boundary is indicated by line feed. ` 1 - message boundary is indicated by the presence of a 1 in the msb of the first byte (within the section trace message). bit [1:0] - receive section trace message length[1:0] these read/write bit-fields are used to specify the le ngth of the section trace message that the receive sts- 1/sts-3 toh processor block will receive. the relations hip between the content of these bit-fields and the corresponding receive section trace message length is presented below trace message length r eceive s ection t race m essage l ength [1:0] r esulting r eceive s ection t race m essage l ength ( in terms of bytes ) 00 1 byte 01 16 bytes 10/11 64 bytes t able 116: r eceive sts-1/sts-3 t ransport - r eceive sd b urst e rror t olerance - b yte 1 (a ddress l ocation = 0 x 0252) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH328 preliminary 98 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - sd_burst_tolerance - msb these read/write bits, along with the contents of the receive sts-1/sts-3 tr ansport - sd burst tolerance - byte 0 registers are used to specify the maximum number of b2 by te (or bip-24) errors that the corresponding receive sts- 1/sts-3 toh processor block can accumulate during a singl e sub-interval period (e.g., an sts-1 or sts-3 frame period), when determining whether or not to decla re the sd (signal degrade) defect condition. n ote : the purpose of this feature is to ar e used to provide some level of b2 error burst filtering, when the receive sts-1/sts-3 toh processor block is accu mulating b2 byte (or bip-24) errors in order to declare the sd defect condition. the user can implement this feature in order to configure the receive sts-1/sts-3 toh processor block to detect b2 bit errors in multiple sub-interv al periods before it will decl are the sd defect condition. bit [7:0] - sd_burst_tolerance - lsb these read/write bits, along with the contents of the receive sts-1/sts-3 tr ansport - sd burst tolerance - byte 1 registers are used to specify the maximum number of b2 by te (or bip-24) errors that the corresponding receive sts- 1/sts-3 toh processor block can accumulate during a singl e sub-interval period (e.g., an sts-1 or sts-3 frame period), when determining whether or not to decla re the sd (signal degrade) defect condition. n ote : the purpose of this feature is to ar e used to provide some level of b2 error burst filtering, when the receive sts-1/sts-3 toh processor block is accu mulating b2 byte (or bip-24) errors in order to declare the sd defect condition. the user can implement this feature in order to configure the receive sts-1/sts-3 toh processor block to detect b2 bit errors in multiple sub-interv al periods before it will decl are the sd defect condition. bit [7:0] - sf_burst_tolerance - msb these read/write bits, along with the co ntents of the receive sts-1/sts-3 transport - sf burst tolerance - byte 0 registers are used to specify the maximum number of b2 by te (or bip-24) errors that the corresponding receive sts- 1/sts-3 toh processor block can accumulate during a singl e sub-interval period (e.g., an sts-1 or sts-3 frame period), when determining whether or not to declare the sf (signal failure) defect condition. n ote : the purpose of this feature is to ar e used to provide some level of b2 error burst filtering, when the receive sts-1/sts-3 toh processor block is accu mulating b2 byte (or bip-24) errors in order to declare the sf defect condition. the user can implement this feature in order to configure the receive sts-1/sts-3 toh processor block to detect b2 bit errors in multiple sub-interv al periods before it will decl are the sf defect condition. t able 117: r eceive sts-1/sts-3 t ransport - r eceive sd b urst e rror t olerance - b yte 0 (a ddress l ocation = 0 x 0253) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 118: r eceive sts-1/sts-3 t ransport - r eceive sf b urst e rror t olerance - b yte 1 (a ddress l ocation = 0 x 0256) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH328 99 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - sf_burst_tolerance - lsb these read/write bits, along with the co ntents of the receive sts-1/sts-3 transport - sf burst tolerance - byte 1 registers are used to specify the maximum number of b2 byte (or bip-24)errors that the corresponding receive sts- 1/sts-3 toh processor block can accumulate during a singl e sub-interval period (e.g., an sts-1 or sts-3 frame period), when determining whether or not to declare the sf (signal failure) defect condition. n ote : the purpose of this feature is to ar e used to provide some level of b2 error burst filtering, when the receive sts-1/sts-3 toh processor block is accu mulating b2 byte (or bip-24) errors in order to declare the sf defect condition. the user can implement this feature in order to configure the receive sts-1/sts-3 toh processor block to detect b2 bit errors in multiple sub-interv al periods before it will decl are the sf defect condition. bit [7:0] - sd_clear_monitor_interval - msb these read/write bits, along the conten ts of the receive sts-1/sts-3 transport - sd clear monitor interval - byte 1 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-1/sts-3 toh processor block is che cking the incoming sts-1 or sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the user- specified sd defect clearance monitoring period. if, during this sd defect clearance monitoring period, the receive sts-1/sts-3 toh processor block accumulates less b2 byte (or bip-24) errors than that programmed into the receive sts-1/sts-3 transport sd clear threshold register, then the receive sts-1/sts-3 toh processor block will clear the sd defect condition. n otes : 1. the value that the user writes into these three (3 ) sd clear monitor window registers, specifies the duration of the sd defect clearance monitoring period, in terms of ms. 2. this particular register byte contains the msb (mos t significant byte) value of the three registers that specifiy the sd defect clearance monitoring period. bit [7:0] - sd_clear_monitor_in terval - bits 15 through 8 t able 119: r eceive sts-1/sts-3 t ransport - r eceive sf b urst e rror t olerance - b yte 0 (a ddress l ocation = 0 x 0257) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 120: r eceive sts-1/sts-3 t ransport - r eceive sd c lear m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 0259) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 121: r eceive sts-1/sts-3 t ransport - r eceive sd c lear m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 025a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH328 preliminary 100 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 these read/write bits, along the conten ts of the receive sts-1/st s-3 transport - sd clear monitor interval - byte 2 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-1/sts-3 toh proc essor block is checking the incoming sts-1 or sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the user- specified sd defect clearance monitoring period. if, during this sd defecf clearance monitoring period, the receive sts-1/sts-3 toh processor block accumula tes less b2 byte (or bip-24) errors than that programmed into the receive sts-1/sts-3 transport sd clear thres hold register, then the receive sts-1/sts-3 toh processor block will clear the sd defect condition. n ote : the value that the user writes into these three (3) sd clear monitor window registers, specifies the duration of the sd defect clearance monitoring period, in terms of ms. bit [7:0] - sd_clear_monitor_interval - lsb these read/write bits, along the conten ts of the receive sts-1/st s-3 transport - sd clear monitor interval - byte 2 and byte 1 registers are used to specif y the length of the monitoring period (in terms of ms) for sd (signal degrade) defect clearance .when the receive sts-1/sts-3 toh processor block is chec king the incoming sts-1 or sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte (or bip-24) errors throughout the user- specified sd defect clearance monitoring period. if, during this sd defect clearance monitoring period, the receive sts-1/sts-3 toh processor block accumula tes less b2 byte (or bip-24) errors than that programmed into the receive sts-1/sts-3 transport sd clear thres hold register, then the receive sts-1/sts-3 toh processor block will clear the sd defect condition n otes : 1. the value that the user writes into these three (3) sd clear monitor window registers, specifies the duration of the sd defect clearance monitoring period, in terms of ms. 2. this particular register byte contains the lsb (leas t significant byte) value of the three registers that specify the sd defect clearance monitoring period. bit [7:0] - sf_clear_monitor_interval - msb these read/write bits, along the contents of the receive st s-1/sts-3 transport - sf clear monitor interval - byte 1 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-1/sts-3 toh proc essor block is checking the incoming sts-1 or sts-3 signal in order to determine if it should clear the sf defec t condition, it will accumulate b2 byte (or bip-24) errors throughout the user- t able 122: r eceive sts-1/sts-3 t ransport - r eceive sd c lear m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 025b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sd_clear_ monitor_ win - dow[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 123: r eceive sts-1/sts-3 t ransport - r eceive sf c lear m onitor i nterval - b yte 2 (a ddress l ocation = 0 x 025d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
preliminary XRT86SH328 101 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications specified sf defect clearance monitoring period. if, duri ng this sf defect clearance monitoring period, the receive sts-1/sts-3 toh processor block accumulates less b2 byte (or bip-24) errors than that programmed into the receive sts-1/sts-3 transport sf clear threshold register, then the receive sts-1/sts-3 toh processor blolck will clear the sf defect condition. n otes : 1. the value that the user writes into these three (3) sf clear monitor window registers, specifies the duration of the sf defect clearance monitoring period, in terms of ms. 2. this particular register byte contains the msb (mos t significant byte) value of the three registers that specify the sf defect clearance monitoring period. bit [7:0] - sf_clear_monitor_i nterval - bits 15 through 8 these read/write bits, along the contents of the receive st s-1/sts-3 transport - sf clear monitor interval - byte 2 and byte 0 registers are used to specif y the length of the monitoring period (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-1/sts-3 toh processor block is che cking the incoming sts-1 or sts-3 signal in order to determine if it should clear the sf defect condition, it will ac cumulate b2 byte (or bip-24) errors throughout the user- specified sf defect clearance monitoring period. if, duri ng this sf defect clearance monitoring period, the receive sts-1/sts-3 toh processor block accumulates less b2 byte (or bip-24) errors than that programmed into the receive sts-1/sts-3 transport sf clear threshold register, then the receive sts-1/sts-3 toh pr ocessor block will clear the sf defect condition. n ote : the value that the user writes into these three (3) sf clear monitor window registers, specifies the duration of the sf defect clearance monitoring period, in terms of ms. bit [7:0] - sf_clear_monitor_interval - lsb these read/write bits, along the contents of the receive st s-1/sts-3 transport - sf clear monitor interval - byte 2 and byte 1 registers are used to specif y the length of the monitoring period (in terms of ms) for sf (signal failure) defect clearance when the receive sts-1/sts-3 toh processor block is che cking the incoming sts-1 or sts-3 signal in order to determine if it should clear the sf defect condition, it will ac cumulate b2 byte (or bip-24) errors throughout the user- specified sf defect clearance monitoring period. if, duri ng this sf defect clearance monitoring period, the receive sts-1/sts-3 toh processor block accumulates less b2 byte (or bip-24) errors than that programmed into the receive sts-1/sts-3 transport sf clear threshold register, then the receive sts-1/sts-3 toh pr ocessor block will clear the sf defect condition. n otes : 1. the value that the user writes into these three (3) sf clear monitor window registers, specifies the duration of the sf defect clearance monitoring period, in terms of ms. t able 124: r eceive sts-1/sts-3 t ransport - r eceive sf c lear m onitor i nterval - b yte 1 (a ddress l ocation = 0 x 025e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 125: r eceive sts-1/sts-3 t ransport - r eceive sf c lear m onitor i nterval - b yte 0 (a ddress l ocation = 0 x 025f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sf_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1
XRT86SH328 preliminary 102 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 2. this particular register byte contains the lsb (leas t significant byte) value of the three registers that specify the sf defect clearance monitoring period. bit 7 - transmit path ais upon declaration of the section trace message unstable defect condition this read/write bit-field is used to configure the re ceive sts-1/sts-3 toh proce ssor block to automatically transmit the path ais (ais-p) indicator via the downstr eam traffic (e.g., towards the receive sts-1/sts-3 poh processor block), anytime it declares the section trace me ssage unstable defect condition within the incoming sts-1 or sts-3 data-stream. ` 0 - does not configure the receive sts-1/sts-3 toh proce ssor block to automatically transmit the ais-p indicator (via the downstream traffic) whenever (and for the duration t hat) it declares the section trace message unstable defect condition. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) whenever (and fo r the duration that) it declares the se ction trace message unstable defect condition. n ote : the user must also set bit 0 (transmit ais-p enab le) to 1 to configure the receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 6 - transmit path ais (ais-p) upon declaration of the section trace message mismatch defect condition this read/write bit-field is used to configure the re ceive sts-1/sts-3 toh proce ssor block to automatically transmit the path ais (ais-p) indicator via the downstr eam traffic (e.g., towards the receive sts-1/sts-3 poh processor blocks), anytime (and for the duration that) it declares the section trace message mi smatch defect condition within the incoming sts-1/sts-3 data stream. ` 0 - does not configure the receive sts-1/sts-3 toh proce ssor block to automatically transmit the ais-p indicator (via the downstream traffic) whenever it declar es the section trace mismatch defect condition. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) whenever (and for the duration that) it declares the se ction trace message mismatch defect condition. n ote : the user must also set bit 0 (transmit ais-p enab le) to 1 to configure the receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 5 - transmit path ais upon declaration of the signal failure (sf) defect condition this read/write bit-field is used to configure the re ceive sts-1/sts-3 toh proce ssor block to automatically transmit a path ais (ais-p) indicator via the downstrea m traffic (e.g., towards the receive sts-1/sts-3 poh processor block), anytime (and for the duration that) it declares the sf defect condition. ` 0 - does not configure the receive st s-1/sts-3 toh processor block to tran smit the ais-p in dicator (via the downstream traffic) upon dec laration of the sf defect. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) anytime (and for the duration that) it decla res the sf defect condition. n ote : the user must also set bit 0 (transmit ais-p enab le) to 1 to configure the receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 4 - transmit path ais upon declaration of the signal degrade (sd) defect t able 126: r eceive sts-1/sts-3 t ransport - a uto ais c ontrol r egister (a ddress l ocation = 0 x 0263) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit ais-p (down- stream) upon section trace mes - sage unsta - ble transmit ais-p (down- stream) upon sec - tion trace message mismatch transmit ais-p (down- stream) upon sf transmit ais-p (down- stream) upon sd unused transmit ais-p (down- stream) upon lof transmit ais-p (down- stream) upon los transmit ais-p (down- stream) enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 103 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this read/write bit-field is used to configure the re ceive sts-1/sts-3 toh proce ssor block to automatically transmit a path ais (ais-p) indicator via the downstrea m traffic (e.g., towards the receive sts-1/sts-3 poh processor block) anytime (and for the duratio n that) it declares the sd defect condition. ` 0 - does not configure the receive st s-1/sts-3 toh processor block to tran smit the ais-p in dicator (via the downstream traffic) upon decla ration of the sd defect. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) anytime (and for the duration that) it dec lares the sd defect condition. n ote : the user must also set bit 0 (transmit ais-p enab le) to 1 to configure th e receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 3 - unused bit 2 - transmit path ais upon declaration of the loss of frame (lof) defect this read/write bit-field is used to configure the re ceive sts-1/sts-3 toh proce ssor block to automatically transmit a path ais (ais-p) indicator via the downstrea m traffic (e.g., towards the receive sts-1/sts-3 poh processor block), anytime (and for the duration that) it declares the lof defect condition. ` 0 - does not configure the receive st s-1/sts-3 toh processor block to tran smit the ais-p in dicator (via the downstream traffic) upon dec laration of the lof defect. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) anytime (and for the duration that) it declare s the lof defect condition. n ote : the user must also set bit 0 (transmit ais-p enab le) to 1 to configure th e receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 1 - transmit path ais upon declaration of the loss of signal (los) defect this read/write bit-field is used to configure the re ceive sts-1/sts-3 toh proce ssor block to automatically transmit a path ais (ais-p) indicator via the downstrea m traffic (e.g., towards the receive sts-1/sts-3 poh processor block), anytime (and for the duration that) it declares the los defect condition. ` 0 - does not configure the receive st s-1/sts-3 toh processor block to tran smit the ais-p in dicator (via the downstream traffic) anytime it declares the los defect condition. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) anytime (and for the duration that) it decla res the los defect condition. n ote : the user must also set bit 0 (transmit ais-p enab le) to 1 to configure th e receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 0 - automatic transmission of ais-p enable this read/write bit-field serves two purposes. it is used to configure the receive st s-1/sts-3 toh processor block to automat ically transmit the path ais (ais-p) indicator, via the down-stream traffic (e.g., towards the receive sts-1/sts-3 poh processor block), upon detection of an sf, sd, section trace mismatch, section trac e unstable, lof or los defect conditions. it also is used to configure the rece ive sts-1/sts-3 toh processor block to au tomatically transmit a path ais (ais- p) indicator via the downstream traffi c (e.g., towards the receive sts-1/st s-3 poh processor block) anytime it declares the ais-l defect condition within the incoming sts-1/sts-3 datastream. ` 0 - configures the receive sts-1/sts-3 toh processor block to not automatically transmit the ais-p indicator (via the downstream traffic) upon declaration of the ais-l defect condition or any of the above-mentioned defect conditions. ` 1 - configures the receive sts-1/sts-3 toh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) upon declaration of the ais-l defect or any of t he above-mentioned defect conditions. n ote : the user must also set the corresponding bit-fields (withi n this register) to 1 in order to configure the receive sts-1/sts-3 toh processor block to automatically transmit the ais-p indicator upon declaration of a given alarm/defect condition.
XRT86SH328 preliminary 104 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:6] - unused bit 5 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the lo s (loss of signal) defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit the ds1/ e1 ais indicator via the downstream ds1/e1 si gnals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor block declares the los defect condition.3 ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signal , anytime the receive sts-1/ sts-3 toh processor block declares the los defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor block declares the los defect condition. bit 4 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the lof (loss of frame) defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit the ds1/ e1 ais indicator via the downstream ds1/e1 si gnals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor bl ock declares the lof defect condition. ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime the receive sts-1/sts-3 toh processor block declares the lof defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor block declares the lof defect condition. bit 3 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the sd (signal degrade) defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit the ds1/ e1 ais indicator via the downstream ds1/e1 si gnals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor block declares the sd defect condition. ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime the receive sts-1/sts-3 toh processor block declares the sd defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor block declares the sd defect condition. bit 2 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the signal fa ilure (sf) defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit t he ds1/e1 ais indicator via the downstream ds1/ e1 signal, anytime (and for the duration that) the receive sts-1/sts-3 toh processor bl ock declares the sf defect condition. ` 0 - does not configures all 28 of the egress direction tr ansmit ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signal , anytime the receive sts-1/ sts-3 toh processor block declares the sf defect condition. t able 127: r eceive sts-1/sts-3 t ransport - a uto ais ( in d ownstream t1/e1 s ) c ontrol r egister (a ddress l ocation = 0 x 026b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit ais (via down - stream t1/e1s) upon los transmit ais (via down - stream t1/e1s) upon lof transmit ais (via down - stream t1/e1s) upon sd transmit ais (via down - stream t1/e1s) upon sf unused transmit ais (via down - stream t1/e1s) enable r/o r/o r/w r/w r/w r/w r/o r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 105 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime (and for the duration that) the receive sts-1/sts-3 toh processor block declares the sf defect condition. bit 1 - unused bit 0 - automatic transmission of ds1/e1 ais (via the downstream ds1/e1s) enable this read/write bit-field serves two purposes.it is us ed to configure each of the 28 egress direction transmit ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator vi a the downstream ds1/e1 signal, upon declaration of either the sf, sd, los or lof defect conditions via the re ceive sts-1/sts-3 toh processor block. it also is used to configur e each of the 28 egress direction transmit ds1/e1 framer blocks to au tomatically transmit the ds1/e1 ais indicator, via its out bound ds1/e1 signals, upon declaration of the ais-l defect condition, via the receive sts-1/sts-3 toh processor block. ` 0 - does not configure all 28 of the egress direction transmit ds1/e1 framer blocks to autom atically transmit the ds1/e1 ais indicator, whenever the receive sts-1/sts-3 to h processor block declares either the los, lof, sd, sf or ais-l defect conditions. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator, whenever (and for the duration that) the receive sts-1/sts-3 toh processor block declares either the los, lof, sd, sf or ais-l defect conditions. bit [7:0] - receive a1, a2 byte er ror count register - msb register this reset-upon-read register, along with the receive st s-1/sts-3 transport - a1, a2 byte error count register - byte 0 presents a 16-bit representation of th e total number of a1 and a2 byte er rors that the rece ive sts-1/sts-3 toh processor block has detected (within the incoming sts-1/ sts-3 data-stream) since the la st read of this register. n ote : this register contains the msb (most significant byte) of this 16-bit expression. bit [7:0] - receive a1, a2 byte er ror count register - lsb register this reset-upon-read register, along with the receive st s-1/sts-3 transport - a1, a2 byte error count register - byte 1 presents a 16-bit representation of the total number of a1 and a2 byte errors that the receive sts-1/sts-3 toh processor block has detected (within the incoming sts-1/ sts-3 data-stream) since the la st read of this register. n ote : this register contains the lsb (least sign ificant byte) of this 16-bit expression. 2.4 receive sts-1 poh pr ocessor block registers the register map for the receive sts-1 poh processor bl ock is presented in the table below. additionally, a detailed description of each of the receive sts-1/sts-3 poh processor block registers is presented below. t able 128: r eceive sts-1/sts-3 t ransport - a1, a2 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 026e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive a1, a2 byte error count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 129: r eceive sts-1/sts-3 t ransport - a1, a2 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 026f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive a1, a2 byte error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 106 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 in order to provide some orientatio n for the reader, an illustration of th e functional block diagram for the XRT86SH328, with the receive sts-1 poh processor block highlighted is presented below in figure 4 . bit [7:2] - unused bit [1:0] - payload_type[1:0] f igure 4. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the r eceive sts-1 poh p rocessor b lock highlighted t able 130: r eceive sts-1 p ath - r eceive c ontrol r egister - b yte 2 (a ddress = 0 x 0281) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused payload_type[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
preliminary XRT86SH328 107 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:4] - unused bit 3 - check (pointer adjustment) stuff select this read/write bit-field is used to enable/disable the so net standard recommendation that a pointer increment or decrement operation, detected within 3 sonet frames of a pr evious pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. ` 0 - disables this sonet standard implement ation. in this mode, all pointer-adj ustment operations that are detected will be accepted. ` 1 - enables this sonet standard implementation. in this mode, all pointer-adjustment o perations that are detected within 3 sonet frame periods of a previous pointer-adjustment operation will be ignored. bit 2 - path - remote defe ct indicator type select this read/write bit-field is used to configure the receiv e sts-1 poh processor block to support either the single- bit or the enhanced rdi-p form of signaling, as described below. ` 0 - configures the receive sts-1 poh proc essor block to support single-bit rdi-p. in this mode, the receive sts-1 poh processor block will only monitor bit 5, within the g1 byte (of the incoming spe data), in order to declare and cl ear the rdi-p defect condition. ` 1 - configures the receive st s-1 poh processor block to su pport enhanced rdi-p (erdi-p). in this mode, the receive sts-1 poh processor block will monito r bits 5, 6 and 7, within the g1 byte, in order to declare and clear the rdi-p defect condition. bit 1 - rei-p error type this read/write bit-field is used to specify how the rece ive sts-1 poh processor block will count (or tally) rei-p events, for performance monitoring purposes. the user c an configure the receive sts-1 poh processor block to increment rei-p events on either a per-bit or per-frame basis. if the user configures the re ceive sts-1 poh processor block to increment rei-p events on a per-bit basis, then it will increment the receive path rei-p error count register by the value of the lower nibble within the g1 byte of the incoming sts-1/sts-3 data-stream. if the user configures the receive sts-1 poh processor block to increment rei-p events on a per-frame basis, then it will increment the receive path rei-p error count register each time it receives an sts- 1/sts-3 frame, in which the lower nibble of the g1 byte (bits 1 through 4) are set to a non-zero value. ` 0 - configures the receive sts-1 poh processor bloc k to count or tally rei-p events on a per-bit basis. ` 1 - configures the receive sts-1 poh processor block to count or tally rei-p events on a per-frame basis. bit 0 - b3 error type this read/write bit-field is used to specify how the receive st s-1 poh processor block will count (or tally) b3 byte errors, for performance monitoring purposes. the user can configure the receive sts-1 poh processor block to increment b3 byte errors on either a per-bit or per-frame basis. if the user configures the re ceive sts-1 poh processor block to increment b3 byte errors on a per-bit basis, then it will increment the receive path b3 byte error count register by the number of bits (within the b3 byte value) that is in error. if the user configures the receive st s-1 poh processor block to increment b3 byte errors on a per-frame basis, then it will increment the receive path b3 byte error count register each time it rece ives an sts-1/sts-3 frame that contains an erred b3 byte. ` 0 - configures the receive sts-1 poh processor bl ock to count b3 byte errors on a per-bit basis ` 1 - configures the receive sts-1 poh processor bloc k to count b3 byte errors on a per-frame basis. t able 131: r eceive sts-1 p ath - r eceive c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0283) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused checkstuff rdi-ptype rei-perror type b3 error type r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 108 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:1] - unused bit 0 - path trace message unstable defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the path trace message unstable defect condition. the receiv e sts-1 poh processor block will declare the path trace message unstable defect condition, whenever the path trac e message unstable counter reaches the value 8. the path trace message unstable counter will be incremented for each time that it receives a path trace message that differs from the previously received message. the path tr ace unstable counter is cleared to 0 whenever the receive sts-1 poh processor block has received a given path trace message 3 (or 5) consecutive times. n ote : receiving a given path trace message 3 (or 5) co nsecutive times also sets this bit-field to 0 ` 0 - indicates that the receive sts-1 poh processor bl ock is not currently declaring the path trace message unstable defect. ` 1 - indicates that the receive sts-1 poh processor blol ck is currently declaring the path trace message unstable defect condition. bit 7 - trace identification mi smatch (tim-p) defect indicator this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the path trace identification mismat ch (tim-p) defect cond ition. the receive sts-1 poh processor block will declare the tim-p defect condition, when none of th e received 64-byte string (received via the j1 byte, within the incoming sts- 1/sts-3 data-stream) matches the expected 64 byte message. the receive sts-1 poh processor block will clear the tim-p defect condition, when 80% of the received 64 byte string (received vi a the j1 byte) matches the expected 64 byte message. ` 0 - indicates that the receive sts-1 poh processor bl ock is not currently declar ing the tim-p defect condition. ` 1 - indicates that the receive sts-1 poh processor bl ock is currently declaring the tim-p defect condition. bit 6 - c2 byte (path signal label byte) unstable defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the path signal label byte unstable defect condition. the re ceive sts-1 poh processor block will declare the c2 (path signal label byte) unstable defect condition, whenever the c2 byte unstable counter reaches the value 5. the c2 byte unstable c ounter will be increment ed for each time that it receives an spe wi th a c2 byte value that differs from the previously received c2 byte value. the c2 byte un stable counter is cleared to 0 whenever the receive sts-1 poh processor block has received 3 (or 5) consecutive spes that eac h contains the same c2 byte t able 132: r eceive sts-1 p ath - c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0286) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused path trace message unstable defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 133: r eceive sts-1 p ath - sonet r eceive poh s tatus - b yte 0 (a ddress l ocation = 0 x 0287) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim-p defect declared c2 byte unstablede - fect declared uneq-pde - fectdeclared plm-pde - fectdeclared rdi-pde - fectdeclared rdi-p unstable - condition lop-pde - fectdeclared ais-pdefect - declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 109 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications value.note:receiving a given c2 byte value in 3 (or 5) consecutive spes also sets this bit-field to 0. ` 0 - indicates that the receive sts-1 po h processor block is currently not decl aring the c2 (path signal label byte) unstable defect condition. ` 1 - indicates that the receive sts-1 poh processor blo ck is currently declaring the c2 (path signal label byte) unstable defect condition. bit 5 - path - unequipped (uneq-p) defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the uneq-p defect condition. the receive sts-1 poh processor block will declare the uneq-p defect condition, anytime that it receives at least five (5) cons ecutive sts-1/sts-3 frames, in which the c2 byte was set to the value 0x00 (which indicates that the spe is unequipped). the receive sts-1 poh processor block will clear the uneq-p defect condition, if it receives at least five (5) consecutive sts-1/sts-3 frames, in which the c2 byte was set to a value other than 0x00. ` 0 - indicates that the receive sts-1 poh processor blo ck is currently not declaring the uneq-p defect condition. ` 1 - indicates that the receive sts-1 poh processor bl ock is currently declaring the uneq-p defect condition. n ote : :the receive sts-1 poh processor block will not decl are the uneq-p defect condition if it configured to expect to receive sts-1/st s-3 frames with c2 bytes being set to 0x 00 (e.g., if the receive sts-1 path - expected path label value register -address location= 0x0297) is set to 0x00. bit 4 - path payload mismatch (plm-p) defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the plm-p defect condition.the receive sts-1 poh processor block will declare the plm-p defect condition, if it receives at least five (5) consecutive sts-1/sts-3 frames, in which th e c2 byte was set to a value other than that which it is expecting to receive. whenever the receive sts-1 poh processor block is determining whether or not it should declare the plm-p defect, it will check the contents of the following two registers. ? the receive sts-1 path - received path label value register (address location= 0xn196). ? the receive sts-1 path - expected path label value register (address location= 0xn197). the receive sts-1 path - expected path label value register contains the value of the c2 bytes, that the receive sts-1 poh processor blocks expects to receive.the receive sts-1 path - received path label value register contains the value of the c2 byte, th at the receive sts-1 poh processor block has most received validated (by receiving this same c2 byte in five consecutive sts-1/st s-3 frames). the receive sts-1 poh processor block will declare the plm-p defect condition if the contents of these two register do not match. the receive sts-1 poh processor block will clear the plm-p defect condition if whenever the contents of these two registers do match. ` 0 - indicates that the receive sts-1 poh processor blo ck is currently not declaring the plm-p defect condition. ` 1 - indicates that the receive sts-1 poh processor bl ock is currently declaring the plm-p defect condition n ote : the receive sts-1 poh processor block will clear the plm-p defect, upon declaring the uneq-p defect condition. bit 3 - path remote defect i ndicator (rdi-p) defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the rdi-p defect condition. if the receive sts-1 poh processor block is configured to support the single-bit rdi-p function, then it will declare the rdi-p defect condition if bit 5 (wit hin the g1 byte of the incoming sts-1/st s-3 frame) is set to 1 for rdi-p_thrd number of incoming consecutive sts-1/sts-3 frames. if the receive sts-1 poh processor block is configured to support the enhanced rdi-p (e rdi-p) function, then it will declare the rdi-p defect condition if bits 5, 6 and 7 (within the g1 byte of the incoming sts-1/sts-3 frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for rdi-p_thrd number of consecutive sts-1/sts-3 frames. ` 0 - indicates that the receive sts-1 poh processor blo ck is not currently declaring the rdi-p defect condition. ` 1 - indicates that the receive sts-1 poh processor bl ock is currently declaring the rdi-p defect condition. n ote : the user can specify the value for rdi-p_thrd by writi ng the appropriate data into bits 3 through 0 (rdi-p thrd) within the receive sts-1 path - sonet receive rdi-p register (address location= 0x0293). bit 2 - rdi-p (path - remote defect indicator) unstable defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the rdi-p unstable defect condition. t he receive sts-1 poh processor block will declare a rdi-p i unstable defect
XRT86SH328 preliminary 110 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 condition whenever the rdi-p unstable counter reaches t he value rdi-p thrd. the rdi-p unstable counter is incremented for each time that the receive sts-1 poh proce ssor block receives an rdi-p va lue that differs from that of the previous sts-1/sts-3 frame. the rdi-p unstable counter is cleared to 0 whenever the same rdi-p value is received in rdi-p_thrd cons ecutive sts-1/sts-3 frames. n ote : receiving a given rdi-p value, in rd i-p_thrd consecutive sts-1/ sts-3 frames also clears this bit-field to 0. ` 0 - indicates that the receive sts-1 poh processor bl ock is not currently declaring the rdi-p unstable defect condition. ` 1 - indicates that the receive sts-1 poh processor block is currently declaring the rdi-p unstable defect condition. n ote : the user can specify the value for rdi-p_thrd by writi ng the appropriate data into bits 3 through 0 (rdi-p thrd) within the receive sts-1 path - sonet receive rdi-p register (address location= 0x0293). bit 1 - loss of pointer indi cator (lop-p) defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the lop-p (loss of pointer) defect condition. the receive sts-1 poh processor block will declare the lop-p defect condition, if it cannot detect a valid pointer (h1 and h2 bytes, within the toh) within 8 to 10 consecutive so net frames. further, the receive sts-1 poh processor block will declare the lop-p defect conditi on, if it detects 8 to 10 consecutiv e ndf events. the receive sts-1 poh processor block will clear the lop-p defect condition, whenever it detects valid pointer bytes (e.g., the h1 and h2 bytes, within the toh) and normal ndf value for thre e consecutive incoming sts-1/sts-3 frames. ` 0 - indicates that the receive sts-1 poh processo r block is not declaring the lop-p defect condition. ` 1 - indicates that the receive sts-1 poh processor bl ock is currently declaring the lop-p defect condition. bit 0 - path ais (ais-p) defect declared this read-only bit-field indicates whether or not the rece ive sts-1 poh processor block is currently declaring the ais-p defect condition. the receive sts-1 poh processor bl ock will declare the ais-p defect condition if it detects all of the following conditions within three consecutive incoming sts-1/sts-3 frames. ? the h1, h2 and h3 bytes are set to an all ones pattern. ? the entire spe is set to an all ones pattern. the receive sts-1 poh processor block will clear the ais- p defect condition when it detects a valid sts-1/sts-3 pointer (h1 and h2 bytes) and a set or normal ndf for three consecutive sts-1/sts-3 frames. ` 0 - indicates that the receive sts-1 poh processor blo ck is not currently declaring the ais-p defect condition. ` 1 - indicates that the receive sts-1 poh processor bl ock is currently declaring the ais-p defect condition n ote : the receive sts-1 poh processor block will not declare the lop-p defect condition if it detects an all ones pattern in the h1, h2 and h3 bytes. it will, instead, declare the ais-p defect condition. bit [7:5] - unused bit 4 - detection of ais pointer interrupt status this reset-upon-read bit-field indicates whether or not th e detection of ais pointer interrupt has occurred since the last read of this register.if this interrupt is enabled, t hen the receive sts-1 poh processor block will generate this interrupt anytime it detects an ais pointer in the incoming sts-1/sts-3 data stream. t able 134: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt s tatus - b yte 2 (a ddress l ocation = 0 x 0289) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused detection of ais pointer interrupt status detection of pointer change interrupt status unused change in tim-p defect condition interrupt status change in path trace message unstable defect condition interrupt status r/o r/o r/o rur rur r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 111 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : an ais pointer is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an all ones pattern. ` 0 - indicates that the detection of ais pointer interrupt has not occurred since the last read of this register. ` 1 - indicates that the detection of ais pointer interrup t has occurred since the last read of this register. bit 3 - detection of pointe r change interrupt status this reset-upon-read bit-field indicate s whether or not the detect ion of pointer change interrupt has occurred since the last read of this register.if this interrupt is enabl ed, then the receive sts-1 po h processor block will generate an interrupt anytime it accepts a new pointer value (e.g., h1 and h2 bytes, in the toh bytes). ` 0 - indicates that the detection of poin ter change interrupt has not occurred si nce the last read of this register. ` 1 - indicates that the detection of po inter change interrupt has occurred sinc e the last read of this register. bit 2 - unused bit 1 - change in tim-p (tr ace identification mismatch ) defect condition interrupt this reset-upon-read bit-field indicate s whether or not the change in tim-p de fect condition interrupt has occurred since the last read of this register.if this interrupt is enab led, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the tim-p defect condition. ? whenever the receive sts-1 poh processor block clears the tim-p defect condition. ` 0 - indicates that the change in tim-p defect condition inte rrupt has not occurred since the last read of this register. ` 1 - indicates that the change in tim-p defect condition inte rrupt has occurred since the last read of this register. bit 0 - change in path trace id entification message unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in path trace message unstable defect condition interrupt has occurred since the last read of this register.if this interrupt is enabled, then the receive sts-1 poh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declare the path trace message unstable defect condition. ? whenever the receive sts-1 poh processor block clears the path trace message unstable defect condition. ` 0 - indicates that the change in path trace message un stable defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in path trace message unstabl e defect condition interrupt has occurred since the last read of this register. bit 7 - new path trace message interrupt status this reset-upon-read bit-field indicates whether or not the new path trace message interrupt has occurred since the last read of this register. t able 135: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt s tatus - b yte 1 (a ddress l ocation = 0 x 028a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new path trace message interrupt status detection of rei-p event interrupt status change in uneq-p defect condition interrupt status change in plm-p defect condition interrupt status new c2 byte interrupt status change in c2 byte unstable defect condition interrupt status change in rdi-p unstable defect condition interrupt status new rdi-p value interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 112 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 if this interrupt is enabled, then the receive sts-1 po h processor block will generate an interrupt anytime it has accepted (or validated) a new path trace message. ` 0 - indicates that the new path trac e message interrupt has not occurred since the last read of this register. ` 1 - indicates that the new path trac e message interrupt has occurred since the last read of this register. bit 6 - detection of rei-p event interrupt status this reset-upon-read bit-field indicates whether or not the detection of rei-p event interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects an rei-p event within the inco ming sts-1/sts-3 data-stream. ` 0 - indicates that the detection of rei-p event interrupt has not occurred since the last read of this register. ` 1 - indicates that the detection of rei-p event interrupt has occurred since the last read of this register. bit 5 - change in uneq-p (path - unequipped) defect condition interrupt status this reset-upon-read bit-field indicates whether or no t the change in uneq-p defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following conditions. ? when the receive sts-1 poh processor bl ock declares the uneq-p defect condition. ? when the receive sts-1 poh processor bl ock clears the uneq-p defect condition. ` 0 - indicates that the change in uneq-p defect condition interrupt has not occurred sinc e the last read of this register. ` 1 - indicates that the change in uneq-p defect condition inte rrupt has occurred since the last read of this register. n ote : the user can determine if the receive sts-1 poh proc essor block is currently declaring the uneq-p defect condition by reading out the state of bit 5 (uneq-p defect declared) wit hin the receive sts-1 path - sonet receive poh status - byte 0 register (address location= 0xn187). bit 4 - change in plm-p (path - payload mismatch) defect condition interrupt status this reset-upon-read bit indicates whether or not the change in plm-p defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following conditions. ? when the receive sts-1 poh processor block declares the plm-p defect condition. ? when the receive sts-1 poh processor block clears the plm-p defect condition. ` 0 - indicates that the change in plm-p defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in plm-p defect condition inte rrupt has occurred since the last read of this register. bit 3 - new c2 byte interrupt status this reset-upon-read bit-field indicates whether or not th e new c2 byte interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 po h processor block will generate an interrupt anytime it has accepted a new c2 byte. ` 0 - indicates that the new c2 byte interrupt has not occurred since the last read of this register. ` 1 - indicates that the new c2 by te interrupt has occurred since the last read of this register. bit 2 - change in c2 byte unstable de fect condition interrupt status this reset-upon-read bit-field indicates whether or not th e change in c2 byte unstable defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following events. ? when the receive sts-1 poh processor block decla res the c2 byte unstable defect condition. ? when the receive sts-1 poh processor block clears the c2 byte unstable defect condition.
preliminary XRT86SH328 113 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 0 - indicates that the change in c2 byte unstable defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in c2 byte unstable defect c ondition interrupt has occurred since the last read of this register. n ote : the user can determine whether or not the receive sts-1 poh processor block is currently declaring the c2 byte unstable defect condition by reading out the state of bit6 (c2 byte unstable defect declared) within the receive sts-1 path - sonet rece ive poh status - byte 0 register (address location= 0x0287). bit 1 - change in rdi-p unstable defect condition interrupt status this reset-upon-read bit-field indicates whether or not the change in rdi-p unstable defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following conditions. ? when the receive sts-1 poh processor block declares an rdi-p unstable defect condition. ? when the receive sts-1 poh processor block clears the rdi-p unstable defect condition. ` 0 - indicates that the change in rdi-p unstable defect cond ition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in rdi-p unstable defect cond ition interrupt has occurred since the last read of this register. n ote : the user can determine the current st ate of rdi-p unstable defect conditi on by reading out the state of bit 2 (rdi-p unstable defect condition) within the receiv e sts-1 path - sonet receive poh status - byte 0 register (address location= 0x0287). bit 0 - new rdi-p value interrupt status this reset-upon-read bit-field indicates whether or not th e new rdi-p value interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh pr ocessor block will generate this interrupt anytime it receives and validates a new rdi-p value. ` 0 - indicates that the new rdi-p value interrupt has not occurred since the last read of this register. ` 1 - indicates that the new rdi-p value interrupt has occurred since the last read of this register. n ote : the user can obtain the new rdi-p value by reading ou t the contents of the rdi-p accept[2:0] bit-fields. these bit-fields are located in bits 6 through 4, within the receive sts-1 path - sonet receive rdi-p register (address location= 0x0293). bit 7 - detection of b3 by te error interrupt status this reset-upon-read bit-field indicates whether or not th e detection of b3 byte error interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a b3 byte error in the incoming sts-1/sts-3 data stream. ` 0 - indicates that the detection of b3 byte error interrupt has no t occurred since the last read of this interrupt. t able 136: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt s tatus - b yte 0 (a ddress l ocation = 0 x 028b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 detection of b3 byte error interrupt status detection of new pointer interrupt status detection of unknown pointer interrupt status detection of pointer dec - rement interrupt status detection of pointer increment interrupt status detection of ndf pointer interrupt status change of lop-p defect condition interrupt status change of ais-p defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 114 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 1 - indicates that the detection of b3 byte error interrupt has occurred since the last read of this interrupt. bit 6 - detection of new pointer interrupt status this reset-upon-read indicates whether the detection of ne w pointer interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a new pointer value in the incoming sts-1/sts-3 frame. n ote : pointer adjustments with ndf will not generate this interrupt. ` 0 - indicates that the detection of new pointer interrupt has not occurred since the last read of this register. ` 1 - indicates that the detection of new pointer interrupt has occurred since the last read of this register. bit 5 - detection of unknow n pointer interrupt status this reset-upon-read bit-field indicates whether or not the detection of unknown pointer interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime that it detects a pointer that does not fit in to any of the following categories. ? an increment pointer ? a decrement pointer ? an ndf pointer ? an ais (e.g., all ones) pointer ? new pointer ` 0 - indicates that the detection of unkn own pointer interrupt has no t occurred since the last read of this register. ` 1 - indicates that the detection of un known pointer interrupt has occurred since the last read of this register. bit 4 - detection of pointer decrement interrupt status this reset-upon-read bit-field indicates whether or not the detection of pointer decrement interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a pointer decrement event. ` 0 - indicates that the detection of pointer decrement interr upt has not occurred since the last read of this register. ` 1 - indicates that the detection of pointer decrement inte rrupt has occurred since the last read of this register. bit 3 - detection of pointe r increment interrupt status this reset-upon-read bit-field indicates whether or not the detection of pointer increment interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it det ects a pointer increment event. ` 0 - indicates that the detection of poin ter increment interrupt has not occurred si nce the last read of this register. ` 1 - indicates that the detection of po inter increment interrupt has occurred si nce the last read of this register. bit 2 - detection of ndf pointer interrupt status this reset-upon-read bit-field indicates whether or not the detection of ndf pointer interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects an ndf pointer event. ` 0 - indicates that the detection of ndf pointer interrupt has not occurred since the la st read of this register. ` 1 - indicates that the detection of ndf pointer interrupt has occurred since the last read of this register. bit 1 - change of lop-p defe ct condition interrupt status this reset-upon-read bit-field indicates whether or not the change in lop-p defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following events. ? when the receive sts-1 poh processor bl ock declares the lop-p defect condition.
preliminary XRT86SH328 115 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ? when the receive sts-1 poh processor bl ock clears the lop-p defect condition. ` 0 - indicates that the change in lop-p defect condition interrupt has not occurred si nce the last read of this register. ` 1 - indicates that the change in lop-p defect condition in terrupt has occurred since the last read of this register. n ote : the user can determine if the receive sts-1 poh proc essor block is currently declaring the lop-p defect condition by reading out the state of bit 1 (lop-p de fect declared) within the receive sts-1 path - sonet receive poh status - byte 0 register (address location=0x0287). bit 0 - change of ais-p def ect condition interrupt status this reset-upon-read bit-field indicate s whether or not the chan ge of ais-p defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the ais-p defect condition. ? whenever the receive sts-1 poh processor block clears the ais-p defect condition. ` 0 - indicates that the change of ais-p defect condition inte rrupt has not occurred since the last read of this register. ` 1 - indicates that the change of ais-p defect condition inte rrupt has occurred since the last read of this register. n ote : the user can determine if the receive sts-1 poh proc essor block is currently declaring the ais-p defect condition by reading out the state of bit 0 (ais-p defect declared) wit hin the receive sts-1 path - sonet receive poh status - byte 0 register (address location= 0x0287). bit [7:5] - unused bit 4 - detection of ais pointer interrupt enable this read/write bit-field is used to either enable or disable the detection of ais pointer interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects an ais pointer, in the incomi ng sts-1/sts-3 data stream. n ote : an ais pointer is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an all ones pattern. ` 0 - disables the detection of ais pointer interrupt. ` 1 - enables the detection of ais pointer interrupt. bit 3 - detection of pointe r change interrupt enable this read/write bit-field is used to either enable or disable the detection of pointer change interrupt. if this interrupt is enabled, then the receive sts-1 po h processor block will generate an interrupt anytime it has accepted a new pointer value. ` 0 - disables the detection of pointer change interrupt. ` 1 - enables the detection of pointer change interrupt. t able 137: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt e nable - b yte 2 (a ddress l ocation = 0 x 028d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused detection of ais pointer interrupt enable detection of pointer change interrupt enable unused change in tim-p defect condition interrupt enable change in path trace message unstable defect condition interrupt enable r/o r/o r/o r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 116 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 2 - unused bit 1 - change in tim-p (tr ace identification mismatch ) defect condition interrupt this read/write bit-field is used to either enable or disable the change in tim-p condition interrupt. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following events. ? if the tim-p defect condition is declared. ? if the tim-p defect condition is cleared. ` 0 - disables the change in tim-p defect condition interrupt. ` 1 - enables the change in tim-p defect condition interrupt. bit 0 - change in path trace message unstable defect condition interrupt status this read/write bit-field is used to either enable or di sable the change in path trace message unstable defect condition interrupt. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block de clares the path trace message unstable defect condition. whenever the receive sts-1 poh proce ssor block clears the path trace message unstable defect condition. ` 0 - disables the change in path trace message unstable defect condition interrupt. ` 1 - enables the change in path trace message unstable defect condition interrupt. bit 7 - new path trace message interrupt enable this read/write bit-field is used to either enabl e or disable the new path trace message interrupt. if this interrupt is enabled, then the receive sts-1 po h processor block will generate an interrupt anytime it has accepted (or validated) and new path trace message. ` 0 - disables the new path trace message interrupt. ` 1 - enables the new path trace message interrupt. bit 6 - detection of rei-p event interrupt enable this read/write bit-field is used to either enable or disable the detection of rei-p event interrupt. if this interrupt is enabled, then he rece ive sts-1 poh processor block will gene rate an interrupt anytime it detects an rei-p condition in the co ming sts-1/sts-3 data-stream. ` 0 - disables the detection of rei-p event interrupt. ` 1 - enables the detection of rei-p event interrupt. bit 5 - change in uneq-p (path - unequi pped) defect condition interrupt enable this read/write bit-field is used to either enable or disable the change in uneq-p defect condition interrupt. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following conditions t able 138: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt e nable - b yte 1 (a ddress l ocation = 0 x 028e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 new path trace mes - sage inter - rupt enable detection of rei-p event interrupt enable change in uneq-p defect con - dition inter - rupt enable change in plm-p defect con - dition inter - rupt enable new c2 byte interrupt enable change in c2 byte unstable defect con - dition inter - rupt enable change in rdi-p unstable defect con - dition inter - rupt enable new rdi- pvalue inter - rupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 117 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ? when the receive sts-1 poh processor bl ock declares the uneq-p defect condition. ? when the receive sts-1 poh processor bl ock clears the uneq-p defect condition. ` 0 - disables the change in uneq-p defect condition interrupt. ` 1 - enables the change in uneq-p defect condition interrupt. bit 4 - change in plm-p (path - payload labe l mismatch) defect cond ition interrupt enable this read/write bit is used to either enable or disable the change in plm-p defect condition interrupt. if this interrupt is enabled, then the rece ive sts-1 poh processor block will genera te an interrupt in response to either of the following conditions. ? whenever the receive sts-1 poh processor bl ock declares the plm-p defect condition. ? whenever the receive sts-1 poh processor block clears the plm-p defect condition. ` 0 - disables the change in plm-p defect condition interrupt. ` 1 - enables the change in plm-p defect condition interrupt. bit 3 - new c2 byte interrupt enable this read/write bit-field is used to either enable or disable the new c2 byte interrupt. if this interrupt is enabled, then th e receive sts-1 poh processor block will generate an interrupt anytime it has accepted a new c2 byte. ` 0 - disables the new c2 byte interrupt. ` 1 - enables the new c2 byte interrupt. n ote : the user can obtain the value of this new c2 byte by reading the contents of the receive sts-1 path - received path label value register (address location= 0x0296). bit 2 - change in c2 by te unstable defect condition interrupt enable this read/write bit-field is used to either enable or di sable the change in c2 byte unstable condition interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will gener ate an interrupt in response to either of the following events. ? when the receive sts-1 poh processor block dec lares the c2 byte unstable defect condition. ? when the receive sts-1 poh processor block clea rs the c2 byte unstable defect condition. ` 0 - disables the change in c2 byte unstable defect condition interrupt. ` 1 - enables the change in c2 byte unstable defect condition interrupt. bit 1 - change in rdi-p unstable defect condition interrupt enable this read/write bit-field is used to either enable or disa ble the change in rdi-p unstable defect condition interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will gener ate an interrupt in response to either of the following conditions. ? whenever the receive sts-1 poh processor blo ck declares the rdi-p unstable defect condition. ? whenever the receive sts-1 poh processor block clears the rdi-p unstable defect condition. ` 0 - disables the change in rdi-p unstable defect condition interrupt. ` 1 - enables the change in rdi-p unstable defect condition interrupt. bit 0 - new rdi-p value interrupt enable this read/write bit-field is used to either enable or disabl e the new rdi-p value interrupt.if this interrupt is enabled, then the receive sts-1 poh processor block will generate this interrupt anytime it receives and validates a new rdi- p value. ` 0 - disables the new rdi-p value interrupt. ` 1 - enable the new rdi-p value interrupt.
XRT86SH328 preliminary 118 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - detection of b3 byte error interrupt enable this read/write bit-field is used to either enable or disable the detection of b3 byte error interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a b3-byte error in the incomi ng sts-1/sts-3 data-stream. ` 0 - disables the detection of b3 byte error interrupt. ` 1 - enables the detection of b3 byte error interrupt. bit 6 - detection of new pointer interrupt enable this read/write bit-field is used to either enable or disable the detection of new pointer interrupt. if this interrupt is enabled, then the re ceive sts-1 poh processor block will generate an interrupt anytime it detects a new pointer value in the incoming sts-1/sts-3 frame. n ote : :pointer adjustment s with ndf will not gener ate this interrupt. ` 0 - disables the detection of new pointer interrupt. ` 1 - enables the detection of new pointe r interrupt. bit 5 - detection of unknow n pointer inte rrupt enable this read/write bit-field is used to either enable or disable the detection of unknown pointer interrupt. if this interrupt is enabled, then the re ceive sts-1 poh processor block will generate an interrupt anytime it detects a pointer adjustment that does not fit into any of the followi ng categories. an increment pointer. a decrement pointer an ndf pointer ais pointer new pointer. ` 0 - disables the detection of unknown pointer interrupt. ` 1 - enables the detection of unknown pointer interrupt. bit 4 - detection of pointer decrement interrupt enable this read/write bit-field is used to enable or di sable the detection of po inter decrement interrupt. if this interrupt is enabled, then the receive sts-1/sts-3 toh processor block will generate an interrupt anytime it detects a pointer-decrement event. ` 0 - disables the detection of pointer decrement interrupt. ` 1 - enables the detection of pointer decrement interrupt. bit 3 - detection of pointe r increment interrupt enable this read/write bit-field is used to either enable or disable the detection of pointer increment interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a pointer increment event. ` 0 - disables the detection of pointer increment interrupt. ` 1 - enables the detection of pointer increment interrupt. bit 2 - detection of ndf pointer interrupt enable this read/write bit-field is used to either enable or disable the detection of ndf pointer interrupt. if this interrupt is enabled, then the re ceive sts-1 poh processor block will generate an interrupt anytime it detects t able 139: r eceive sts-1 p ath - sonet r eceive p ath i nterrupt e nable - b yte 0 (a ddress l ocation = 0 x 028f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 detection of b3 byte errorinter - ruptenable detection of new pointer interrupt enable detection of unknown pointer inter - rupt enable detection of pointer dec - rement inter - rupt enable detection of pointer incrementin - terrupt enable detection of ndf pointer - interrupt enable change of lop-p defectcondi - tion interrupt enable change of ais-p defectcondi - tioninterrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 119 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications an ndf pointer event. ` 0 - disables the detection of ndf pointer interrupt. ` 1 - enables the detection of ndf pointer interrupt. bit 1 - change of lop-p defe ct condition interrupt enable this read/write bit-field is used to either enable or dis able the change in lop (loss of pointer) condition interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will gener ate an interrupt in response to either of the following events. ? when the receive sts-1 poh processor block declares the lop-p defect condition condition. ? when the receive sts-1 poh processor blo ck clears the lop-p defect condition. ` 0 - disable the change of lop-p defect condition interrupt. ` 1 - enables the change of lop-p defect condition interrupt. n ote : the user can determine the current state of the lop-p de fect condition by reading out the contents of bit 1 (lop-p defect declared) within the receive sts-1 path - sonet receive poh status - byte 0 (address location= 0x0287). bit 0 - change of ais-p def ect condition interrupt enable this read/write bit-field is used to either enable or disable the change of ais-p (path ais) defect condition interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will gener ate an interrupt in response to either of the following events. ? when the receive sts-1 poh processor blo ck declares the ais-p defect condition. ? when the receive sts-1 poh processor blo ck clears the ais-p defect condition. ` 0 - disables the change of ais-p defect condition interrupt. ` 1 - enables the change of ais-p defect condition interrupt. n ote : the user can determine the current state of the ais-p de fect condition by reading out the contents of bit 0 (ais-p defect declared) within the receive sts-1 pa th - sonet receive poh status - byte 0 (address location= 0x0287). bit 7 - unused bit [6:4] - accepted rdi-p value these read-only bit-fields contain the va lue of the most recently accepted rdi-p (e.g., bits 5, 6 and 7 within the g1 byte) value that has been accepted by the receive sts-1 poh processor block. n ote : a given rdi-p value will be accepted by the receive sts- 1 poh processor block, if this rdi-p value has been consistently received in rdi-p threshol d[3:0] number of sts-1/sts-3 frames. bit [3:0] - rdi-p threshold[3:0] these read/write bit-fields are used to defined the rdi-p acceptance threshold for the receive sts-1 poh processor block. the rdi-p acceptance threshold is th e number of consecutive sts-1/sts-3 fr ames, in which the receive sts-1 poh processor block must receive a given rdi-p value, before it accepts or validates it. the most recently accepted rdi-p value is written into the rdi-p accept[2:0] bit-fiel ds, within this register. t able 140: r eceive sts-1 p ath - sonet r eceive rdi-p r egister (a ddress l ocation = 0 x 0293) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused rdi-p_accept[2:0] rdi-p threshold[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 120 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - received filtered c2 byte value these read-only bit-fields contain the value of the most recently accepted c2 byte, via the receive sts-1 poh processor block. the receive sts-1 poh processor block will accept a c2 byte va lue (and load it into these bit-fields) if it has received a consistent c2 byte, in five (5 ) consecutive sts-1/sts-3 frames. n ote : the receive sts-1 poh processor block uses this regi ster, along the receive sts-1 path - expected path label value register (address location = 0x0297), when declaring or clearing the uneq-p and plm-p defect conditions. bit [7:0] - expected c2 byte value these read/write bit-fields are used to specify the c2 (path label byte) value, that the receive sts-1 poh processor block should expect when declaring or clearing the uneq-p and plm-p defect conditions. if the contents of the received c2 byte value[7:0] (see receive sts-1 path - received path label value register) matches the contents in these register, then the re ceive sts-1 poh will not declare any defect conditions. n ote : the receive sts-1 poh processor block uses this register, along with the receive sts-1 path - receive path label value register (address location = 0x0296), when declaring or clearing the uneq-p and plm-p defect conditions. bit [7:0] - b3 byte error count - msb this reset-upon-read register, along with receive sts-1 pa th - b3 byte error count register - bytes 2 through 0, function as a 32 bit counter, which is incremented anytim e the receive sts-1 poh processor block detects a b3 byte error. n otes : 1. if the receive sts-1 poh processor block is configur ed to count b3 byte errors on a per-bit basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1/sts-3 spe) that are in error. 2. if the receive sts-1 poh processo r block is configured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts-1/sts-3 spe that contains an erred b3 byte. t able 141: r eceive sts-1 p ath - r eceived p ath l abel v alue (a ddress l ocation = 0 x 0296) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 received_c2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 1 1 1 1 1 1 1 1 t able 142: r eceive sts-1 p ath - e xpected p ath l abel v alue (a ddress l ocation = 0 x 0297) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 expected_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 t able 143: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 3 (a ddress l ocation = 0 x 0298) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 121 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - b3 byte error count (bits 23 through 16) this reset-upon-read register, along with receive sts-1 pa th - b3 byte error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremented anytim e the receive sts-1 poh processor block detects a b3 byte error. n otes : 1. if the receive sts-1 poh processor block is configur ed to count b3 byte errors on a per-bit basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1/sts-3 spe) that are in error. 2. if the receive sts-1 poh processo r block is configured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts-1/sts-3 spe that contains an erred b3 byte. bit [7:0] - b3 byte error count - (bits 15 through 8) this reset-upon-read register, along with receive sts-1 pa th - b3 byte error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremented anytim e the receive sts-1 poh processor block detects a b3 byte error. n otes : 1. if the receive sts-1 poh processor bl ock is configured to count b3 byte errors on a per-bit basis, then it will increment this 32 bit c ounter by the number of bits, within the b3 byte (of ea ch incoming sts-1/sts-3 spe) that are in error. 2. if the receive sts-1 poh processor block is configured to count b3 byte errors on a per-frame basis, then it will increment this 32 bit c ounter each time that it rece ives an sts-1/sts-3 spe that contains an erred b3 byte. bit [7:0] - b3 byte error count - lsb this reset-upon-read register, along with receive sts-1 pa th - b3 byte error count register - bytes 3 through 1 function as a 32 bit counter, which is incremented anytim e the receive sts-1 poh processor block detects a b3 byte error. n otes : t able 144: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 2 (a ddress l ocation = 0 x 0299) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 145: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 1 (a ddress l ocation = 0 x 029a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 146: r eceive sts-1 p ath - b3 b yte e rror c ount r egister - b yte 0 (a ddress l ocation = 0 x 029b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 122 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 1. if the receive sts-1 poh processor block is configur ed to count b3 byte errors on a per-bit basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1/sts-3 spe) that are in error. 2. f the receive sts-1 poh processor block is configur ed to count b3 byte errors on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts-1/sts-3 spe that contains an erred b3 byte. bit [7:0] - rei-p event count - msb this reset-upon-read register, along with receive sts-1 path - rei-p error count register - bytes 2 through 0, function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a path - remote error indicator event within t he incoming sts-1/sts-3 spe data-stream. n otes : 1. if the receive sts-1 poh processor block is configured to count rei-p events on a per-bit basis, then it will increment this 32 bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1/sts-3 spe. 2. if the receive sts-1 poh processor blo ck is configured to count rei-p events on a per-frame basis, then it will increment this 32 bit counter each time that it rece ives an sts-1/sts-3 spe that contains a non-zero rei-p value. bit [7:0] - rei-p event count (bits 23 through 16) this reset-upon-read register, along with receive sts-1 path - rei-p error count register - bytes 3, 1 and 0, function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a path - remote error indicator event within the inconing sts-1/sts-3 spe data-stream. n otes : 1. if the receive sts-1 poh processor block is configur ed to count rei-p events on a per-bit basis, then it will increment this 32 bit counter by the nibble-value with in the rei-p field of the incoming g1 byte within each incoming sts-1/sts-3 frame. 2. if the receive sts-1 poh processor block is confi gured to count rei-p events on a per-frame basis, then it will increment this 32 bit c ounter each time that it receives an sts-1/sts-3 spe that contains a non- zero rei-p value. t able 147: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 3 (a ddress l ocation = 0 x 029c) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 148: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 2 (a ddress l ocation = 0 x 029d) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 149: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 1 (a ddress l ocation = 0 x 029e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 123 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - rei-p event co unt - (bits 15 through 8) this reset-upon-read register, along with receive sts-1 path - rei-p error count register - bytes 3, 2 and 0, function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a path - remote error indicator event within t he incoming sts-1/sts-3 spe data-stream. n otes : 1. if the receive sts-1 poh processor block is configur ed to count rei-p events on a per-bit basis, then it will increment this 32 bit counter by the nibble-value with in the rei-p field of the incoming g1 byte within each incoming sts-1/sts-3 spe. 2. if the receive sts-1 poh processor block is confi gured to count rei-p events on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts-1/sts-3 spe that contains a non- zero rei-p value bit [7:0] - rei-p event count - lsb this reset-upon-read register, along with receive sts-1 path - rei-p error count register - bytes 3 through 1, function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a path - remote error indicator event within t he incoming sts-1/sts-3 spe data-stream. n otes : 1. if the receive sts-1 poh processor block is configur ed to count rei-p events on a per-bit basis, then it will increment this 32 bit counter by the nibble-va lue within the rei-p field of the incoming g1 byte. 2. if the receive sts-1 poh processor block is confi gured to count rei-p events on a per-frame basis, then it will increment this 32 bit counter each time that it receives an sts-1/sts-3 spe that contains a non- zero rei-p value. bit [7:6] - unused bit 5 - new message ready this read/write bit-field indicates whether or not th e receive path trace message buffer has received a new expected value. ` 0 - indicates no new expected value has been downloaded into the receive j1 trace buffer. ` 1 - indicates a new expected value has been downloaded into the receive j1 trace buffer and can be used to make comparisons with the accepted j1 message. bit 4 - receive section trace message buffer read selection this read/write bit-field is used to specify which of the following receive path trace message buffer segments to t able 150: r eceive sts-1 p ath - rei-p e vent c ount r egister - b yte 0 (a ddress l ocation = 0 x 029f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-p_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 151: r eceive sts-1 p ath - r eceive p ath t race m essage b uffer c ontrol r egister (a ddress l ocation = 0 x 02a3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused new message ready receive path trace message buffer read select receive path trace message accept threshold path trace message alignment type receive path trace message length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 124 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 read. a. the actual receive path trace message buffer. the actual receive path trace message buffer contains the contents of the most recently received (and accepted) pa th trace message via the inco ming sts-1/sts-3 data-stream. b. the expected receive path trace message buffer. the expected receive path trace message buffer contains the contents of the path trace message th at the user expects to receive. the contents of this particular buffer are usually specified by the user. ` 0 - executing a read to the receive j1 trace buffer, will return contents within the valid message buffer. ` 1 - executing a read to the receive j1 trace buffer, will return contents within the expected message buffer. n ote : in the case of the receive sts-1 po h processor block, the receive j1 tr ace buffer is located at address location 0x0500 through 0x053f. bit 3 - path trace message accept threshold this read/write bit-field is used to select the number of consecutive times that the receive sts-1 poh processor block must receive a given receive trace message, before it is accepted and loaded into the receive path trace message. ` 0 - the receive sts-1 poh processor block accepts the path trace message after it has re ceived it the third time in succession. ` 1 - the receive sonet poh processor block accepts the inco ming path trace message after it has received in the fifth time in succession. bit 2 - path trace message alignment type this read/write bit-field is used to specify have the receive sts-1 poh processor block will locate the boundary of the j1 trace message. ` 0 - message boundary is indicated by line feed. ` 1 - message boundary is indicated by the presence of a 1 in the msb of a the first byte (within the j1 trace message). bit [1:0] - path trace message length[1:0] these read/write bit-fields are used to specify the length of the receive path trace message that the receive sts- 1 poh processor block will receive. the relationship between the content of these bit-fi elds and the corresponding receive path trace message length is presented below. bit [7:2] - unused bit [1:0] current pointer value - msb these read-only bit-fields, along with that from the rece ive sts-1 path - pointer value - byte 0 register combine to reflect the current value of the pointer that the receive sts-1 poh processor block is using to locate the spe within the incoming sts-1/sts-3 data stream.note these register bits comprise the upper byte value of the pointer value. receive trace path message length msg length[1:0] r esulting p ath t race m essage l ength 00 1 byte 01 16 bytes 10/11 64 bytes t able 152: r eceive sts-1 p ath - p ointer v alue - b yte 1 (a ddress l ocation = 0 x 02a6) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused current_pointer val - uemsb[9:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 125 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - current pointer value - lsb these read-only bit-fields, along with that from the rece ive sts-1 path - pointer value - byte 1 register combine to reflect the current value of the pointer that the receive sts-1 poh processor block is using to locate the spe within the incoming sts-1/sts-3 data stream.note these register bits comprise the lower byte value of the pointer value. bit [7:0] - defect_c2_byte_value[7:0] these read/write bit-fields are used to configure the receive sts-1 poh processor bl ock to automatically force the transmission of the ds1/e1 ais pattern (in the egress dir ection of all 28 channels) anytime it accepts a c2 byte value matching that written into this register. n ote : the chip will only automatically transmit the ds1/e1 ai s pattern if bit 1 (defect c2 byte downstream ais enable), within the receive sts-1 path - receive au to ais - c2 byte control register is set to 1. bit [7:2] - unused bit 1] - defect c2 byte downstream ais enable bit 0 - unused t able 153: r eceive sts-1 p ath - p ointer v alue - b yte 0 (a ddress l ocation = 0 x 02a7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 current_pointer_value_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 154: r eceive sts-1 p ath - r eceive a uto ais - c2 b yte v alue r egister (a ddress = 0 x 02b9) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 defect_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 155: r eceive sts-1 p ath - r eceive a uto ais - c2 b yte c ontrol r egister (a ddress = 0 x 02ba) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused defect c2 byte down - stream ais enable unused r/o r/o r/o r/o r/o r/o r/w r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 126 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - unused bit 6 - transmit path ais (downstream) upon declaration of the unstable c2 byte defect condition this read/write bit-field is used to configure the receiv e sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator vi a the downstream traffic (e.g., towards eac h of the 28 egress direction transmit ds1/e1 framer blocks), anytime (and for the durati on that) it declares the un stable c2 byte defect cond ition within the incoming sts-1/sts-3 data-stream. ` 0 - does not configure the receive sts-1 poh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) whenever it declares the unstable c2 byte defect condition. ` 1 - configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the downstream traffic) whenever it declares the unstable c2 byte defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 5 - transmit path ais (downstream) upon declaratio n of the uneq-p (path - uneq uipped) defect condition this read/write bit-field is used to configure the receiv e sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator vi a the downstream traffic (e.g., towards eac h of the 28 egress direction transmit ds1/e1 framer blocks), anytime (and for the duration th at) it declares the une q-p defect condition. ` 0 - does not configure the receive sts-1 poh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) whenever it dec lares the uneq-p defect condition. ` 1 - configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the downstream traffic) whenever it dec lares the uneq-p defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 4 - transmit path ais (downstream) upon declaratio n of the plm-p (path - payload label mismatch) defect condition this read/write bit-field is used to configure the receiv e sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator vi a the downstream traffic (e.g., towards eac h of the 28 egress direction transmit ds1/e1 framer blocks), anytime (and for the duration th at) it declares the pl m-p defect condition. ` 0 - does not configure the receive sts-1 poh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) whenever it declares the plm-p defect condition. ` 1 - configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the downstream traffic) whenever it dec lares the plm-p defect condition.note n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 3 - transmit path ais (downstream) upon declaration of the path trace message unstable defect condition this read/write bit-field is used to configure the receiv e sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator vi a the downstream traffic (e.g., towards eac h of the 28 egress direction transmit ds1/e1 framer blocks), anytime (and for the duration that) it declares the path trace messa ge unstable defect condition within t able 156: r eceive sts-1 p ath - auto ais c ontrol r egister (a ddress l ocation = 0 x 02bb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit ais-p (down- stream) upon c2 byte unstable transmit ais-p (down- stream) upon uneq-p transmit ais-p (down- stream) upon plm-p transmit ais-p (down- stream) upon path trace message unstable transmit ais-p (down- stream) upon tim-p transmit ais-p (down- stream) upon lop-p transmit ais-p (down- stream) enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 127 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications the incoming sts-1/sts-3 data-stream. ` 0 - does not configure the receive sts-1 poh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic) whenever it declares the path trace message unstable defect condition. ` 1 - configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the downstream traffic) whenever it declares the path trace message unstable defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 2 - transmit path ais (downstream) upon declar ation of the tim-p (path trace message identification mismatch) defect condition this read/write bit-field is used to configure the receiv e sts-1 poh processor block to automatically transmit a path ais (ais-p) indicator via the down stream traffic (e.g., towards each of the 28 egress direction transmit ds1/e1 framer blocks), anytime (and for the dur ation that) it declares the tim-p defe ct condition within the incoming sts- 1/sts-3 data-stream. ` 0 - does not configure the receive sts-1 poh processor bl ock to transmit the ais-p indicator (via the downstream traffic) whenever it declares the tim-p defect condition. ` 1 - configures the receive sts-1 poh processor block to tr ansmit the ais-p indicator (via the downstream traffic) whenever it declares the tim-p defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 1 - transmit path ais (downstr eam) upon detection of loss of pointer (lop-p) defect condition this read/write bit-field is used to configure the receiv e sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator via the down stream traffic (e.g., towards each of the 28 egress direction transmit ds1/e1 framer blocks), anytime (and for the dur ation that) it declares the lop-p defect condition within th e incoming sts- 1/sts-3 data-stream. ` 0 - does not configure the receive sts-1 poh processor blo ck to automatically transmit the ais-p indicator (via the downstream traffic, towards the corresponding transmit sone t poh processor block) whenever it declares the lop- p defect condition. ` 1 - configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the downstream traffic, towards the corresponding transmit sone t poh processor block) whenever it declares the lop- p defect condition. n ote : the user must also set bit 0 (transmit ais-p enable ) to 1 to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. bit 0 - automatic transmission of ais-p enable this read/write bit-field serves two purposes. ? it is used to configure the receiv e sts-1 poh processor block to autom atically transmit the path ais indicator, via the down-stream traffic (e.g., towards eac h of the 28 egress direction transmit ds1/e1 framer blocks), upon detection of an uneq- p, plm-p, lop-p or los conditions. ? it also is used to configure the re ceive sts-1 poh processor block to aut omatically transmit a path (ais-p) indicator via the downstream traffic (e.g., towards each of the 28 egress direction transmit ds1/e1 framer blocks) anytime it detects an ais-p conditio n in the incoming sts-1/sts-3 data-stream. ` 0 - configures the receive sts-1 poh processor block to not automatically tr ansmit the ais-p indicator (via the downstream traffic, towards each of the 28 egress direction transmit ds1/e1 framer blocks) whenever it declares any of the above-mentioned defect conditions. ` 1 - configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the downstream traffic, towards each of the 28 egress direction transmit ds1/e1 framer blocks) whenever it declares any of the above-mentioned defect condition. n ote : the user must also set the corresponding bit-fields (withi n this register) to 1 in order to configure the receive sts-1 poh processor block to automatically transmi t the ais-p indicator upon detection of a given alarm/defect condition.
XRT86SH328 preliminary 128 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - unused bit 6 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the lop-p defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit t he ds1/e1 ais indicator via the downstream ds1/ e1 signal, anytime (and for the duration that) the receive sts-1 poh processor block declares the lop-p defect condition. ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signal, anytime the receive sts-1 poh processor block declares the lop-p defect. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signal, anytime ( and for the duration that) the receive sts-1 poh processor block declares the lop-p defect. bit 5 - transmit ds1/e1 ais (via downstream t1/e1s) up on declaration of the plm-p defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit t he ds1/e1 ais indicator via the downstream ds1/ e1 signal, anytime (and for the duration that) the receive sts-1 poh processor block declares the plm-p defect condition. ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime the receive sts-1 poh processor block declares the plm-p defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/ e1 signals, anytime (and for the duration that) the receive sts-1 poh processor block declares the plm-p defect condition. bit 4 - unused bit 3 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the uneq-p defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit the ds1/ e1 ais indicator via the downstream ds1/e1 si gnals, anytime (and for the duration that) the receive sts-1 poh processor block declares the uneq-p defect condition. ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime the receive sts-1 poh processor block declares the uneq-p defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/ e1 signals, anytime (and for the duration that) the receive sts-1 poh processor block declares the uneq-p defect condition. bit 2 - transmit ds1/e1 ais (via downstream t1/e1s) upon declaration of the tim-p defect condition this read/write bit-field is used to configure each of the 28 egress direct ion transmit ds1/e1 framer blocks to automatically transmit the ds1/ e1 ais indicator via the downstream ds1/e1 si gnals, anytime (and for the duration that) the receive sts-1 poh processor blo ck declares the tim-p defect condition. ` 0 - does not configure all 28 of the egress direction transm it ds1/e1 framer blocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signals, anytime the receive sts-1 poh processor block declares t able 157: r eceive sts-1 p ath - sonet r eceive a uto a larm r egister - b yte 0 (a ddress l ocation = 0 x 02c3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit ais (via downstream t1/e1s) upon lop-p transmit ais (via down - stream t1/e1s) uponplm-p unused transmit ais (via down - stream t1/e1s) upon uneq- p transmit ais (via down - stream t1/e1s) upon tim-p transmit ais (via down - stream t1/e1s) upon ais-p unused r/w r/w r/w r/o r/w r/w r/w r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 129 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications the tim-p defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer bl ocks to automatically transmit the ds1/e1 ais indicator via the downstream ds1/ e1 signals, anytime (and for the duration that) the receive sts-1 poh processor block declares the tim-p defect condition. bit 1 - transmit ds1/e1 ais (via downstream t1/e1s) upon ais-p this read/write bit-field is used to configure each of t he 28 egress direction transmit ds1/e1 framer blocks to automatically transmit the ds1/ e1 ais indicator via the downstream ds1/e1 si gnals, anytime (and for the duration that) the receive sts-1 poh processor block declares the ais-p defect condition. ` 0 - does not configure all 28 of the egress direction transmit ds1/e1 framer blocks to autom atically transmit the ds1/e1 ais indicator via the downstream ds1/e1 signal, anytime the receive sts-1 poh processor block declares the ais-p defect condition. ` 1 - configures all 28 of the egress direction transmit ds1/e1 framer blocks to automatically transmit the ais-p indicator via the downstream ds1/e1 signals, anytime (and for the duration that) the receive sts-1 poh processor block declares the ais-p defect condition. bit 0 - unused bit [7:0] - receive negative pointer adjustment count - msb these reset-upon-read bits, al ong with that in receive sts-1 path - receive ne gative pointer adjustment count register - byte 0 present a 16-bit repr esentation of the number of negative (or decrementing ) pointer adjustments that the receive sts-1 poh processor block has detect ed since the last read of these registers. n ote : this register contains the msb (most significant bits) of this 16-bit expression. bit [7:0] - receive negative poin ter adjustment count - lsb these reset-upon-read bits, al ong with that in receive sts-1 path - receive ne gative pointer adjustment count register - byte 1 present a 16-bit repr esentation of the number of negative (or decrementing ) pointer adjustments that the receive sts-1 poh processor block has detect ed since the last read of these registers. n ote : this register contains the lsb (least significant bits) of this 16-bit expression. t able 158: r eceive sts-1 p ath - r eceive n egative p ointer a djustment c ount r egister - b yte 1 (a ddress = 0 x 02c4) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive negative pointer adjustment count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 159: r eceive sts-1 p ath - r eceive n egative p ointer a djustment c ount r egister - b yte 0 (a ddress = 0 x 02c5) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive negative pointe r adjustment count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 130 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - receive positive poin ter adjustment count - msb these reset-upon-read bits, al ong with that in receive sts-1 path - receive po sitive pointer ad justment count register - byte 0 present a 16-bit representation of the nu mber of positive (or increment ing) pointer adjustments that the receive sts-1 poh processor block has detect ed since the last read of these registers. n ote : this register contains the msb (most significant bits) of this 16-bit expression. bit [7:0] - receive positive poin ter adjustment count - lsb these reset-upon-read bits, al ong with that in receive sts-1 path - receive po sitive pointer ad justment count register - byte 1 present a 16-bit representation of the nu mber of positive (or increment ing) pointer adjustments that the receive sts-1 poh processor block has detect ed since the last read of these registers. n ote : this register contains the lsb (least significant bits) of this 16-bit expression. bit [7:0] - j1 byte captured value[7:0] these read-only bit-fields contain the value of the j1 byte , within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new j1 byte value. bit [7:0] - b3 byte captured value[7:0] these read-only bit-fields contain the va lue of the b3 byte, within the most recently received sts-1/sts-3 frame. t able 160: r eceive sts-1 p ath - r eceive p ositive p ointer a djustment c ount r egister - b yte 1 (a ddress = 0 x 02c6) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive positive pointer adjustment count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 161: r eceive sts-1 p ath - r eceive p ositive p ointer a djustment c ount r egister - b yte 0 (a ddress = 0 x 02c7) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive positive pointe r adjustment count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 162: r eceive sts-1 p ath - r eceive j1 b yte c apture r egister (a ddress l ocation = 0 x 02d3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 j1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 163: r eceive sts-1 p ath - r eceive b3 b yte c apture r egister (a ddress l ocation = 0 x 02d7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 131 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new b3 byte value. bit [7:0] - c2 byte captured value[7:0] these read-only bit-fields contain the value of the c2 byte , within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new c2 byte value. bit [7:0] - g1 byte captured value[7:0] these read-only bit-fields contain the value of the g1 byte , within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new g1 byte value. bit [7:0] - f2 byte captured value[7:0] these read-only bit-fields contain the value of the f2 byte, within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new f2 byte value. bit [7:0] - h4 byte captured value[7:0] these read-only bit-fields contain the value of the h4 byte , within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new h4 byte value. t able 164: r eceive sts-1 p ath - r eceive c2 b yte c apture r egister (a ddress l ocation = 0 x 02db) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 165: r eceive sts-1 p ath - r eceive g1 b yte c apture r egister (a ddress l ocation = 0 x 02df) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 166: r eceive sts-1 p ath - r eceive f2 b yte c apture r egister (a ddress l ocation =0 x 02e3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 167: r eceive sts-1 p ath - r eceive h4 b yte c apture r egister (a ddress l ocation = 0 x 02e7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h4_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 132 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - z3 byte captured value[7:0] these read-only bit-fields contain the value of the z3 by te, within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new z3 byte value. bit [7:0] - z4 (k3) byte captured value[7:0] these read-only bit-fields contain the value of the z4 (k3) byte, within the most re cently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame period. during the next sts-1/sts-3 frame period, this value will be overridden with a new z4 (k3) byte value. bit [7:0] - z5 byte captured value[7:0] these read-only bit-fields contain the value of the z5 by te, within the most recently received sts-1/sts-3 frame. this particular value is stored in this register for one sts-1/sts-3 frame peri od. during the next sts-1/sts-3 frame period, this value will be overridden with a new z5 byte value. t able 168: r eceive sts-1 p ath - r eceive z3 b yte c apture r egister (a ddress l ocation = 0 x 02eb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 169: r eceive sts-1 p ath - r eceive z4 (k3) b yte c apture r egister (a ddress l ocation = 0 x 02ef) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z4(k3)_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 170: r eceive sts-1 p ath - r eceive z5 b yte c apture r egister (a ddress l ocation = 0 x 02f3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z5_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 133 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 2.5 receive tug-3 mapper/vc-4 poh pr ocessor block regi sters (sdh/tug-3 applications only) the register map for the receive tu-3 mapper/vc-4 poh processor block is presented and discussed in detail within the "sdh version of the register map". in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328 device, with the receiv e tug-3 maper/vc-4 poh processor block "highlighted" is presented below in figure 5 . for detailed on the "receive tug-3 mapper/vc-4 po h processor block" regi sters, please see the "XRT86SH328 28-channel ds1/e1 framer/liu wit h ds3 mux and tu-mapper ic - register map & description - sdh applications" 2.6 transmit sts-1/sts-3 toh processor block registers the register map for the transmit sts-1/sts-3 toh processor block is presented in the table below. additionally, a detailed description of each of the tr ansmit sts-1/sts-3 toh processor block registers is presented below. in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328, with the transmit sts-1/sts-3 toh processor block highlighted is presented below in figure 6 . f igure 5. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the r eceive tug-3 m apper /vc-4 poh p rocessor block " highlighted " sts-1/ stm-0 telecom bus interface sts-1/ stm-0 telecom bus interface transmit stm-1 soh processor block transmit stm-1 soh processor block receive stm-1 soh processor block receive stm-1 soh processor block transmit vc-3 poh processor block transmit vc-3 poh processor block receive vc-3 poh processor block receive vc-3 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from tu channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to tu channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 receive tug-3 mapper/ vc-4 poh processor block receive tug-3 mapper/ vc-4 poh processor block transmit tug-3 mapper/ vc-4 poh processor block transmit tug-3 mapper/ vc-4 poh processor block
XRT86SH328 preliminary 134 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:4] - unused bit [3:0] - control_pointer[3:0] f igure 6. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the t ransmit sts- 1/sts-3 toh p rocessor b lock highlighted t able 171: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 3 (a ddress l ocation = 0 x 0700) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused control_pointer[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
preliminary XRT86SH328 135 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:3] - unused bit 2 - auto transmit ais-l enable bit 1 - section dcc relocate bit 0 - line dcc relocate bit [7:6] - unused bit 5 - e2 byte insert method this read/write bit-field is used to specify the source of the contents of the e2 byte, within the transmit output sts- 1/sts-3 or sts-3 data stream. 0 - e2 byte is obtained fr om txtoh serial input port.] 1 - e2 byte is obtained from the cont ents within the transmit transport - e2 byte value register (address location = 0x0747). this selection provides the user with soft ware control over the value of the outbound e2 byte. bit 4 - e1 byte insert method this read/write bit-field is used to specify the source of the contents of the e1 byte, within the transmit output sts- 1 or sts-3 data stream. 0 - e1 byte is obtained fr om txtoh serial input port. 1 - e1 byte is obtained from the cont ents within the transmit transport - e1 byte value register (address location= 0x0743). this selection provides the user with soft ware control over the value of the outbound e1 byte. bit 3 - f1 byte insert method this read/write bit-field is used to sp ecify the source of the contents of th e f1 byte, within the transmit output sts- 1 or sts-3 data stream. 0 - f1 byte is obtained from txtoh serial input port. 1 - f1 byte is obtained from the contents within the tran smit transport - f1 byte value register (address location= 0x073f). this selection provides the user with softw are control over the value of the outbound f1 byte. bit 2 - s1 byte insert method this read/write bit-field is used to specify the source of the contents of the s1 byte, within the transmit output sts- 1 or sts-3 data stream. 0 - s1 byte is obtained fr om txtoh serial input port. 1 - s1 byte is obtained from the cont ents within the transmit transport - s1 byte value register (address location= 0x073b). this selection provides the user with soft ware control over the value of the outbound s1 byte. t able 172: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 2 (a ddress l ocation = 0 x 0701) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused auto trans - mit ais-l enable section dcc relocate line dcc relocate r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 173: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0702) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved e2 insert - method e1 insert method f1 insert method s1 insert method k1k2 insert method m0m1 insert method[1] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 136 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 1 - k1k2 by te insert method this read/write bit-field is used to specify the source of the contents of the k1 and k2 bytes, within the transmit output sts-1 or sts-3 data stream. 0 - k1 and k2 bytes are obtained from txtoh serial input port. 1 - k1 and k2 bytes are obtained from the contents within th e transmit transport - k1k2 byte value register - byte 1 (address location= 0x072e) and the transmit transport - k1 k2 byte value register - byte 2 (address location= 0x072f). this selection provides the user with software control over the va lue of the outbound k1 and k2 bytes. bit 0 - m0m1 insert method this read/write bit-field, along with m0m1 insert meth od[0] (located in the transmit transport - sonet control register - byte 0) are used to specify the source of the contents of the m0/m1 byte, within the tr ansmit output sts-1 or sts-3 data stream. the relationship between these two bit- fields and the corresponding source of the m0/m1 byte is presented below. bit 7 - m0m1 insert method this read/write bit-field, along with m0m1 byte insert method[1] (located in the transmit sts-1/sts-3 transport - sonet control register - byte 1) are us ed to specify the source of the contents of the m0/m 1 byte, within the transmit output sts-1 or sts-3 data stream. the relationship between these two bit-fields and the corresponding source of the m0/m1 byte is presented below. source of m)/m1 byte m0m1 i nsert m ethod [1:0] s ource of m0/m1 b yte 0 0 from the receive sts-1/sts-3 toh processo r block (b2 byte (or bip-24) error count) 0 1 obtained from the contents of the transmit sts-1/sts-3 transpor t - m0/m1 byte value register (address location= 0x0737). 1 0 m0/m1 byte is obtained from the txtoh serial input port. 1 1 from the receiver sts-1/sts-3 toh processo r block (b2 byte (or bip-24) error count). t able 174: t ransmit sts-1/sts-3 t ransport - t ransmit c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0703) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m0m1 insert method[0] unused rdi-l force ais-l force losforce scramble enable b2 error insert a1a2 error insert r/w r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 source of m0/m1 byte m0m1 b yte i nsert m ethod [1:0] s ource of m0/m1 b yte 0 0 from the receive sts-1/sts-3 toh pr ocessor block (b2 byte error count) 0 1 obtained from the contents of the transmit st s-1/sts-3 transport - m0/m1 byte value reg - ister (address location= 0x0737). 1 0 m0/m1 byte is obtained from the txtoh serial input port. 1 1 from the receive sts-1/sts-3 toh proc essor block (b2 byte error count).
preliminary XRT86SH328 137 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit6 - unused bit 5 - transmit line - remote defect indicator this read/write bit-field is used to (by software contro l) force the transmit sts-1/sts-3 toh processor block to generate and transmit the rdi-l indicator to the remote terminal equipment. ` 0 - does not configure the transmit sts-1/sts-3 toh processor block to generate and transmit the rdi-l indicator. ` 1 - configures the transmit sts-1/st s-3 toh processor block to generate and transmit the rdi-l indicator. in this case, the transmit sts-1/sts-3 toh processor block wi ll force bits 6, 7 and 8 (of the k2 byte) to the value 1, 1, 0. n ote : this bit-field is ignored if the transmit sts-1/sts-3 to h processor block is currently transmitting the line ais (ais-l) indicator or los pattern. bit 4 - transmit line - ais indicator this read/write bit-field is used to (by software contro l) force the transmit sts-1/sts-3 toh processor block to generate and transmit the ais-l indicator to the remote terminal equipment. ` 0 - does not configure the transmit sts-1/sts-3 toh proc essor block to generate and transmit the ais-l indicator. ` 1 - configures the transmit sts-1/st s-3 toh processor block to generate and transmit the ais-l indicator. in this case, the transmit sts-1/sts-3 toh processor bl ock will force all bits (within the outbound sts-1 or sts-3 frame) with the exception of the sectio n overhead bytes to an all ones pattern. n ote : this bit-field is ignored if the transmit sts-1/sts- 3 toh processor block is transmitting the los pattern. bit 3 - transmit los pattern this read/write bit-field is used to (by software contro l) force the transmit sts-1/sts-3 toh processor block to transmit the los (loss of signal) pattern to the remote terminal equipment. ` 0 - does not configure the transmit sts-1/sts-3 toh processor block to ge nerate and transmit the los pattern. ` 1 - configures the transmit sts-1/st s-3 toh processor block to transmit th e los pattern. in this case, the transmit sts-1/sts-3 toh processor bl ock will force all bytes (within the out bound sonet frame) to an all zeros pattern. bit 2 - scramble enable this read/write bit-field is used to either enable or disable the scrambler, within the transmit sts-1/sts-3 toh processor block circuitry. ` 0 - disables the scrambler. ` 1 - enables the scrambler. bit 1 - transmit b2 byte error insert enable this read/write bit-field is used to configure the transmi t sts-1/sts-3 toh processor block to insert errors into the outbound b2 bytes, per the contents within the transmi t sts-1/sts-3 transport - transmit b2 byte error mask register. ` 0 - configures the transmit sts-1/sts- 3 toh processor block to not insert errors into the b2 bytes, within the outbound sts-1 or sts-3 signal. ` 1 - configures the transmit sts-1/sts-3 toh processor block to insert into the b2 bytes (per the contents within the transmit b2 byte error mask register). bit 0 - transmit a1a2 byte error insert enable this read/write bit-field is used to configure the transmi t sts-1/sts-3 toh processor block to insert errors into the outbound a1 and a2 bytes, within the outbound sts-1 or sts-3 data-stream. ` 0 - configures the transmit sts-1/sts-3 toh processor block to not insert errors into the a1 and a2 bytes, within the outbound sts-1 or sts-3 data-stream. ` 1 - configures the transmit sts-1/sts-3 toh processor block to insert errors into the a1 and a2 bytes, within the outbound sts-1 or sts-3 data-stream.
XRT86SH328 preliminary 138 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:1] - unused bit 0 - transmit erred a1 byte enable this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 toh proce ssor block to transmit a continuous stream of sts-1 or sts-3 fr ames, in which the a1 byte is erred. ` 0 - configures the transmit sts-1/sts-3 toh processor bl ock to not transmit sts-1 or sts-3 frames with erred a1 bytes. ` 1 - configures the transmit sts-1/st s-3 toh processor block to transmit st s-1 or sts-3 frames with erred a1 bytes. bit [7:1] - unused bit 0 - transmit erred a2 byte enable this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 toh proce ssor block to transmit a continuous stream of sts-1 or sts-3 fr ames, in which the a2 byte is erred. ` 0 - configures the transmit sts-1/sts-3 toh processor bl ock to not transmit sts-1 or sts-3 frames with erred a2 bytes. ` 1 - configures the transmit sts-1/st s-3 toh processor block to transmit st s-1 or sts-3 frames with erred a2 bytes. bit [7:0]b1 byte error mask[7:0] these read/write bit-fields are used to insert bit errors into the b1 bytes, within the outbound sts-1 or sts-3 data stream. the transmit sts-1/sts-3 toh processor block will perform an xor operation wit h the contents of the b1 byte, and this register. the results of this calculation will be inserted into the b1 byte position within the outbound sts- 1 or sts-3 data stream. for each bit-field (within this regist er) that is set to 1, the corresponding bit, within the b1 byte will be in error. t able 175: t ransmit sts-1/sts-3 t ransport - t ransmit a1 b yte e rror r egister (a ddress l ocation = 0 x 0717) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit erred a1byte enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 176: t ransmit sts-1/sts-3 t ransport - t ransmit a2 b yte e rror r egister (a ddress l ocation = 0 x 071f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit erred a2 byte enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 177: t ransmit sts-1/sts-3 t ransport - t ransmit b1 b yte e rror m ask r egister (a ddress l ocation = 0 x 0723) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1_byte_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 139 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : for normal operation, the user should set this register to 0x00. bit [7:1] - unused] bit 0 - transmit b2 byte error enable this read/write bit-field is used to configure the trans mit sts-1/sts-3 toh processo r block to perform the xor operation with the content s of the transmit sts-1/sts-3 transport -tr ansmit b2 bit error mask register (address location = 0x072b) ` 0 - disables the xor operation. in this case, the transmi t sts-1/sts-3 toh processor block will not perform the xor operation with the transmit sts- 1/sts-3 transport - transmit b2 bit error mask register. as a consequence, the transmit sts-1/sts-3 toh processor block will transmit a continuous stream of sts-1s with no b2 byte errors. ` 1 - enables the xor operation. in this setting, the transmit sts-1/sts-3 toh pr ocessor will perform the xor operation of the value of the b2 byte (within the outbound sts-1 or sts-3 frame) with t he contents within the transmit sts-1/sts-3 transport - transmi t b2 bit error mask register. bit [7:0] - transmit b2 error mask-byte these read/write bit-fields are used to insert b2 byte errors into the outbound sts-1 or sts-3 data-stream, for diagnostic purposes. if bit 0 (transmit b2 error enable) wit hin the transmit sts-1/sts-3 transport - transmit b2 byte error register (address location = 0xn927) is set to 1, then transmit sts-1/ sts-3 toh processor block will be configured to perform an xor operation between the contents of this register, with the contents of the outbound b2 byte. the results of this calculation is written back into the b2 byte position, within the outbound sts-1 or sts-3 data. hence, for every bit (within this register) that is set to 1, the corre sponding bit (within the outbound b2 byte) will be erred. n otes : 1. 1. for normal (e.g., un-erred) operat ion, the user should ensure that this register is set to the value 0x00. 2. these register bits are ignored unless bit 0 (trans mit b2 error enable), withi n the transmit sts-1/sts- 3 transport - transmit b2 byte error register has been set to 1. t able 178: t ransmit sts-1/sts-3 t ransport - t ransmit b2 b yte e rror m ask r egister (a ddress l ocation = 0 x 0727) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit b2 error enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 179: t ransmit sts-1/sts-3 t ransport - t ransmit b2 b it e rror m ask r egister (a ddress l ocation = 0 x 072b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_b2_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 140 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - transmit k2 byte value if the appropriate k1k2 insert method is selected, then these read/write bit-fields will are used to specify the contents of the k2 byte, within the outbound sts-1/sts-3 signal. n ote : if bit 1 (k1k2 insert method) within the transmit sts- 1/sts-3 transport - sonet transmit control register - byte 1 (address location= 0x0702) is set to 1, then the transmit sts-1/sts-3 toh processor block will load the contents of this register into t he k2 byte-field, within each outbound st s-1 or sts-3 frame. these register bits are ignored if bit 1 (k1k2 insert method) is set to 0. bit [7:0] - transmit k1 byte value if the appropriate k1k2 insert method is selected, then these read/write bit-fields will are used to specify the contents of the k1 byte, within the outbound sts-1/sts-3 signal. n ote : if bit 1 (k1k2 insert method) within the transmit sts- 1/sts-3 transport - sonet transmit control register - byte 1 (address location= 0x0702) is set to 1, then the transmit sts-1/sts-3 toh processor block will load the contents of this register into t he k1 byte-field, within each outbound st s-1 or sts-3 frame. these register bits are ignored if bit 1 (k1k2 insert method) is set to 0. bit [7:4] - unused bit 3 - external transmit line remo te defect indica tor (rdi-l) enable this read/write bit-field is used to ex ternally insert the value for bits 6, 7 and 8 (of the k2 byte) into the outbound sts-1 or sts-3 data stream. if the user enables this featur e, then the user can enable or disable the insertion of the rdi-l indicator, via the txpoh_n input pin. 0 - disables this feature. 1 - enables this feature. bit 2 - transmit line remote defect in dicator (rdi-l) upon detection of ais-l t able 180: t ransmit sts-1/sts-3 t ransport - k2 b yte v alue r egister - b yte 1 (a ddress l ocation = 0 x 072e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_k2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 181: t ransmit sts-1/sts-3 t ransport - k1 b yte v alue r egister - b yte 1 (a ddress l ocation = 0 x 072f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_k1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 182: t ransmit sts-1/sts-3 t ransport - rdi-l c ontrol r egister (a ddress l ocation = 0 x 0733) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused external rdi-l enable transmit rdi-l upon ais transmit rdi-l upon lof transmit rdi-l upon los r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 141 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 toh processor block to automatically transmit a rdi-l indicator to the remo te terminal anytime (and for the durat ion) that the receive sts-1/sts-3 toh processor block is detecting a line ais (ais-l) indicator. ` 0 - configures the transmit sts-1/sts- 3 toh processor block to not automati cally transmit the rdi-l indicator, upon the receive sts-1/sts-3 toh proces sor block detecting the ais-l indicator. ` 1 - configures the transmit sts-1/sts- 3 toh processor block to automatically transmit the rdi-l indicator, upon the receive sts-1/sts-3 toh processor block detecting the ais-l indicator. bit 1 - transmit line remote defect indicator (rdi-l) upon detection of lof this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 toh processor block to automatically transmit a rdi-l indicator to the remo te terminal anytime (and for the durat ion) that the receive sts-1/sts-3 toh processor block is declaring the lof defect ` .0 - configures the transmit sts-1/sts-3 toh processor block to not automatically tr ansmit the rdi-l indicator, whenever the receive sts-1/sts-3 toh processor block declares the lof defect. ` 1 - configures the transmit sts-1/st s-3 toh processor block to automatically transmit the rdi-l indicator, whenever the receive sts-1/sts-3 toh processor block declares the lof defect. bit 0 - transmit line remote defect indicator (rdi-l) upon detection of los this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 toh processor block to automatically transmit a rdi-l indicator to the remo te terminal anytime (and for the durat ion) that the receive sts-1/sts-3 toh processor block is declaring the los defect. ` 0 - configures the transmit sts-1/sts- 3 toh processor block to not automati cally transmit the rdi-l indicator, whenever the receive sts-1/sts-3 toh processor block declares the los defect. ` 1 - configures the transmit sts-1/st s-3 toh processor block to automatically transmit the rdi-l indicator, whenever the receive sts-1/sts-3 toh processor block declares the los defect. bit [7:0] - transmit m0m1 byte value if the appropriate m0m1 insert method is selected, then these read/write bit-fields will are used to specify the contents of the m0m1 byte, with in the outbound sts-1/sts-3 signal. n ote : if bit 0 (m0m1 insert method - bit 1) within the tr ansmit sts-1/sts-3 transport - sonet transmit control register - byte 1 (address location= 0x0702) and bit7 (m0 m1 byte insert method - bit 0) within the transmit sts-1/sts-3 transport - sonet transmit control register - byte 0 (address location= 0x0703) are set to 0, 1, then the sts-1/sts-3 transmit block will load the contents of this register into the m0m1 byte-field, within each outbound sts-1 or sts-3 frame. th ese register bits are ignored if th e m0m1 insert method[1:0] bits are set to any value other than 0, 1. bit [7:0] - transmit s1 byte value if the appropriate s1 insert method is selected, then these read/write bit-fields will are used to specify the contents of the s1 byte, within the outbound sts-1/sts-3 signal. if bit 2 (s1 insert method) withi n the transmit sts-1/sts-3 t able 183: t ransmit sts-1/sts-3 t ransport - m0m1 b yte v alue r egister (a ddress l ocation = 0 x 0737) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_m0m1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 184: t ransmit sts-1/sts-3 t ransport - s1 b yte v alue r egister (a ddress l ocation = 0 x 073b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_s1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 142 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 transport - sonet transmit control register - byte 1 (add ress location= 0x0702) is set to 1, then the sts-1/sts-3 transmit block will load the contents of this register into th e s1 byte-field, within each outbound sts-1 or sts-3 frame. n ote : these register bits are ignored if bi t 2 (s1 insert method) is set to 0. bit [7:0] - transmit f1 byte value if the appropriate f1 byte insert method is selected, then these read/write bit-fields will are used to specify the contents of the f1 by te, within the outbound sts-1/sts-3 signal. n ote : if bit 3 (f1 byte insert method) wit hin the transmit sts-1/sts-3 transport - sonet transmit control register - byte 1 (address location= 0x0702) is set to 1, th en the transmit sts-1/sts-3 toh processor block will load the contents of this register into the f1 byte-field, within each outbound sts-1 or st s-3 frame. these register bits are ignored if bit 3 (f1 insert method) is set to 0. bit [7:0] - transmit e1 byte value if the appropriate e1 byte insert method is selected, then these read/write bi t-fields will are used to specify the contents of the e1 byte, within the outbound sts-1/sts-3 signal. note n ote : if bit 4 (e1 insert method) within t he transmit sts-1/sts-3 transport - sonet transmit control register - byte 1 (address location= 0x0702) is set to 1, then the transmit sts-1/sts-3 toh processor block will load the contents of this register into t he e1 byte-field, within each outbound st s-1 or sts-3 frame. these register bits are ignored if bit 4 (e1 insert method) is set to 0. bit [7:0] - transmit e2 byte value if the appropriate e2 byte insert method is selected, then these read/write bi t-fields will are used to specify the contents of the e2 byte, within the outbound sts-1/sts-3 signal. n ote : if bit 5 (e2 insert method) within t he transmit sts-1/sts-3 transport - sonet transmit control register - byte 1 (address location= 0x0702) is set to 1, then the transmit sts-1/sts-3 toh processor block will load the contents of this register into t he e2 byte-field, within each outbound st s-1 or sts-3 frame. these register bits are ignored if bit 5 (e2 insert method) is set to 0. t able 185: t ransmit sts-1/sts-3 t ransport - f1 b yte v alue r egister (a ddress l ocation = 0 x 073f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_f1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 186: t ransmit sts-1/sts-3 t ransport - e1 b yte v alue r egister (a ddress l ocation = 0 x 0743) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_e1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 187: t ransmit sts-1/sts-3 t ransport - e2 b yte v alue r egister (a ddress l ocation = 0 x 0747) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_e2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 143 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - transmit j0 byte value these read/write bits are used to specify the value of the j0 byte, that will be transmitted via the transport overhead, within the very next sts-1 or sts-3 frame. this register is only valid if the transmit sts-1/sts-3 toh processor block is configured to read out th e contents from this register and insert it into the j0 byte -field within each outbound sts-1 or sts-3 frame. the us er accomplishes this by setting bits 1 and 0 (j0_type), within the transmit sts-1/sts-3 transport - j0 byte control re gister (address location= 0x074f) to 1, 0. bit [7:4] - unused bit [3:2] - message length[1:0] these two read/write bit-fields are used to specify the leng th of the message that is to be repetitively transmitted via the j0 byte as shown in the table below. j bit [1:0] - transmit j0 source[1:0] these two read/write bit-fields are used to specify the source of the message that will be transported via the j0 byte/message, within the outbound sts-1 or st s-3 data-stream, as shown in the table below t able 188: t ransmit sts-1/sts-3 t ransport - j0 b yte v alue r egister (a ddress l ocation = 0 x 074b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_j0_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 189: t ransmit sts-1/sts-3 t ransport - t ransmitter j0 b yte c ontrol r egister (a ddress l ocation = 0 x 074f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused message length[1:0] j0_type[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 message length msg_length[1:0] c orresponding m essage l ength (b ytes ) 00 1 byte 01 16 bytes 10 or 11 64 bytes source of j0 byte message 0_type[1:0] c orresponding s ource of j0 b yte /m essage . 00 automatically set the j0 byte, in each outbound sts-1 or sts-3 frame to 0x01. 01 the transmit section tracemessage buffert he transmit sts-1/sts-3 section trace buffer memory is located at address locations 0x0900 through 0x093f.
XRT86SH328 preliminary 144 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 10 from the transmit j0 byte value[7:0] register. in this setting, the transmit sts-1/sts-3 toh processor block will read out the contents of the transmit j0 va lue[7:0] register (address location= 0x074b), and will insert this value into the j0 byte of each outbound sts- 1 or sts-3 frame. 11 from the txpoh_n input pin. source of j0 byte message 0_type[1:0] c orresponding s ource of j0 b yte /m essage .
preliminary XRT86SH328 145 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 2.7 transmit sts-1/sts-3 poh processor block registers the register map for the transmit sts-1/sts-3 poh processor block is presented in the table below. additionally, a detailed description of each of the tran smit sts-1/sts-3 poh proc essor block registers is presented below. in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328, with the transmit sts- 1/sts-3 poh processor block highlighted is presented below in figure 7 . bit [7:2] - unused bit [1:0] - payload_type[1:0] f igure 7. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the t ransmit sts- 1/sts-3 poh p rocessor b lock highlighted t able 190: t ransmit sts-1/sts-3 p ath - t ransmit c ontrol r egister - b yte 2 (a ddress l ocation = 0 x 0781) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused payload_type[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
XRT86SH328 preliminary 146 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:4] - unused bit 3 - z5 insertion type this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processor block to use either the transmit sts-1/sts-3 path - transmit z5 value register or the tpoh input pin as the source for the z5 byte, in the outbound sts-1/sts-3 spe. ` 0 - configures the transmit sts-1/st s-3 poh processor block to use the transmit sts-1/sts-3 path - transmit z5 value register (address location= 0x07b3). ` 1 - configures the transmit sts-1/sts-3 poh processor block to use the tpoh input as the source for the z5 byte, in the outbound sts-1/sts-3 spe. bit 2 - z4 insertion type this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processor block to use either the transmit sts-1/sts-3 path - transmit z4 value register or the tpoh input pin as the source for the z4 byte, in the outbound sts-1/sts-3 spe. ` 0 - configures the transmit sts-1/st s-3 poh processor block to use the transmit sts-1/sts-3 path - transmit z4 value register (address location= 0x07af). ` 1 - configures the transmit sts-1/sts-3 poh processor block to use the tpoh input as the source for the z4 byte, in the outbound sts-1/sts-3 spe. bit 1 - z3 insertion type this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processor block to use either the transmit sts-1/sts-3 path - transmit z3 value register or the tpoh input pin as the source for the z3 byte, in the outbound sts-1/sts-3 spe. ` 0 - configures the transmit sts-1/st s-3 poh processor block to use the transmit sts-1/sts-3 path - transmit z3 value register (address location = 0x07ab). ` 1 - configures the transmit sts-1/sts-3 poh processor block to use the tpoh input as the source for the z3 byte, in the outbound sts-1/sts-3 spe. bit 0 - h4 insertion type this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processor block to use either the transmit sts-1/sts-3 path - transmit h4 value register or the tpoh input pin as the source for the h4 byte, in the outbound sts-1/sts-3 spe. ` 0 - configures the transmit sts-1/st s-3 poh processor block to use the transmit sts-1/sts-3 path - transmit h4 value register (address location= 0x07a7). ` 1 - configures the transmit sts-1/sts- 3 poh processor block to use the tpoh input as the source for the h4 byte, in the outbound sts-1/sts-3 spe. t able 191: t ransmit sts-1/sts-3 p ath - t ransmit c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0782) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused z5 insertion - type z4 insertion - type z3 insertion - type h4 insertion type r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 147 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - f2 insertion type this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processor block to use either the transmit sts-1/sts-3 path - tr ansmit f2 value register or the tpoh input pin as the source for the f2 byte, in the outbound sts-1/sts-3 spe. ` 0 - configures the transmit sts-1/st s-3 poh processor block to use the tr ansmit sts-1/sts-3 path - transmit f2 value register (address location= 0x07a3). ` 1 - configures the transmit sts-1/sts-3 poh processor block to use the tpoh input as the source for the f2 byte, in the outbound sts-1/sts-3 spe. bit [6:5] - rei-p in sertion type[1:0] these two read/write bit-fields are us ed to configure the transmit sts-1/ sts-3 poh processor block to use one of the three following sources for the rei-p bit-fields (e.g., bits 1 through 4, within the g1 byte of the outbound sts- 1/sts-3 spe). ? from the corresponding receive sts-1/sts-3 poh processor block (e g., when it detects b3 bytes in its incoming spe data). ? from the transmit g1 byte value register (address location= 0x079f). ? from the tpoh input pin. ` 00/11 - configures the transmit sts-1/ sts-3 poh processor block to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon receive conditions as detected by the corresponding receive sts-1/sts-3 poh processor block. ` 01 - configures the transmit sts-1/sts-3 poh processor bl ock to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon the c ontents within the transmit g1 byte valu e register (address location= 0x079f). ` 10 - configures the transmit sts-1/sts-3 poh processor blo ck to use the tpoh input pin as the source of bits 1 through 4 (in the g1 byte of the outbound spe). bit [4:3] - rdi-p insertion type[1:0] these two read/write bit-fields are us ed to configure the transmit sts-1/ sts-3 poh processor block to use one of the three following sources for the rdi-p bit-fields (e.g ., bits 5 through 7, within t he g1 byte of the outbound sts- 1/sts-3 spe). ? from the receive sts-1/sts-3 poh processor block (e g., when it detects various alarm conditions within its incoming spe data). ? from the transmit g1 byte value register (address location = 0x079f). ? from the tpoh input pin. ` 00/11 - configures the transmit sts-1/ sts-3 poh processor block to set bits 5 through 7 (in the g1 byte of the outbound spe) based upon receive conditions as detected by the receive sts-1/sts-3 poh processor block. ` 01 - configures the transmit sts-1/sts-3 poh processor bl ock to set bits 5 through 7 (in the g1 byte of the outbound spe) based upon the c ontents within the tr ansmit g1 byte value register. ` 10 - configures the transmit sts-1/sts-3 poh processor blo ck to use the tpoh input pin as the source of bits 5 through 7 (in the g1 byte of the outbound spe). bit 2 - c2 insertion type this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processor block to use either the transmit sts-1/sts-3 path - tr ansmit c2 byte value register or the tpoh input pin as the source for the c2 byte, in t able 192: t ransmit sts-1/sts-3 p ath - t ransmit c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0783) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f2 insertion type rei-p insertion type[1:0] rdi-p insertion type[1:0] c2 byte insertion type c2 byte auto insert mode enable transmit ais-p enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 148 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 the outbound sts-1/sts-3 spe. ` 0 - configures the transmit sts-1/st s-3 poh processor block to use the transmit sts-1/sts-3 path - transmit c2 value register (address location= 0x079b). ` 1 - configures the transmit sts-1/sts- 3 poh processor block to use the tpoh input as the source for the c2 byte, in the outbound sts-1/sts-3 spe. bit 1 - auto-insert pd i-p indicator enable this read/write bit-field are used to configure the tr ansmit sts-1/sts-3 poh proces sor block to automatically insert the pdi-p (path - payload defect indicator) whenever the ais-p indicator is received from the receive sonet poh processor block. if this feature is enabled, then the tr ansmit sts-1/sts-3 poh processor block will automatically set the c2 byte (within the outbound spe) to 0xfc (to indicate a pdi-p condition) when ever it receives the ais-p indicator, from the receive sonet poh processor block. bit 0 - transmit ais-p enable this read/write bit-field is used to configure the trans mit sts-1/sts-3 poh processo r block to (via software control) transmit an ais-p indicator to the remote pte.if this feature is e nabled, then the transmit sts-1/sts-3 poh processor block will automa tically set the h1, h2, h3 and al l the spe bytes to an all ones pattern, prior to routing this data to the transmit sts-1/sts-3 toh processor block. ` 0 - configures the transmit sts-1/sts- 3 poh processor block to not transmit the ais-p indicator to the remote pte. ` 1 - configures the transmit sts-1/sts- 3 poh processor block to transmit t he ais-p indicator to the remote pte. bit [7:0] - transmit j1 byte value these read/write bit-fields are used to have software control over the value of the j1 byte, within each outbound sts-1/sts-3 spe. if the user configures the tr ansmit sts-1/sts-3 poh processor block to this register as the source of the j1 byte, then it will automatically write the contents of this register into the j1 byte loca tion, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the user writes a 0 into bit 2 (c2 insertion type) wit hin the transmit sts-1/sts-3 path - j1 control register register (address location= 0x0783). bit [7:0] - transmit b3 byte mask[7:0] this read/write bit-field is used to in sert errors into the b3 byte, within the outbound sts-1/sts-3 spe, prior to transmission to the transmit st s-1/sts-3 toh processor block. the transmit sts-1/sts-3 poh processor block will perform an xor operation with th e contents of this register, and the b3 byte value. the results of this operation will be writ ten back into the b3 byte of t he outbound sts-1/sts-3 spe. t able 193: t ransmit sts-1/sts-3 p ath - t ransmitter j1 b yte v alue r egister (a ddress l ocation = 0 x 0793) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_j1_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 194: t ransmit sts-1/sts-3 p ath - t ransmit b3 b yte e rror m ask r egister (a ddress l ocation = 0 x 0797) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_b3_byte_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 149 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : if the user sets a particular bit-field, within this regist er, to 1, then that correspondin g bit, within the outbound b3 byte will be in error. for normal operation, the user should set this register to 0x00. bit [7:0] - transmit c2 byte value these read/write bit-fields are used to have software co ntrol over the value of the c2 byte, within each outbound sts-1/sts-3 spe. if the user configures the transmit sts-1/ sts-3 poh processor block to this register as the source of the c2 byte, then it will automatically writ e the contents of this register into the c2 byte location, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the user writes a 0 into bit 2 (c2 byte in sertion type) within the transmit sts-1/sts- 3 path - sonet control register - byte 0 register (address location= 0x0783). bit [7:0] - transmit g1 byte value: these read/write bit-fields are used to have software co ntrol over the contents of the rdi-p and rei-p bit-fields, within each g1 byte in the outbound sts-1/sts-3 spe. n ote : if the users sets rei-p_insertion_t ype[1:0] and rdi-p_insertion_type[1 :0] bits to the value [0, 1], then contents of the rei-p and the rdi-p bit-fields (within each g1 byte of the outbound sts-1/sts-3 spe) will be dictated by the contents of this r egister. the rei-p_insert ion_type[1:0] and rdi-p_i nsertion_type[1:0] bit- fields are located in the transmit sts-1/sts-3 path - sonet control register - byte 0 register (address location= 0x0783) bit [7:0] - transmit f2 byte value these read/write bit-fields are used to have software co ntrol over the value of the f2 byte, within each outbound sts-1/sts-3 spe. if the user configures the transmit sts-1/ sts-3 poh processor block to this register as the source of the f2 byte, then it will automatically writ e the contents of this register into the f2 byte location, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the us er writes a 0 into bit7 (f2 byte inse rtion type) within the transmit sts-1/sts- 3 path - sonet control register - byte 0 register (address location= 0x0783). t able 195: t ransmit sts-1/sts-3 p ath - t ransmit c2 b yte v alue r egister (a ddress l ocation = 0 x 079b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 196: t ransmit sts-1/sts-3 p ath - t ransmit g1 b yte v alue r egister (a ddress l ocation = 0 x 079f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_g1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 197: t ransmit sts-1/sts-3 p ath - t ransmit f2 b yte v alue r egister (a ddress l ocation = 0 x 07a3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_f2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 150 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - transmit h4 byte value these read/write bit-fields are used to have software co ntrol over the value of the h4 byte, within each outbound sts-1/sts-3 spe. if the user configures the transmit sts-1/ sts-3 poh processor block to this register as the source of the h4 byte, then it will automatically writ e the contents of this register into the h4 byte location, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the user writes a 0 into bit 0 (h4 insertion type) wit hin the transmit sts-1/sts-3 path - sonet control register - byte 1 register (address location= 0x07a7). bit [7:0] - transmit z3 byte value these read/write bit-fields are used to have software co ntrol over the value of the z3 byte, within each outbound sts-1/sts-3 spe.if the user configures the transmit sts- 1/sts-3 poh processor block to this register as the source of the z3 byte, then it will autom atically write the contents of this register into the z3 byte location, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the user writes a 0 into bit 1 (z3 insertion type) wit hin the transmit sts-1/sts-3 path - sonet control register - byte 0 register (address location= 0x0782). bit [7:0] - transmit z4 byte value these read/write bit-fields are used to have software co ntrol over the value of the z4 byte, within each outbound sts-1/sts-3 spe. if the user configures the transmit sts-1/ sts-3 poh processor block to this register as the source of the z4 byte, then it will automatically writ e the contents of this register into the z4 byte location, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the user writes a 0 into bit 2 (z4 insertion type) wit hin the transmit sts-1/sts-3 path - sonet control register - byte 0 register (address location= 0x0782). t able 198: t ransmit sts-1/sts-3 p ath - t ransmit h4 b yte v alue r egister (a ddress l ocation = 0 x 07a7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_h4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 199: t ransmit sts-1/sts-3 p ath - t ransmit z3 b yte v alue r egister (a ddress l ocation = 0 x 07ab) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_z3_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 200: t ransmit sts-1/sts-3 p ath - t ransmit z4 b yte v alue r egister (a ddress l ocation = 0 x n9af) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_z4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 151 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - transmit z5 byte value these read/write bit-fields are used to have software co ntrol over the value of the z5 byte, within each outbound sts-1/sts-3 spe. if the user configures the transmit sts-1/ sts-3 poh processor block to this register as the source of the z5 byte, then it will automatically writ e the contents of this register into the z5 byte location, within each outbound sts-1/sts-3 spe. this feature is enabled whenever the user writes a 0 into bit 3 (z5 insertion type) wit hin the transmit sts-1/sts-3 path - sonet control register - byte 0 register (address location= 0x0782). bit [7:6] - unused bitt 5 - pointer force this read/write bit-field is used to load the values contained within the transmit st s-1/sts-3 poh arbitrary h1 pointer and transmit sts-1/st s-3 poh arbitrary h2 pointe r registers (address location= 0x07bf and 0x07c3) into the h1 and h2 bytes (within the outbound sts-1 or sts-3 data stream). the actual location of the spe will not be adjusted, per the value of h1 and h2 by tes. hence, this feature should cause the remote terminal to declare an invalid pointer condition. ` 0 - configures the transmit sts-1/st s-3 poh and toh processors to transm it sts-1 or sts-3 data with normal and correct h1 and h2 bytes. ` 1 - configures the transmit sts-1/sts- 3 poh and toh processor blocks to ov erwrite the values of the h1 and h2 bytes (in the outbound sts-1 or sts-3 data-stream) with th e values in the transmit st s-1/sts-3 poh arbitrary h1 and h2 pointer registers. bitt 4 - check stuff monitoring this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 poh and to h processor blocks to only execute a positive, negative or ndf event (via the insert po sitive stuff, insert negative stuff, insert continuous or single ndf options, via software command) if no pointer adjust ment (ndf or otherwise) has occurred during the last 3 sts-1/sts-3 frame periods. ` 0 - disables this feature.in this mode, the transmit sts-1/sts-3 poh and toh processor block will execute a software-commanded pointer adjustment event, independent of whether a pointer adjustment event has occurred in the last 3 sts-1/sts-3 frame periods. ` 1 - enables this feature.in this mo de, the transmit sts-1/st s-3 poh and toh processor block will only execute a software-commanded pointer adjustment event, if no pointer adju stment event has occurred during the last 3 sts- 1/sts-3 frame periods. bitt 3 - insert negative stuf this read/write bit-field is used to configure the transmit sts-1/sts-3 po h and toh processor blocks to insert a negative-stuff into the outbound sts-1 or sts-3 data st ream. this command, in-turn will cause a pointer t able 201: t ransmit sts-1/sts-3 p ath - t ransmit z5 b yte v alue r egister (a ddress l ocation = 0 x 07b3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_z5_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 202: t ransmit sts-1/sts-3 p ath - t ransmit p ath c ontrol r egister (a ddress l ocation = 0 x 07b7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused pointer force check stuff insert nega - tive stuff insertposi - tive stuff insertcontin - uous ndf events insertsingle ndf event r/o r/o r/w r/w w w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 152 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 decrementing event at the remote terminal. ` writing a 0 to 1 transition into this bit-field causes the following to happen. ? a negative-stuff will occur (e.g., a single payload byte will be inserted into the h3 byte position within the outbound sts-1 or sts-3 data stream). ? the d bits, within the h1 and h2 bytes will be inverted (to denote a decrementing po inter adjustment event). ? the contents of the h1 and h2 bytes will be decremented by 1, and will be used as the new pointer from this point on. n ote : once the user writes a 1 into this bi t-field, the XRT86SH328 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to 0. bitt 2 - insert positive stuff this read/write bit-field is used to configure the transmit sts-1/sts-3 po h and toh processor blocks to insert a positive-stuff into the outbound sts-1 or sts-3 data stream. this command, in-turn will cause a pointer incrementing event at the remote terminal. ` writing a 0 to 1 transition into this bit-field causes the following to happen. ? a positive-stuff will occur (e.g., a single stuff-byte wi ll be inserted into the st s-1 or sts-3 data-stream, immediately after the h3 byte position within the outbound sts-1 or sts-3 data stream). ? the i bits, within the h1 and h2 bytes will be inverted (to denote a incrementing pointer adjustment event). ? the contents of the h1 and h2 byte s will be incremented by 1, and will be us ed as the new pointer from this point on.note n ote : once the user writes a 1 into this bi t-field, the XRT86SH328 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to 0. bitt 1 - insert continuous ndf events this read/write bit-field is used configure the tr ansmit sts-1/sts-3 poh and toh processor blocks to continuously insert a new data flag (ndf) pointer adjustment into the outbound sts-1 or sts-3 data stream. as the transmit sts-1/sts-3 poh and to h processor blocks insert the ndf ev ent into the sts-1 or sts-3 data stream, it will proceed to load in the contents of the tran smit sts-1/sts-3 poh arbitrary h1 pointer and transmit sts- 1/sts-3 poh arbitrary h2 pointer registers into the h1 and h2 bytes (within the outbound sts-1 or sts-3 data stream). ` 0 - configures the transmit sts-1/st s-3 toh and poh processor blocks to not continuously insert ndf events into the outbound sts-1 or sts-3 data stream. ` 1- configures the transmit sts-1/sts-3 toh and poh proce ssor blocks to continuously insert ndf events into the outbound sts-1 or sts-3 data stream. bitt 0 - insert single ndf event this read/write bit-field is used to configure the transmit sts-1/sts-3 po h and toh processor blocks to insert a new data flag (ndf) pointer adjustment into the outbound sts-1 or sts-3 data stream. ` writing a 0 to 1 transition into this bit-field causes the following to happen ? the n bits, within the h1 byte will set to the value 1001 ? the ten pointer-value bits (within the h1 and h2 bytes) will be set to new pointer value per the contents within the transmit sts-1/sts-3 poh - arbi trary h1 pointer and transmit sts-1/sts-3 poh arbitrary h2 pointer registers (address location= 0x07bf and 0xn9c3). n ote : afterwards, the n bits will resume their normal value of 0110 and this new pointer value will be used as the new pointer from this point on. once the user writes a 1 in to this bit-field, the XRT86SH328 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to 0.
preliminary XRT86SH328 153 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:2] - unused bit [1:0] - j1 byte insertion_method[1:0] these read/write bit-fields are used to specify the method that the user will use to insert the j1 byte into the outbound sts-1/sts-3 spe. the relationshi p between the contents of these bit-fields and the corresponding j1 byte insertion method is presented below. bit [7:4] - ndf (new data flag) bits these read/write bit-fields are used provide the value that will be loaded into the ndf bit-field (of the h1 byte), whenever a 0 to 1 transition occurs in bit 5 (pointer forc e) within the transmit sts-1/ sts-3 path - transmit path control register (address location= 0x07b7). bit [3:2] - ss bits these read/write bit-fields is used to provide the value that will be loaded into the ss bit-fields (of the h1 byte) whenever a 0 to 1 transition occurs in bit 5 (pointer force) within the tran smit sts-1/sts-3 path - transmit path control register (address location= 0x07b7). the ss bits have no functional value, within the h1 byte. bit [1:0] - h1 pointer value[1:0] these two read/write bit-fields, along with the constants of the transmit sts-1/sts-3 pa th - transmit arbitrary h2 pointer register (address location= 0x07c3) are us ed to provide the contents of the pointer word. these two read/write bit-fields are used to define the valu e of the two most significant bits within the pointer word. whenever a 0 to 1 transition occurs in bit 5 (pointer fo rce) within the transmit sts-1/sts-3 path - transmit path control register (address location= 0x07b7), the values of these two bits will be loaded into the two most significant t able 203: t ransmit sts-1/sts-3 p ath - sonet p ath j1 c ontrol r egister (a ddress l ocation = 0 x 07bb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused insertion_method[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 insertion method j1 b yte i nsertion m ethod [1:0] r esulting i nsertion m ethod 00 insert the value 0x00 01 not valid 10 insert from the transmit sonet path - transmit j1 byte value register (address location= 0x0793) 11 insert via the txpoh_n input port t able 204: t ransmit sts-1/sts-3 p ath - t ransmit a rbitrary h1 p ointer r egister (a ddress l ocation = 0 x 07bf) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ndf bits ss bits h1 pointer value r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 154 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits within the pointer word. bit [7:0] - h2 pointer value[1:0] these eight read/write bit-fields, along with the constant s of bits 1 and 0 within the transmit sts-1/sts-3 path - transmit arbitrary h1 pointer register (address location= 0x07c3) are used to provide the contents of the pointer word. these two read/write bit-fields are used to define the value of the eight least significant bits within the pointer word. ` whenever a 0 to 1 transition occurs in bit 5 (pointer fo rce) within the transmit sts-1/sts-3 path - transmit path control register (address location= 0x07b7), the values of these eight bits will be loaded into the h2 byte, within the outbound sts-1 or sts-3 data stream. bit [7:2] - unused bit [1:0] - transmit po inter word - high[1:0] these two read-only bits, along with the contents of the transmit sts-1/sts-3 path - tr ansmit current pointer byte register - byte 0 (address location= 0x07c7) reflect the cu rrent value of the pointer (o r offset of spe within the sts- 1/sts-3 frame). these two bits contain the two most significant bits within the 10-bit pointer word. bit [7:0] - transmit pointer word - low[7:0] these two read-only bits, along with the contents of the transmit sts-1/sts-3 path - tr ansmit current pointer byte register - byte 1 (address location= 0x07c6) reflect the cu rrent value of the pointer (o r offset of spe within the sts- 1/sts-3 frame). these two bits contain the eight le ast significant bits within the 10-bit pointer word. t able 205: t ransmit sts-1/sts-3 p ath - t ransmit a rbitrary h2 p ointer r egister (a ddress l ocation = 0 x 07c3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h2 pointer value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 206: t ransmit sts-1/sts-3 p ath - t ransmit c urrent p ointer b yte r egister - b yte 1 (a ddress l ocation = 0 x 07c6) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused tx_pointer_high[1:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 0 t able 207: t ransmit sts-1/sts-3 p ath - t ransmit c urrent p ointer b yte r egister - b yte 0 (a ddress l ocation = 0 x 07c7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx_pointer_low[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 1 0 1 0
preliminary XRT86SH328 155 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:4] - unused bit [3:1] - plm-p (path - pa yload mismatch) - rdi-p code these three read/write bit-fields are used to specify the value that the transmit sts- 1/sts-3 poh processor block will transmit, within the rdi-p bit-fields of the g1 by te (within the outbound sts- 1/sts-3 spe), whenever the corresponding receive sts-1/sts-3 poh processor block detect s and declares a plm-p condition. in order to enable this feature, the user must set bit 0 (rdi -p upon plm-p) within this register to 1. bit 0 - transmit rdi-p upon plm-p this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 poh proce ssor block to automatically transmit the rdi-p code (as configured in bits 3 through 1 - within this register) whenever the corresponding receive sts-1/sts-3 poh processor block declares a plm-p condition. ` 0 - disables the automatic transmission of rdi-p upon detection of plm-p. ` 1 - enables the automatic transmission of rdi-p upon detection of plm-p. bit [7:5] - tim-p (path - trace identifi cation message mismatch) - rdi-p code these three read/write bit-fields are used to specify the value that the transmit sts- 1/sts-3 poh processor block will transmit within the rdi-p bit-fields of the g1 byte (within the outbound sts-1/sts-3 spe), whenever the receive sts-1/sts-3 poh processor block detects and declares the tim-p defect condition. to enable this feature, the user must set bit 4 (t ransmit rdi-p upon tim-p) within this register to 1. bit 4 - transmit rdi-p upon tim-p this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 poh proce ssor block to automatically transmit the rdi-p code (as configured in bits 7 through 5 - within this register) whenever the corresponding receive sts-1/sts-3 poh processor block dec lares the tim-p defect condition. ` 0 - disables the automatic transmission of rdi-p upon detection of tim-p. ` 1 - enables the automatic transmission of rdi-p upon detection of tim-p. bit [3:1] - uneq-p (path - unequipped) - rdi-p code these three read/write bit-fields are used to specify the value that the transmit sts- 1/sts-3 poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within the outbound sts-1/sts-3 spe), whenever the receive sts-1/sts-3 poh processor block detects an d declares the uneq-p defect condition. to enable this feature, the user must set bit 0 (t ransmit rdi-p upon uneq-p) within this register to 1. bit 0 - transmit rdi-p upon uneq-p t able 208: t ransmit sts-1/sts-3 p ath - rdi-p c ontrol r egister - b yte 2 (a ddress l ocation = 0 x 07c9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused plm-p rdi-p code[2:0] transmit rdi-p upon plm-p r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 209: t ransmit sts-1/sts-3 p ath - rdi-p c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 07ca) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tim-p rdi-p code[2:0] transmit rdi-p upon tim -p uneq-p rdi-p code[2:0] transmit rdi-p upon uneq-p r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 156 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 poh proce ssor block to automatically transmit the rdi-p code (as configured in bits 3 through 1 - within this register) whenever the corresponding receive sts-1/sts-3 poh processor block dec lares the uneq-p defect condition. ` 0 - disables the automatic transmission of rdi-p upon detection of uneq-p. ` 1 - enables the automatic transmission of rdi-p upon detection of uneq-p. t able 210: t ransmit sts-1/sts-3 p ath - rdi-p c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 07cb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lop-p rdi-p code[2:0] transmit rdi-p upon lop-p ais-p rdi-p code[2:0] transmit rdi-p upon ais-p r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 157 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:5] - lop-p (path - loss of pointer) - rdi-p code these three read/write bit-fields are used to specify the value that the transmit sts- 1/sts-3 poh processor block will transmit, within the rdi-p bit-fields of the g1 by te (within the outbound sts- 1/sts-3 spe), whenever the corresponding receive sts-1/sts-3 poh processo r block detects and declares a lop-p condition. to enable this feature, the user must set bit 4 (rdi-p upon lop-p) with in this register to 1. bit 4 - transmit rdi-p upon lop-p this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 poh proce ssor block to automatically transmit the rdi-p code (as configured in bits 7 through 5 - within this register) whenever the corresponding receive sts-1/sts-3 poh processor block declares a lop-p condition ` 0 - disables the automatic transmissi on of rdi-p upon det ection of lop-p. ` 1 - enables the automatic transmission of rdi-p upon detection of lop-p. bit[3:1]ais-p (path - ais) - rdi-p code these three read/write bit-fields are used to specify the value that the transmit sts- 1/sts-3 poh processor block will transmit, within the rdi-p bit-fields of the g1 by te (within the outbound sts- 1/sts-3 spe), whenever the corresponding receive sts-1/sts-3 poh processo r block detects and declares an ais-p condition. to enable this feature, the user must set bit 4 (rdi-p upon ais-p) withi n this register to 1. bit 0 - transmit rdi-p upon ais-p this read/write bit-field is used to configure the tr ansmit sts-1/sts-3 poh proce ssor block to automatically transmit the rdi-p code (as configured in bits 7 through 5 - within this register) whenever the corresponding receive sts-1/sts-3 poh processor blo ck declares a ais-p condition. ` 0 - disables the automatic transmission of rdi-p upon detection of ais-p. ` 1 - enables the automatic transmission of rdi-p upon de tection of ais-p. bit [7:4] - unused bit 3:0] - txpohclk outp ut clock signal speed these read/write bit-fields are used to specify the frequency of the txpohclk output clock signal. the formula that relates the contents of these register bits to the txpohclk frequency is presented below. freq = 51.84 /[2 * (txpoh_clock_speed + 1) for sts-3/sts-1/sts-3 applications, the fr equency of the rxpohclk output signal must be in the range of 2.36mhz to 25.92mhz bit [7:0] - transmit negative pointer adju stment count - msb this reset-upon-read register, along with the transmit negative pointer adjustment count register - byte 0 presents a 16-bit representati on of the number of negative (or decrementi ng) pointer adjustments that have occurred t able 211: t ransmit sts-1/sts-3 p ath - s erial p ort c ontrol r egister (a ddress l ocation = 0 x 07cf) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused txpoh clock speed[4:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 212: t ransmit sts-1/sts-3 p ath - t ransmit n egative p ointer a djustment c ount r egister - b yte 1 (a ddress l ocation = 0 x 07d0) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_negative_pointer_adjustment_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 158 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 (in the outbound sts-1 or sts-3 data-stream) since the last read of this register. n ote : this register contains the msb (most significant bits) of this 16-bit expression. bit [7:0] - transmit negative po inter adjustment count - lsb this reset-upon-read register, along with the transmit negative pointer adjustment count register - byte 1 presents a 16-bit representati on of the number of negative (or decrementi ng) pointer adjustment s that have occurred (in the outbound sts-1 or sts-3 data-stream) since the last read of this register. n ote : this register contains the lsb (least significant bits) of this 16-bit expression. bit [7:0] - transmit positive pointer adjustment count - msb this reset-upon-read register, along with the transmit positi ve pointer adjustment count register - byte 0 presents a 16-bit representation of the number of positive (or incrementing) pointe r adjustments that have occurred (in the outbound sts-1 or sts-3 data-stream) sinc e the last read of this register. n ote : this register contains the msb (most si gnificant bits) of this 16-bit expression. bit [7:0] - transmit positive pointer adjustment count - lsb this reset-upon-read register, along with the transmit positi ve pointer adjustment count register - byte 1 presents a 16-bit representation of the number of positive (or incrementing) pointe r adjustments that have occurred (in the outbound sts-1 or sts-3 data-stream) sinc e the last read of this register. n ote : this register contains the lsb (least significant bits) of this 16-bit expression. to here 1/12/07 2.8 transmit tug-3 mapper/vc- 4 poh processor block regist ers (sdh/tug-3 applications only) the register map for the transmit tu-3 mapper/vc-4 po h processor block is presented an discussed in detail within the "sdh version of the register map". t able 213: t ransmit sts-1/sts-3 p ath - t ransmit n egative p ointer a djustment c ount r egister - b yte 0 (a ddress l ocation = 0 x 07d1) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_negative_pointer_ adjustment_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 214: t ransmit sts-1/sts-3 p ath - t ransmit p ositive p ointer a djustment c ount r egister - b yte 1 (a ddress l ocation = 0 x 07d2) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_positive_pointe r_adjustment_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 215: t ransmit sts-1/sts-3 p ath - t ransmit p ositive p ointer a djustment c ount r egister - b yte 1 (a ddress l ocation = 0 x 07d3) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit_positive_pointer _adjustment_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 159 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328 device, with the transmit tug-3 maper/vc -4 poh processor block "highlighted" is presented below in figure _. for detailed on the "transmit tug-3 mapper/vc-4 po h processor block" registers, please see the "XRT86SH328 28-channel ds1/e1 framer/liu wit h ds3 mux and tu-mapper ic - register map & description - sdh applications". 2.9 global vt mapper bl ock control registers the register map for the global vt mapper block is pr esented in the table below. additionally, a detailed description of each of the global vt mapper control registers is presented below. f igure 8. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the t rans - mit tug-3 m apper /vc-4 poh p rocessor block " highlighted " t able 216: g lobal c ontrol - vt-m apper b lock - vt m apper b lock c ontrol r egister (a ddress = 0 x 0c03) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused latch count rei-v enable unused sonet/sdh loop-back r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 sts-1/ stm-0 telecom bus interface sts-1/ stm-0 telecom bus interface transmit stm-1 soh processor block transmit stm-1 soh processor block receive stm-1 soh processor block receive stm-1 soh processor block transmit vc-3 poh processor block transmit vc-3 poh processor block receive vc-3 poh processor block receive vc-3 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from tu channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to tu channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 receive tug-3 mapper/ vc-4 poh processor block receive tug-3 mapper/ vc-4 poh processor block transmit tug-3 mapper/ vc-4 poh processor block transmit tug-3 mapper/ vc-4 poh processor block
XRT86SH328 preliminary 160 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:4] - unused bit 3 - latch count ` a "0 to 1" transition within this bit-field commands each of the vt-de-mapper blocks to update the contents within the following bit-fields/pmon registers. bit 2 - rei-v enable this read/write bit-field is used to configure a given transmit vt-mapper block to automatically insert the appropriate rei-v value (based upon the number of b2 bi t errors that are detected by the corresponding receive vt- mapper block) into the v5 byte, within its outbound vt1.5 or vt2 data-stream. ` 0 - configures the transmit vt-mapper block to not automatically insert the rei-v value into each v5 byte, within the outbound vt data-stream. ` 1 - configures the transmit vt-mapper block to automatically insert the rei- v value into each v5 byte, within the outbound vt data-stream. bit 1 - unused bit 0 - vt mpper sonet/sdh loop-back this read/write bit-field permits the user to configur e the XRT86SH328 device to operate in the "vt mapper sonet/sdh loop-back" mode. if the us er configures the XRT86SH328 device to operate in this mode, then the outputs (from each of the 28 vt-mapper blocks) will be intern ally looped back into the inputs of their corresponding vt- de-mapper block. figure _ presents an illustration of the XRT86SH328 device whenever it has been configured to operate in the "vt mapper sonet/sdh loop-back" mode. figure _, illustration of the functional block dia gram of the XRT86SH328 device with the "vt-mapper sonet/sdh loop-back" path depicted. b it f ields r egister n ame a ddress l ocation vt-payload pointer increment count[3:0] channel control vt mapper block - egress direction - bip-2 error count register - byte 1 0xnd4a bip-2 error count[11:8] channel control vt mapper block - egress direction - bip-2 error count register - byte 1 0xnd4a bip-2 error count[7:0] channel control vt mapper block - egress direction - bip-2 error count register - byte 0 0xnd4b vt-payload pointer dec - rement count[3:0] channel control - vt mapper block - egress direction - rei-v event count register - byte 1 0xnd4e rei-v event count[11:8] channel control - vt mapper block - egress direction - rei-v event count register - byte 1 0xnd4e rei-v event count[7:0] channel control - vt mapper block - egress direction - rei-v event count register - byte 0 0xnd4f
preliminary XRT86SH328 161 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 0 - does not configure the XRT86SH328 device to opera te in the "vt-mapper sonet/sdh loop-back" mode. ` 1 - configures the XRT86SH328 device to operate in the "vt-mapper sonet/sdh loop-back" mode. bit7 - latch error count a 0 to 1 transition within this bit-field commands the test patt ern receiver to latch its current bit error count into bits 6 - 0 (test pattern error count[14:8]) and bit [7:0] (test patt ern error count[7:0]) within the vt mapper - test pattern detector error count register (add ress locations = 0x0c16 and 0x0c17). bit6 - insert pattern error this bit-field is used to configure the vt-mapper test pattern gene rator block to insert a single bit-error into the outbound vt data-stream. a 0 to 1 trans ition within this bit-field will command the vt-mapper test pattern generator block to insert a single bit-error into the outbound vt data-stream. bits [5 - 0] - reserved f igure 9. i llustration of the f unctional b lock d iagram of the XRT86SH328 with the vt-m apper sonet/sdh l oop - back path depicted t able 217: g lobal c ontrol - vt-m apper b lock - t est p attern c ontrol r egister - b yte 1 (a ddress = 0 x 0c0e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 latch error count insert pat - tern error reserved r/w r/w r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 vt mapper sonet/sdh loop-back
XRT86SH328 preliminary 162 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits 7 - 6 - vt1.5 transmit test pattern[1:0] this read/write bit-field is used to specify the test patt ern that the vt1.5 test pattern generator will generate and transmit. bit[5:4] - vt2 transmit test pattern[1:0] this read/write bit-field is used to specify the test pa ttern that the vt2 test pattern generator will generate and transmit. bit[3:2] - vt3 transmit test pattern[1:0] this read/write bit-field is used to specify the test pa ttern that the vt3 test pattern generator will generate and transmit. t able 218: g lobal vt-m apper b lock - t est p attern c ontrol r egister - b yte 0 (a ddress = 0 x 0c0f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt1.5 transmit test pat - tern[1:0] vt2 transmit test pat - tern[1:0] vt3 transmit test pat - tern[1:0] vt6 transmit test pat - tern[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 transmitted test pattern vt1.5 t ransmit t est p attern [1:0] t est p attern t ransmitted 00 all zeros pattern 01 all ones pattern 10 repeating 1010? pattern 11 2^15-1 prbs pattern transmitted test pattern vt2 t ransmit t est p attern [1:0] t est p attern t ransmitted 00 all zeros pattern 01 all ones pattern 10 repeating 1010? pattern 11 2^15-1 prbs pattern transmitted test pattern vt3 t ransmit t est p attern [1:0] t est p attern t ransmitted 00 all zeros pattern 01 all ones pattern 10 repeating 1010? pattern 11 2^15-1 prbs pattern
preliminary XRT86SH328 163 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[1:0] - vt6 transmit test pattern[1:0] this read/write bit-field is used to specify the test pa ttern that the vt6 test pattern generator will generate and transmit. bit7-6 - test ch annel size[1:0]: these two read/write bit-fields are used to specify the size of the test channel (e.g., the channel that will be used to transport the user-specified test pattern. bit 5 - test channel drop side sonet/sdh this read/write bit-field is used to select the source of t he test channel. in this case, the user can either select either a ds1/e1 channel originating from the receive so net/sdh block or a ds1/e1 channel originating from the ingress direction ds1/e1 blocks. ` 0 - configures the test channel source to be one of the ds1/e1 channels, originating from the ingress direction ds1/e1 blocks. ` 1 - configures the test channel source to be the ds 1/e1 channels, originating from the receive sonet/sdh blocks bit[4:0] - test channel drop side[4:0] these read/write bit-fields are used to select wh ich data-stream will be outp ut via the test channel. transmitted test pattern vt6 t ransmit t est p attern [1:0] t est p attern t ransmitted 00 all zeros pattern 01 all ones pattern 10 repeating 1010? pattern 11 2^15-1 prbs pattern t able 219: g lobal c ontrol - vt-m apper b lock - t est p attern d rop r egister - b yte 1 (a ddress = 0 x 0c12) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test channel size[1:0] test channel drop side sonet/sdh test channel drop side[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 test channel size t est c hannel s ize [1:0] t est c hannel s ize 00 vt-6 01 vt-3 10 vt2/tu-12 11 vt1.5/tu-11
XRT86SH328 preliminary 164 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 output data stream via test channel t est c hannel d rop s ide [4:0] t est c hannel u sed 00000 do not use 00001 ds1/e1 channel 1 00010 ds1/e1 channel 2 00011 ds1/e1 channel 3 00100 ds1/e1 channel 4 00101 ds1/e1 channel 5 00110 ds1/e1 channel 6 00111 ds1/e1 channel 7 01000 ds1/e1 channel 8 01001 ds1/e1 channel 9 01010 ds1/e1 channel 10 01011 ds1/e1 channel 11 01100 ds1/e1 channel 12 01101 ds1/e1 channel 13 01110 ds1/e1 channel 14 01111 ds1/e1 channel 15 10000 ds1/e1 channel 16 10001 ds1/e1 channel 17 10010 ds1/e1 channel 18 10011 ds1/e1 channel 19 10100 ds1/e1 channel 20 10101 ds1/e1 channel 21 10110 ds1/e1 channel 22 10111 ds1/e1 channel 23 11000 ds1/e1 channel 24 11001 ds1/e1 channel 25 11010 ds1/e1 channel 26 11011 ds1/e1 channel 27 11100 ds1/e1 channel 28 11101 ais will be generated 11110 test channel input 11111 user selected test pattern
preliminary XRT86SH328 165 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bits 7 - 6 - receive (expected) pattern: this read/write bit-field is used to specify the test pattern, that the vt-mapper pattern receiver should be expecting, as shown in the table below. bit 5 - test channel drop-side sonet/sdh this read/write bit-field is used to select which set of ds1/e1 traffic should be used, as a basis of comparison against the test signal. in this case, the user can either se lect the either the ds1/e1 traf fic originating from the ingress direction ds1/e1 blocks or the ds1/e1 traffi c originating from the receive sonet/sdh blocks. ` 0 - configures the pattern receiver to compare the test signal with one of the ds1/e1 channels, originating from the ingress direction ds1/e1 blocks. ` 1 - configures the pattern receiver to compare the test signal with one of the ds1/e1 channels, originating from the receive sonet/sdh blocks. bit[4:0] - test chan nel drop side[4:0]: these read/write bit-fields are used to select wh ich data-stream will be co mpared with the test signal. t able 220: g lobal c ontrol - vt-m apper b lock - t est p attern d rop r egister - b yte 0 (a ddress = 0 x 0c13) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive (expected) pat - tern[1:0] test channel drop side - sonet/sdh test channel drop side[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 expected test pattern r eceive (e xpected ) p attern [1:0] e xpected t est p attern 00 all zeros pattern 01 all ones pattern 10 repeating 1010? pattern 11 2^15-1 prbs pattern test channel selection t est c hannel d rop s ide [4:0] t est c hannel u sed 00000 do not use 00001 ds1/e1 channel 1 00010 ds1/e1 channel 2 00011 ds1/e1 channel 3 00100 ds1/e1 channel 4 00101 ds1/e1 channel 5 00110 ds1/e1 channel 6 00111 ds1/e1 channel 7
XRT86SH328 preliminary 166 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - vt-mapper test pattern sync: 01000 ds1/e1 channel 8 01001 ds1/e1 channel 9 01010 ds1/e1 channel 10 01011 ds1/e1 channel 11 01100 ds1/e1 channel 12 01101 ds1/e1 channel 13 01110 ds1/e1 channel 14 01111 ds1/e1 channel 15 10000 ds1/e1 channel 16 10001 ds1/e1 channel 17 10010 ds1/e1 channel 18 10011 ds1/e1 channel 19 10100 ds1/e1 channel 20 10101 ds1/e1 channel 21 10110 ds1/e1 channel 22 10111 ds1/e1 channel 23 11000 ds1/e1 channel 24 11001 ds1/e1 channel 25 11010 ds1/e1 channel 26 11011 ds1/e1 channel 27 11100 ds1/e1 channel 28 11101 ais will be generated 11110 test channel input 11111 disable pattern receiver t able 221: g lobal c ontrol - vt-m apper - t est p attern d etector e rror c ount r egister - u pper b yte (a ddress = 0 x 0c16) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-mapper te s t p a t t e r n sync test pattern error count[14:8] r/o rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 test channel selection t est c hannel d rop s ide [4:0] t est c hannel u sed
preliminary XRT86SH328 167 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this read-only bit-field indicates whether or not the vt-map per pattern receiver is curr ently declaring pattern sync with the incoming test signal. ` 0 - vt-mapper pattern receiver is not currently decla ring pattern sync with the incoming test signal. ` 1 - vt-mapper pattern receiver is currently decl aring pattern sync with the incoming test signal. bit[6:0] - test pattern error count[14:8]: these seven (7) reset-upon-read bit-fiel ds, along with the test pattern error co unt[7:0] bit-fields function as a 15- bit pattern bit error count register. if the vt-mapper pattern receiver is cu rrently declaring pattern sync with the designated test signal, then it will incremen t this register (by the value of 1) each time that it detects pattern bit error. these seven (7) bit-fields function as the seven most-significant bits of this 15-bit counter. bit[7:0] - test pattern error count[7:0]: these eight (8) reset-upon-read bit-fields, along with the te st pattern error count[14:8] bit-fields function as a 15- bit pattern bit error count register. if the vt-mapper pattern receiver is cu rrently declaring pattern sync with the designated test signal, then it will incremen t this register (by the value of 1) each time that it detects pattern bit error. these eight (8) bit-fields function as the eight least-significant bits of this 15-bit counter. bits 7 - 6 - unused: bit[5:4] - transmit tributary size select for vt# 6[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 6) will support. n ote : this configuration setting only applies to the transmit vt-mapper block. this conf iguration setting does not configure the receive vt-de-mapper block to expect any particular vt-type within vt group # 6. the user t able 222: g lobal c ontrol - vt-m apper - t est p attern d etector e rror c ount r egister - l ower b yte (a ddress = 0 x 0c17) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test pattern error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 223: g lobal c ontrol - vt-m apper - t ransmit t ributary s ize s elect r egister (a ddress = 0 x 0c1a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused txtributary size select - vt#6[1:0] txtributary size select - vt#5[1:0] txtributary size select - vt#4[1:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 1 1 1 1 1 1 size of vt #6 t x t ributary s ize s elect - vt#6[1:0] r esulting s ize of vt # 6 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11
XRT86SH328 preliminary 168 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 must separately configure the receive vt-de-mapper bl ock's handling of vt-group # 6 by setting bits 4 and 5 (rxtributary size select - vt# 6[1:0]) within the vt-m apper - receive tributary size select register (address = 0x0c1e). bit[3:2] - transmit tributary size select for vt# 5[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 5) will support. bit[1:0] - transmit tributary size select for vt# 4[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 4), will support. bits 7 - 6 - transmit tributar y size select for vt# 3[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 3), will support. size of vt #5 t x t ributary s ize s elect - vt#5[1:0] r esulting s ize of vt # 5 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 size of vt #4 t x t ributary s ize s elect - vt#4[1:0] r esulting s ize of vt # 4 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 t able 224: g lobal c ontrol - vt-m apper - t ransmit t ributary s ize s elect r egister (a ddress = 0 x 0c1b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txtributary size select - vt#3[1:0] txtributary size select - vt#2[1:0] txtributary size select - vt#1[1:0] txtributary size select - vt#0[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 txtributary size select of vt#3 t x t ributary s ize s elect - vt#3[1:0] r esulting s ize of vt # 3 00 vt-6 01 vt-3
preliminary XRT86SH328 169 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[5:4] - transmit tributary size select for vt# 2[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 2) will support. bit[3:2] - transmit tributary size select for vt# 1[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 1) will support. bit[1:0] - transmit tributary size select for vt# 0[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the transmit vt-mapper block (associated with virtual tributary group # 0) will support. 10 vt-2/tu-12 11 vt-1.5/tu-11 txtributary size select of vt#2 t x t ributary s ize s elect - vt#2[1:0] r esulting s ize of vt # 2 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 txtributary size select of vt#1 t x t ributary s ize s elect - vt#1[1:0] r esulting s ize of vt # 1 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 txtributary size select of vt#0 t x t ributary s ize s elect - vt#0[1:0] r esulting s ize of vt # 0 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 txtributary size select of vt#3 t x t ributary s ize s elect - vt#3[1:0] r esulting s ize of vt # 3
XRT86SH328 preliminary 170 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits 7 - 6 - unused: bit[5:4] - receive tributary size select for vt# 6[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 6) will support. bit[3:2] - receive tributary size select for vt# 5[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 5) will support. bit[1:0] - receive tributary size select for vt# 4[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 4) will support. t able 225: g lobal c ontrol - vt-m apper - r eceive t ributary s ize s elect r egister (a ddress = 0 x 0c1e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused rxtributary size select - vt#6[1:0] rxtributary size select - vt#5[1:0] rxtributary size select - vt#4[1:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 1 1 1 1 1 1 resulting size of vt#6 r x t ributary s ize s elect - vt#6[1:0] r esulting s ize of vt # 6 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 resulting size of vt#5 r x t ributary s ize s elect - vt#5[1:0] r esulting s ize of vt # 5 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 resulting size of vt#4 r x t ributary s ize s elect - vt#4[1:0] r esulting s ize of vt # 4 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11
preliminary XRT86SH328 171 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[7:6] - receive tributary size select for vt# 3[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 3) will support. bit[5:4] - receive tributary size select for vt# 2[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 2) will support. bit[3:2] - receive tributary size select for vt# 1[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 1) will support. t able 226: g lobal c ontrol - vt-m apper - r eceive t ributary s ize s elect r egister (a ddress = 0 x 0c1f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxtributary size select - vt#3[1:0] rxtributary size select - vt#2[1:0] rxtributary size select - vt#1[1:0] rxtributary size select - vt#0[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 resulting size of vt#3 r x t ributary s ize s elect - vt#3[1:0] r esulting s ize of vt # 3 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 resulting size of vt#2 r x t ributary s ize s elect - vt#2[1:0] r esulting s ize of vt # 2 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 resulting size of vt#1 r x t ributary s ize s elect - vt#1[1:0] r esulting s ize of vt # 1 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11
XRT86SH328 preliminary 172 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit[1:0] - receive tributary size select for vt# 0[1:0]: these two read/write bit-fields are used to specify the vt-s ize (or the bit-rate to be supported by) that the receive vt-mapper block (associated with virtual tributary group # 0) will support. 2.10 ds3 mapper control registers bit[7:0] - reserved bit 1 - default_r value: when a ds3 signal is mapped into an sts-1/sts-3 spe or a vc -3, there are numerous bits that are also stuffed into the sts-1/sts-3 spe or the vc-3 in order to accommodate the frequency differences between ds3 and an sts- 1/sts-3 spe or an sdh vc-3. one such bit is referred to as an r bit. currently, the sta ndards do not define a use for these bits. hence, this bit can be used as a proprietary communicatio n link between two pieces of equipment. this read/write bit-field is used to set the value for the r bits in the outbound sts-1/sts- 3 spe or sdh vc-3. n otes : 1. the XRT86SH328 includes a corresponding read-only register bit, in which one can obtain the value for the r bits in the incomi ng sts-1/sts-3 spe or sdh vc-3. this regi ster bit is located in bit 1 (received r) within the ds3 mapper block - receive st atus register - byte 1 (address = 0x0d06). 2. this register bit is only active if the XRT86SH328 has been configured to operate in the m13 mux which is asynchronously mapped into sts-1/sts-3 mode. bit 0 - default_o value: when a ds3 signal is mapped into a sts-1/sts-3 spe (in sone t) or a vc-3 (in sdh), there are numerous bits that are also stuffed into the sts-1/sts-3 spe or the vc-3 in order to accommodate the frequency differences between ds3 and an sts-1/sts-3 spe or an sdh vc-3. one such bit is referred to as an 0 bit. currently, the standards do not define a use for these bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read/write bit-field is used to set the value for t he o bits in the outbound sts-1/sts-3 spe or sdh vc-3. n otes : 1. the XRT86SH328 includes a corresponding read-only register bit in which one can obtain the value for the o bits in the incoming sts-1/ sts-3 spe or sdh vc-3. this register bit is located in bit 0 (received o) within the ds3 mapper block - receive status register - byte 1 (address = 0x0d06). 2. this register bit is only active if the xrt86s h328 has been configured to operate in the m13 mux asynchronously mapped into sts-1/sts-3 mode. resulting size of vt#0 r x t ributary s ize s elect - vt#0[1:0] r esulting s ize of vt # 0 00 vt-6 01 vt-3 10 vt-2/tu-12 11 vt-1.5/tu-11 t able 227: ds3 m apper b lock - c ontrol r egister - b yte 1 (a ddress l ocation = 0 x 0d02) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved default_r default_o r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 1 1
preliminary XRT86SH328 173 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[7:1] - reserved bit 0 - gap clock in egress t1/e1 this read/write bit-field permits the user to apply some "clock-smoothing" to the egress direction t1/e1 signals prior to being routed to the transmit ds1/e1 liu block, as depicted below. ` 0 - configures the chip to perform "clock-smoothing" on all eg ress direction t1/e1 signals prior to being routed to the transmit ds1/e1 liu blocks. ` 1- disables this "clock-smoothing" feature. bit[7:2] - reserved: bit 1 - received_r: when a ds3 signal is de-mapped from an sts-1/sts-3 spe (in sonet) or a vc-3 (in sdh), there are numerous bits that were also stuffed into the sts-1/sts-3 spe or th e vc-3 in order to accommodate the frequency differences between ds3 and an sts-1/sts-3 spe or an sdh vc-3. one such bit is referred to as an r bit. currently, the sta ndards do not define a use for these bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read-only bit-field cont ains the value of the r bits within the most recently received sts-1/sts-3 spe or sdh vc-3. n ote : the XRT86SH328 includes a corresponding read/write regi ster bit, in which one can set the value for the r bits, in the outbound sts-1/sts-3 spe or sdh vc-3. this re gister bit is located in bi t 1 (default_r) within the ds3 mapper block - control register - byte 1 (address = 0x0d02). bit 0 - received_o: when a ds3 signal is de-mapped from an sts-1/sts-3 spe (in sonet) or a vc-3 (in sdh), there are numerous bits that were also stuffed into the sts-1/sts-3 spe or th e vc-3 in order to accommodate the frequency difference between ds3 and an sts-1/sts-3 spe or an sdh vc-3. one such bit is referred to as an o bit. currently, the stand ards do not define a use for thes e bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read-only bit-field contains the value of the o bits within the most re cently received sts-1/sts-3 spe or sdh vc-3. n ote : the XRT86SH328 includes a corresponding read/write regi ster bit, in which one can set the value for the r bits, in the outbound sts-1/sts-3 spe or sdh vc-3. this re gister bit is located in bit 1 (default r) within the ds3 mapper block - control register - byte 1 (address = 0x0d02). t able 228: ds3 m apper b lock - c ontrol r egister - b yte 0 (a ddress l ocation = 0 x 0d03) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gap clock in egress t1/e1 r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 t able 229: ds3 m apper b lock - r eceive s tatus r egister - b yte 1 (a ddress l ocation = 0 x 0d06) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved received_r received_o r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 1
XRT86SH328 preliminary 174 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit[7:4] - reserved: bit 3 - receive fifo overrun this read-only bit-field indicates whether or not the ds3 m apper block is currently decl aring a receive fifo overrun condition. a receive fifo overrun condition will only occur if ds3 data is output from th e ds3 mapper block to the receive ds3 framer block at a much faster rate than that which the receive ds3 framer block handles and processes the incoming ds3 data-stream. ` 0 - indicates that the ds3 mapper block is not curr ently declaring the receive fifo overrun condition. ` 1 - indicates that the ds3 mapper block is current ly declaring the receive fifo overrun condition. bit 2 - receive fifo underrun this read-only bit-field indicates whether or not the ds 3 mapper block is currently declaring the receive fifo underrun condition. a receive fifo underrun condition will only occur if ds3 data is output from the ds3 mapper block to the receive ds3 framer block at a much slower rate th an that which the receive ds3 framer bl ock handles and processes the incoming ds3 data-stream. ` 0 - indicates that the ds3 mapper block is not curr ently declaring the receive fifo underrun condition. ` 1 - indicates that the ds3 mapper block is current ly declaring the receive fifo underrun condition. bit 1 - transmit fifo overrun this read-only bit-field indicates whether or not the ds 3 mapper block is currently declaring a transmit fifo overrun condition. a transmit fifo overrun condition will occur if ds3 data is output from the transmit ds 3 framer block (towards the ds3 mapper block) at a much faster rate than which the ds3 mapper block handles and processes the outbound ds3 data-stream. ` 0 - indicates that the ds3 mapper block is not curr ently declaring the transmit fifo overrun condition. ` 1 - indicates that the ds3 mapper block is currently declaring the transmit fifo overrun condition. bit 0 - transmit fifo underrun this read-only bit-field indicates whether or not the ds 3 mapper block is currently declaring a transmit fifo underrun condition. a transmit fifo underrun condition will occur if ds3 data is output from the transmit ds 3 framer block (towards the ds3 mapper block) at a much slower ra te than that which the ds3 mapper block handles and processes the outbound ds3 data-stream. ` 0 - indicates that the ds3 mapper block is not curr ently declaring the transmit fifo underrun condition. ` 1 - indicates that the ds3 mapper block is currently declaring the transmit fifo underrun condition. t able 230: ds3 m apper b lock - r eceive s tatus r egister - b yte 0 (a ddress l ocation = 0 x 0d07) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved receive fifo over - run receive fifo under - run transmit fifo over - run transmit fifo under - run r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 175 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[7:4] - reserved bit 3 - receive fifo overrun interrupt status this reset-upon-read bit-fiel d indicates whether or not the receive fifo overrun in terrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3 mapper block will generate this interrupt anytime it declares a receive fifo overrun condition. ` 0 - indicates that the receive fifo overrun interrupt ha s not occurred since the last read of this register. ` 1 - indicates that the receive fifo overrun interrupt has occurred since the last read of this register. n ote : the user can obtain the current status of the receive fifo overrun condi tion by reading the state of bit 3 (receive fifo overrun condition) within the ds3 mapper - status register - byte 0 (address = 0x0d07). bit 2 - receive fifo underrun interrupt status this reset-upon-read bit-fiel d indicates whether or not th e receive fifo underrun inte rrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3 mapper block will generate this interrupt anytime it declares a receive fifo underrun condition. ` 0 - indicates that the receive fifo underrun interrupt has not occurred since the la st read of this register. ` 1 - indicates that the receive fifo underrun interrupt has occurred since the last read of this register. n ote : the user can obtain the current status of the receiv e fifo underrun condition by reading the state of bit 2 (receive fifo underrun condition) within the ds3 mapp er - status register - byte 0 (address = 0x0d07). bit 1 - transmit fifo overrun interrupt status this reset-upon-read bit-field indicates whether or not t he transmit fifo overrun interrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3 mapper block will generate this interrupt anytime it declares a transmit fifo overrun condition. ` 0 - indicates that the transmit fifo overrun interrupt has not occurred since the last read of this register. ` 1 - indicates that the transmit fifo overrun interrupt has occurred since the last read of this register. n ote : the user can determine the cu rrent status of the transmit fifo overrun conditio n by reading the state of bit 1 (transmit fifo overrun condition) within the ds3 mapper block - status register - byte 0 (address = 0x0d07). bit 0 - transmit fifo underrun interrupt status this reset-upon-read bit-field indicates whether or not th e transmit fifo underrun interrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3 mapper block will generate this interrupt anytime it declares a transmit fifo underrun condition. ` 0 - indicates that the transmit fifo underrun interrupt has not occurred since the last read of this register. ` 1 - indicates that the transmit fifo underrun interrupt has occurred since the last read of this register. t able 231: ds3 m apper b lock - r eceive m apper i nterrupt s tatus r egister - b yte 0 (a ddress = 0 x 0d0b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved receive fifo over - run interrupt status receive fifo under - run interrupt status transmit fifo over - run interrupt status transmit fifo under - run interrupt status r/o r/o r/o r/o rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 176 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 n ote : the user can determine the current state of the transmit fifo underrun condition by reading the state of bit 0 (transmit fifo underrun condition) within the ds3 ma pper block - status register - byte 0 (address = 0x0d07). bit[7:4] - reserved: bit 3 - receive fifo overrun interrupt enable this read/write bit-field is used to either enable or disable the receive fifo overrun interrupt. if this interrupt is enabled, then the ds3 mapper block will generate an interrupt anytime it declares the receive fifo overrun condition. ` 0 - disables this interrupt. ` 1 - enables this interrupt. bit 2 - receive fifo underrun interrupt enable this read/write bit-field is used to either enable or disable the 'receive fifo underrun interrupt. if this interrupt is enabled, then the ds3 mapper block will generate an interrupt anytime it declares the receive fifo underrun condition. ` 0 - disables this interrupt. ` 1 - enables this interrupt. bit 1 - transmit fifo overrun interrupt enable this read/write bit-field is used to either enabl e or disable the transmit fifo overrun interrupt. if this interrupt is enabled, then the ds3 mapper block will generate an interrupt anytime it declares the transmit fifo overrun condition. ` 0 - disables this interrupt. ` 1 - enables this interrupt. bit 0 - transmit fifo underrun interrupt enable this read/write bit-field is used to either enable or disable the transmit fifo underrun interrupt. if this interrupt is enabled, then th e ds3 mapper block will generate an interru pt anytime that the ds3 mapper block declares the transmit fifo underrun condition. ` 0 - disables this interrupt. ` 1 - enables this interrupt. bit7 - pstuff: t able 232: ds3 m apper b lock - r eceive m apper i nterrupt e nable r egister - b yte 0 (a ddress = 0 x 0d0e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved receive fifo over - run interrupt enable receive fifo under - run interrupt enable transmit fifo over - run interrupt enable transmit fifo under - run interrupt enable r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 233: ds3 m apper b lock - p ointer j ustification s tatus r egister - b yte 2 (a ddress = 0 x 0d21) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pstuff unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 177 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[6:0] - unused: 2.11 ds3 framer and m13 mux block registers the register map for the ds3 framer and m13 mux block is presented in the tables below. additionally, a detailed description of each of the ds3 framer and m13 mux block registers is presented below. in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328, with the various functions that are co ntrolled/monitored via the ds3 framer and m13 mux block register highlighted is presented below in figure 10 . t able 234: ds3 m apper b lock - p ointer j ustification s tatus r egister - b yte 1 (a ddress = 0 x 0d22) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t able 235: ds3 m apper b lock - p ointer j ustification s tatus r egister - b yte 0 (a ddress = 0 x 0d23) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t able 236: ds3 m apper b lock - p ointer j ustification j itter c ontrol r egister - b yte 1 (a ddress = 0 x 0d26) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t able 237: ds3 m apper b lock - p ointer j ustification j itter c ontrol r egister - b yte 0 (a ddress = 0 x 0d27) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
XRT86SH328 preliminary 178 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 n ote : these functional blocks are only active if the XRT86SH328 has been configured to oper ate in either the m13 mux or in the m13 mux, which is asynchronously mapped into sts-1/sts-3 mode. bit7 - ds3 framer local loop-back mode: this read/write bit-field is used to configure the ds3/e3 framer block to operate in the ds3 framer block to operate in the ds3 framer local loop-back mode. if the ds3 framer block has been configured to o perate in the framer local loop-back mode, then the output of the transmit ds3 framer block will be in ternally looped-back into the receive ds3 framer block. ` 0 - configures the ds3/e3 framer blo ck to operate in the normal operation (e .g., non-ds3 framer local loop-back) mode ` 1 - configures the ds3/e3 framer block to operate in the ds3 framer local loop-back mode. f igure 10. i llustration of the f unctional b lock d iagram of the XRT86SH328, with the f unctional b locks ( which are controlled / monitored via the ds3 f ramer and m13 mux b lock registers ) high - lighted . t able 238: ds3 f ramer b lock o perating m ode r egister (a ddress = 0 x 0e00) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds3 framer local loop- back set ds3 mode internal los enable ds3 framer block soft - ware reset reserved frame format timrefsel[1:0] r/w r/w r/w r/w r/o r/w r/w r/w 0 1 1 0 0 0 1 1 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
preliminary XRT86SH328 179 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit6 - set ds3 mode to use the transmit and receive ds3 framer blocks, within the XRT86SH328, then the user must set this bit-field to 1. bit 5 - internal los enable this read/write bit-field is used to enable or disable the internal los detector within the receive ds3 framer block. if the user enables the internal los detector, then the rece ive ds3 framer block will be configured to check the incoming ds3 signal for a sufficient number of consecutive a ll zero bits and it will declare and clear the los defect condition based upon the 1s density and the number of c onsecutive 0bits within the incoming ds3 data-stream. if the user disables the internal los detector, then the receive ds3 framer bl ock will not be configured to check the incoming ds3 data-stream for a sufficient number of consecutiv e 0 bits, and it will not declare nor clear the los defect condition based upon the 1s density and the number of c onsecutive 0 bits within the incoming ds3 data-stream. ` 0 - disables the internal los detector ` 1 - enables the internal los detector. bit 4 - ds3 framer block software reset this read/write bit-field is used to execute a software reset to the transmit and receive ds3 framer block. if the user executes this software reset , then the contents of th e transmit/receive ds3 framer block configuration registers will not be reset to their default values. instead, internal state machines (within the transmit and receive ds3 framer blocks) will be reset. ` a 0 to 1 transition in this bit-fiel d commands a software reset to transm it and receive ds3 framer block. bit 3 - reserved bit 2 - frame format this read/write bit-field is used to configure the transmit and receive ds3 framer blocks to operate in either the c-bit parity or the m13/m23 framing formats. ` 0 - configures the transmit and receive ds3 framer blocks to operate in the c-bit parity framing format. ` 1 - configures the transmit and receive ds3 framer blocks to operate in the m13/m23 framing format. bit[1:0] - transmit ds3 framer bl ock timing refere nce select[1:0] the user should set these bit-fields to eith er [1, 0] or [1, 1] for proper operation. bit7 - disable transmit loss of clock feature this read/write bit-field is used to either en able or disable the transmit loss of clock feature. if this feature is enabled, then the ds 3 framer block will enable some circuitry that will terminate the current read or write access (to the microp rocessor interface), if a loss of tr ansmit clock event were to occur. the intent behind this feature is to prevent any read/wri te accesses (to the ds3 framer blocks) from hanging in the event of a loss of clock event. ` 0 - enables the transmit loss of clock feature. ` 1 - disables the transmit loss of clock feature bit6 - loc bit 5 - disable receive loss of clock feature this read/write bit-field is used to either en able or disable the receive loss of clock feature. if this feature is enabled, then the ds 3 framer block will enable some circuitry that will terminate the current read or t able 239: ds3 f ramer b lock - i/o c ontrol r egister (a ddress = 0 x 0e01) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 disable txloc loc disable rxloc unused transmit line clock invert receive line clock invert reframe r/w r/o r/w r/o r/o r/w r/w r/w 1 0 1 0 0 0 0 0
XRT86SH328 preliminary 180 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 write access (to the microp rocessor interface), if a loss of receive clock even t were to occur. the intent behind this feature is to prevent any read/wri te accesses (to the ds3 framer blocks) from hanging in the event of a loss of clock event. ` 0 - enables the receive loss of clock feature. ` 1 - disables the receive loss of clock feature bits 4 -3 - unused bit 2 - transmit line clock invert this read/write bit-field is used to configure the transmit ds3 framer block to update the txds3pos and txds3neg output pins upon either the rising or falling edge of txds3lineclk. ` 0 - configures the transmit ds3 fr amer block to update the txds3pos/txds3neg upon the rising edge of the txds3lineclk. the user should insure that the liu ic will sample txds3pos/txds3neg upon the falling edge of txds3lineclk. ` 1 - configures the transmit ds3 fram er block to update the txds3pos/txds3neg upon the falling edge of the txds3lineclk. the user should insure that the liu ic will sample txds3pos/txds3neg upon the rising edge of txds3lineclk. bit 1 - receive line clock invert this read/write bit-field is used to configure receive ds3 framer block to sample and latch the rxds3pos/rxds3neg input pins upon either the rising or falling edge of rxds3lineclk. ` 0 - configures the receive ds3 framer block to sample the rxds3pos/rxds3neg input pins upon the falling edge of the rxds3lineclk input signal. ` 1 - configures the receive ds3 framer block to sample the rxds3pos/rxds3neg input pins upon the rising edge of the rxds3lineclk input signal. bit 0 - receive ds3 framer block - reframe command a 0 to 1 transition, within this bit-field commands the re ceive ds3 framer block to exit the frame maintenance mode, and go back and enter the frame acquisition mode. n ote : the user should go back and set this bit-field to 0 following execute of the reframe command. bit 7 - receive ds3 framer bock interrupt enable: this read/write bit-field is used to enable or disable the receive ds3 framer block for interrupt generation. if the user enables the receive ds3 framer block (for interrupt generation) at the block level, the user still needs to enable the interrupts at the source le vel, as well, in order for these interrupt to be enabled. however, if the user disables the receive ds3 framer blo ck (for interrupt generation) at the block level, then all receive ds3 framer-relate d blocks are disabled. ` 0 - disables all receive ds 3 framer blocks interrupts. ` 1 - enables the receive ds3 framer block fo r interrupt generation (at the block level) bits 6 - 5 - unused: bit 4 - m13 mux block interrupt enable: this read/write bit-field is used to enable or disable the m13 mux block for interrupt generation. if the user enables t able 240: ds3 f ramer b lock - b lock i nterrupt e nable r egister (a ddress = 0 x 0e04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive ds3 framer block interrupt enable unused m13 mux block inter - rupt enable unused transmit ds3 framer block interrupt enable one second interrupt enable r/w r/o r/o r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 181 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications the m13 mux block (for interrupt generation) at the block level, the user still needs to enable the interrupts at the source level as well, in order for these interrupts to be enabled. however, if the user disables the m13 mx block (for interrupt generation) at the block level, then all m13 mux block- related interrupts are disabled. ` 0 - disables all m13 mux block-related interrupts. ` 1 - enables all m13 mux block-related interrupts. bits 3 - 2 - unused bit 1 - transmit ds3 framer block interrupt enable: this read/write bit-field is used to en able or disable the transmit ds3 framer bl ock for interrupt generation. if the user enables the transmit ds3 framer block (for interrupt generation) at the block level, the user still needs to enable the interrupts at the source level as well, in order for these interrupts to be enabled. however, if the user disables the transmit ds3 framer blo ck (for interrupt generation) at the block level, then all transmit ds3 framer block-related interrupts are disabled. ` 0 - disables all transmit ds3 framer block-related interrupts. ` 1 - enables the transmit ds3 framer block for interrupt generation (at the block level). bit 0 - one second interrupt enable: this read/write bit-field is used to enable or disable the one-second interrupt within the ds3/e3 framer block. if the user enables this interrupt, then the ds3/e3 framer block will generate an interrupt at one second intervals. 0 - disables the one second interrupt 1 - enables the one second interrupt. bit 7 - receive ds3 framer bock interrupt status: this read-only bit-field indicates whether or not the re ceive ds3 framer block is requesting interrupt service. ` 0 - indicates that the receive ds3 framer bloc k is not currently requesting interrupt service. ` 1 - indicates that the receive ds3 framer bl ock is currently requesting interrupt service. bits 6 - 5 - unused: bit 4 - m13 mux block interrupt status: this read-only bit-field indicates whether or not the m13 mux block is requesting interrupt service. ` 0 - indicates that the m13 mux block is not currently requesting interrupt service. ` 1 - indicates that the m13 mux block is currently requesting interrupt service. bits 3 - 2 - unused bit 1 - transmit ds3 framer block interrupt status: this read-only bit-field indicates whether or not the tr ansmit ds3 framer block is requesting interrupt service. ` 0 - indicates that the transmit ds3 framer blo ck is not currently reques ting interrupt service. ` 1 - indicates that the transmit ds3 framer bl ock is currently requesting interrupt service. bit 0 - one second interrupt status: t able 241: ds3 f ramer b lock - b lock i nterrupt s tatus r egister (a ddress = 0 x 0e05) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive ds3 framer block interrupt status unused m13 mux block interrupt status unused transmit ds3 framer block interrupt status one second interrupt status rur r/o r/o rur r/o r/o rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 182 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this reset-upon-read bit-field indicates whether or not a one second interrupt has occurr ed since the last read of this register. ` 0 - indicates that the one second interrupt has not occurred since the last read of this register. ` 1 - indicates that the one second interrupt has o ccurred since the last read of this register. bit[7:4] - must set to 0: each of these read/write bit-fields must be set to 0 for proper operation. bit 3 - m13 local loop-back mode this read/write bit-field is used to configure the XRT86SH328 to operate in the m13 local loop-back mode. if the user configures the XRT86SH328 to operate in the m23 loc al loop-back mode, then the output of the m23 mux block will be internally routed to the input of the m13 demux block. ` 0 - configures the XRT86SH328 to operate in the normal mode ` 1 - configures the XRT86SH328 to o perate in the m13 local loop-back mode figure 11 presents an illustration of the XRT86SH328, whenever it has been configured to ope rate in the m13 local loop-back mode. t able 242: ds3 f ramer b lock - m23 c onfiguration r egister (a ddress = 0 x 0e07) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 must set to 0 m13 local loop-back mode reserved m23 loop-back codes[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 183 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 2 - reserved bit[1:0] - m23 loop-back codes[1:0] these read/write bit-fields are used to specify the coding (or the values that the transmit ds3 framer block will set the c-bits to) in order to request the remote terminal equipment to operate in the remote ds3 loop-back mode. n ote : anytime the transmit ds3 framer block has been configur ed to transmit a ds2 loop-back request code to the remote terminal equipment, then it will set the c-bits to the appropriate value (based upon the user-selection) as specified in the above table. further, the tran smit ds3 framer block will transmit these ds2 loop-back request codes (to the remote terminal equipment) fo r the appropriate ds2 cha nnel, whenever the user f igure 11. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever it has been configured to operate in the m13 l ocal l oop - back m ode codes to request remote ds3 loop-back mode m23 l oop -b ack c odes [1:0] c-b it s ettings to r equest ds2 l oop - back c odes c omments 00/11 cj1 = cj2 = cj3* the transmit ds3 framer block will invert the state of the cj3 bit (from t hat of the corresponding cj1 and cj2 bits) in order to request that the remote terminal execute a ds2 remote loop-back within the jth ds2 channel. 01 cj1 = cj2* = cj3 the transmit ds3 framer block will insert the state of the of the cj2 bit (from that of the corresponding cj1 and cj3 bits) in order to request that the remote terminal exe - cute a remote loop-back within the jth ds2 channel. 10 cj1* = cj2 = cj3 the transmit ds3 framer block will invert the state of the cj1 bit (from t hat of the corresponding cj2 and cj3 bits) in order to request that the remote terminal execute a remote loop-back within the jth ds2 channel. sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
XRT86SH328 preliminary 184 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 commands it to do so by setting any one of the bi ts within the ds3 framer block - m23 - ds2 loop-back request register (address = 0x0e09) to 1. bit7 - reserved bit6 - transmit ds2 ais - ds2 channel 6: this read/write bit-field is used to configure the m12 mu x block (associated with ds2 channel 6) to transmit the ds2 ais indicator, towards the transmit ds3 framer block (and within the outbound ds3 data-stream). ` 0 - configures the m12 mux block (associated with ds2 channel 6) to transmit normal data. ` 1 - configures the m12 mux block (associated with ds2 channel 6) to transmit the ds2 ais indicator. figure 12 presents an illustration of the XRT86SH328, whenever the m1 2 mux has been configured to transmit the ds2 ais indicator towards both the m23 mux and the transmit ds3 framer blocks. bit 5 - transmit ds2 ais - ds2 channel 5: see bit6 description. t able 243: ds3 f ramer b lock - m23 t ransmit ds2 ais c ommand r egister (a ddress = 0 x 0e08) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved transmit ds2 ais - ds2 channel 6 transmit ds2 ais - ds2 channel 5 transmit ds2 ais - ds2 channel 4 transmit ds2 ais - ds2 channel 3 transmit ds2 ais - ds2 channel 2 transmit ds2 ais - ds2 channel 1 transmit ds2 ais - ds2 channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 f igure 12. a n illustration of the XRT86SH328, whenever the m12 mux has been configured to transmit the ds2 ais indicator towards both the m23 mux and the t ransmit ds3 f ramer block sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 ais pattern
preliminary XRT86SH328 185 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 4 - transmit ds2 ais - ds2 channel 4: see bit6 description. tbit 3 - transmit ds2 ais - ds2 channel 3: see bit6 description. bit 2 - transmit ds2 ais - ds2 channel 2: see bit6 description. bit 1 - transmit ds2 ais - ds2 channel 1: see bit6 description. bit 0 - transmit ds2 ais - ds2 channel 0 see bit6 description. bit7 - reserved: bit6 - transmit ds2 loop-back request - ds2 channel 6: this read/write bit-field is used to command the tran smit ds3 framer block to transmit the loop-back request indicator, for ds2 channel 6. ` 0 - the transmit ds3 framer block will not transmit the loop-back request for ds2 channel #6 (normal operation) ` 1 - the transmit ds3 framer block will trans mit the loop-back request for ds2 channel # 6. n ote : whenever the user executes this co mmand, then the transmit ds3 framer block will invert the appropriate c- bit of the three (e.g., c71, c72 or c73) based upo n the user's setting of bits 1 and 0 (m23 loop-back codes[1:0]) within the ds3 framer block - m 23 configuration register (address = 0x0e07). bit 5 - transmit ds2 loop-back request - ds2 channel 5: see bit6 description. bit 4 - transmit ds2 loop-back request - ds2 channel 4: see bit6 description. bit 3 - transmit ds2 loop-back request - ds2 channel 3: see bit6 description. bit 2 - transmit ds2 loop-back request - ds2 channel 2: see bit6 description. bit 1 - transmit ds2 loop-back request - ds2 channel 1: see bit6 description. bit 0 - transmit ds2 loop-back request - ds2 channel 0: see bit6 description. t able 244: ds3 f ramer b lock - m23 - ds2 l oop - back r equest r egister (a ddress = 0 x 0e09) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved transmit ds2 loop- back request - ds2 channel 6 transmit ds2 loop- back request - ds2 channel 5 transmit ds2 loop- back request - ds2 channel 4 transmit ds2 loop- back request - ds2 channel 3 transmit ds2 loop- back request - ds2 channel 2 transmit ds2 loop- back request - ds2 channel 1 transmit ds2 loop- back request - ds2 channel 0 r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 186 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - reserved bit6 - remote ds2 loop -back - ds2 channel 6 this read/write bit-field is used to configure the XRT86SH328 to perform a remote loop-back of ds2 channel 6. if the user configures the XRT86SH328 to perform this loop-back, then the re ceive direction ds2 signal (associated with channel 6) will internally be looped back into the transmit direction. ` 0 - configures ds2 channel 6 to oper ate in the normal (no loop-back) mode ` 1 - configures ds2 channel 6 to oper ate in the remote loop-back mode. figure 13 presents an illustration of the functional bloc k diagram of the XRT86SH328, whenever a given ds2 channel has been configured to operate in the remote ds2 loop-back mode. bit 5 - remote ds2 loop-back - ds2 channel 5 see bit6 description. t able 245: ds3 f ramer b lock - m23 l oop - back a ctivation r egister (a ddress = 0 x 0e0a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved remote ds2 loop-back - ds2 chan - nel 6 remote ds2 loop-back - ds2 chan - nel 5 remote ds2 loop-back - ds2 chan - nel 4 remote ds2 loop-back - ds2 chan - nel 3 remote ds2 loop-back - ds2 chan - nel 2 remote ds2 loop-back - ds2 chan - nel 1 remote ds2 loop-back - ds2 chan - nel 0 r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 f igure 13. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever a given ds2 c hannel has been configured to operate in the r emote ds2 l oop - back m ode sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 remote loop-back in ds2 channel 0
preliminary XRT86SH328 187 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 4 - remote ds2 loop-back - ds2 channel 4 see bit6 description. bit 3 - remote ds2 loop-back - ds2 channel 3 see bit6 description. bit 2 - remote ds2 loop-back - ds2 channel 2 see bit6 description. bit 1 - remote ds2 loop-back - ds2 channel 1 see bit6 description. bit 0 - remote ds2 loop-back - ds2 channel 0 see bit6 description. bit7 - reserved: bit6 - generate ds2 ais re ceive path - ds2 channel 7 this read/write bit-field is used to configure the m23 de -mux block to overwrite the contents of the de-muxed ds2 data-stream (associated with ds2 channe l 7) with the ds2 ais indicator in the egress direction, towards its corresponding (down-stream) m12 de-mux block. ` 0 - the m23 de-mux block will transmit normal ds2 data to the down-stream circuitry. ` 1 - the m23 de-mux block will transmit the ds2 ais indi cator within ds2 channel 7, within the egress direction. figure 14 presents an illustration of the functional bloc k diagram of the xrt86sh3 28, whenever a given ds2 channel has been configured to transmit t he ds2 ais indicator in the egress direction. t able 246: ds3 f ramer b lock - m23 mux f orce r eceive ds2 ais c ommand r egisters (a ddress = 0 x 0e0b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved generate ds2 ais receive path - ds2 channel 7 generate ds2 ais receive path - ds2 channel 6 generate ds2 ais receive path - ds2 channel 5 generate ds2 ais receive path - ds2 channel 4 generate ds2 ais receive path - ds2 channel 3 generate ds2 ais receive path - ds2 channel 2 generate ds2 ais receive path -ds2 channel 1 r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 188 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 5 - generate ds2 ais receive path - ds2 channel 6 see bit 6 description. bit 4 - generate ds2 ais receive path - ds2 channel 5 see bit 6 description. bit 3 - generate ds2 ais receive path - ds2 channel 4 see bit 6 description. bit 2 - generate ds2 ais receive path - ds2 channel 3 see bit 6 description. bit 1 - generate ds2 ais receive path - ds2 channel 2 see bit 6 description. bit 0 - generate ds2 ais receive path - ds2 channel 1 see bit 6 description. f igure 14. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever the m23 d e -mux has been configured to transmit the ds2 ais indicator in the e gress d irection of ds2 c han - nel 0 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 ais pattern
preliminary XRT86SH328 189 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:5] - reserved bit 4 - prbs lock detect this read-only bit-field indicates whether or not the pr bs receiver (within the receive ds3 framer block) has acquired prbs lock with the payload data of the incoming ds3 data-stream, as described below. ` 0 - indicates that the prbs receiver does not ha ve prbs lock with the incoming data-stream. ` 1 - indicates that the prbs receiver does have prbs lock with the incoming data-stream. n ote : this bit-field is only valid if the prbs receiver has been enabled. bit 3 - prbs receiver enable this read/write bit-field is used to either enable or di sable the prbs receiver within the receive ds3 framer block. once the user enables the prbs receiver, then it will proce ed to attempt to acquire and maintain pattern sync (or prbs lock) within the payloadbits, within the incoming ds3 data-stream. ` 0 - disables the prbs receiver ` 1 - enables the prbs receiver. bit 2 - prbs generator enable this read/write bit-field is used to either enable or disable the prbs generator wit hin the transmit ds3 framer block. once the user enables the prbs generator block, then it will proceed to insert a prbs pattern into the payload bits, within the outbound ds3 data-stream. ` 0 - disables the prbs generator ` 1 - enables the prbs generator. bit 1 - receive ds3 framer by-pass bit 0 - transmit ds3 framer by-pass bit7 - unused bit6 - prbs type this read/write bit-field is used to select between two possible prbs patterns, that the prbs generator and receiver will be handling. ` 0 - the prbs generator and receiver will be handling a 2^15-1 prbs pattern. ` 1 - the prbs generator and receiver will be handling a 2^23-1 prbs pattern. n ote : this read/write bit-field is only active if the prbs receiver and generator have been enabled. bit[5:4] - ber control[1:0] t able 247: ds3 f ramer and m13 mux b lock - ds3 t est r egister (a ddress = 0 x 0e0c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved prbs lock detect prbs receiver enable prbs generator enable reserved r/o r/o r/o r/o r/w r/w r/o r/o 0 0 0 0 0 0 0 0 t able 248: ds3 f ramer and m13 mux b lock - ds3 t est r egister # 2 (a ddress = 0 x 0e0e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused prbs type ber control[1:0] unused unframed prbs r/o r/w r/w r/w r/o r/o r/o r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 190 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 these two read/write bit-fields are used to select the rate at which the prbs generator (within the transmit ds3 framer block) will generate and tran smit bit-errors, within th e outbound ds3/prbs data- stream. n ote : these bit-fields are only active if the prbs generator has been enabled. bit[3:1] - unused bit 0 - unframed prbs this read/write bit-field is used to configure the prbs generator an d the transmit ds3 framer block to transmit either a frame or an unframed prbs pattern, within the outbound ds3 data-stream. ` 0 - configures the prbs generator/transmit ds3 framer to transmit a framed prbs pattern, whenever the prbs generator has been enabled. ` 1 - configures the prbs generator/tran smit ds3 framer to transmit an un framed prbs pattern, whenever the prbs generator has been enabled. n ote : this bit-field is only active if the prbs generator has been enabled. bit7 - ds3 ais defect declared: this read-only bit-field indicates whether or not the rece ive ds3 framer block is currently declaring the ais defect condition, within the in coming ds3 data-stream. ` 0 - indicates that the receive ds3 framer block is no t currently declaring the ais defect condition within the incoming ds3 data-stream. ` 1 - indicates that the receive ds3 framer block is current ly declaring the ais defect condition within the incoming ds3 data-stream. bit6 - ds3 los defect declared: this read-only bit-field indicates whether or not the rece ive ds3 framer block is currently declaring the los defect condition, within the in coming ds3 data-stream. ` 0 - indicates that the receive ds3 framer block is no t currently declaring the los defect condition within the incoming ds3 data-stream. ` 1 - indicates that the receive ds3 framer block is currently declaring the los defect condition within the incoming ds3 data-stream. bit 5 - ds3 idle pattern declared: this read-only bit-field indicates whether or not the rece ive ds3 framer block is currently declaring the ds3 idle the relationship between the ber control[1:0] bit-fi elds and the resulting bit error-rate that the prbs generator will. insert within the outbound ds3/prbs data-stream ber c ontrol [1:0] r esulting b it e rror r ate inserted within the outbound ds3/prbs d ata -s tream 00, 11 no bit errors select ed (normal operation) 01 1 bit per 1000 bits are erred 10 1 bit per 1,000,000 bits are erred t able 249: ds3 f ramer b lock - r eceive ds3 c onfiguration & s tatus r egister (a ddress = 0 x 0e10) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds3 ais defect declared ds3 los defect declared ds3 idle pattern declared ds3 oof defect declared reserved framing with valid p-bits f sync algo m sync algo r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 1 0 1 0 0
preliminary XRT86SH328 191 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications pattern, within the incoming ds3 data-stream. ` 0 - indicates that the receive ds3 framer block is not currently declaring the idle pattern condition within the incoming ds3 data-stream. ` 1 - indicates that the receive ds3 framer block is currently declaring the idle pattern condition within the incoming ds3 data-stream. bit 4 - ds3 oof defect declared: this read-only bit-field indicates whether or not the rece ive ds3 framer block is currently declaring the oof (out- of-frame) defect condition. ` 0 - indicates that the receive ds3 framer block is not currently declaring t he oof defect condition. ` 1 - indicates that the receive ds3 framer block is currently declaring the oof defect condition. bit 3 - reserved: bit 2 - framing with valid p-bits: this read/write bit-field is used to configure the receive ds 3 framer block to use either of the following two different sets of ds3 frame acquis ition/maintenance criteria. ? normal framing acquisition/maintenance cr iteria (without p-bit checking) in this mode, the receive ds3 framer block will declare th e in-frame state, once it has successfully completed both the f-bit search and t he m-bit search states. ? framing acquisition/maintenance with p-bit checking: in this mode, the receive ds3 framer block will (in addit ion to passing through the f-bit search and m-bit search states) also verify valid p-bits pr ior to declaring the in-frame state. ` 0 - configures the receive ds3 framer block to use t he normal framing acquisition/maintenance criteria (without p-bit checking) ` 1 - configures the receive ds3 framer block to use the framing acquisition/maintenance with p-bit checking criteria. bit 1 - f-bit search state criteria select: this read/write bit-field is used to configure the receiv e ds3 framer block to use either one of the following ds3 out-of-frame (oof) defect declaration criteria. ` 0 - configures the receive ds3 framer block to declare the oof defect condition, whenever it determines that 6 out of the most recent 15 f-bits (withi n the incoming ds3 data-stream) are erred. ` 1 - configures the receive ds3 framer block to declare th e oof defect condition whenev er it determines that 3 out of the most recent 15 f-bits (withi n the incoming ds3 data-stream) are erred. bit 0 - m-bit search state criteria: this read/write bit-field is used to configure the receiv e ds3 framer block to use either one of the following ds3 out-of-frame (oof) defect declaration criteria. ` 0 - configures the receive ds3 framer block to not declare the oof defect condition whenever it detects m-bit errors. ` 1 - configures the receive ds3 framer block to declare th e oof defect condition whenever it detects m-bit errors within 3 out of 4 of the most recently received ds3 frames. bit7 - 5 - reserved: t able 250: ds3 f ramer b lock - r eceive ds3 s tatus r egister (a ddress = 0 x 0e11) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ds3 ferf/rdi defect declared received aic state received febe[2:0] values r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 192 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 4 - ds3 ferf/rdi defect declared: this read-only bit-field indicates whether or not the rece ive ds3 framer block is currently declaring the ferf/rdi defect condition. ` 0 - indicates that the receive ds3 framer block is not currently declaring the fe rf/rdi defect condition. ` 1 - indicates that the receive ds3 framer block is currently declaring the fe rf/rdi defect condition. bit 3 - received aic state: this read-only bit-field reflects th e current state of the ai c bit-field within the incoming ds3 data-stream. ` 0 - indicates that the receive ds3 fram er block has received at least 2 cons ecutive m-frames that have the aic bit- field set to 0. ` 1 - indicates that the receive ds3 framer block has received at least 63 consecutive m-frames that have the aic bit- field set to 1. bit[2:0] - received febe[2:0] value: these read-only bit-fields reflec ts the febe value within the mo st recently received ds3 frame. ` received febe[2:0] = [1, 1, 1] reflects a normal condition. all other values for received febe[2:0] indicates an erred condition at the remote terminal equipment. n ote : this bit-field is only active if t he transmit/receive ds3 framer blocks ha ve been configured to operate in the c-bit parity framing format. bit7 - detection of cp-bit error interrupt enable: this read/write bit-field is used to either enable or di sable the detection of cp-bit error interrupt, within the XRT86SH328. if this interrupt is enabled, then the receiv e ds3 framer block will generate an interrupt anytime it detects at least one cp-bit error within the incoming ds3 data-stream. ` 0 - disables the detection of cp-bit error interrupt. ` 1 - enables the detection of cp-bit error interrupt. n ote : this bit-field is only active if t he transmit and receive ds3 framer blocks have been configured to operate in the c-bit parity framing format. bit6 - change of ds3 los defect condition interrupt enable: this read/write bit-field is used to either enable or disabl e the change in ds3 los (loss of signal) defect condition, within the XRT86SH328. if this interrupt is enabled, then the receive ds3 framer block will generate an interrupt in response to either of the following conditions. ? the instant that the receive ds3 framer block declares the los defect condition. ? the instant that the receive ds3 framer block clears the los defect condition. ` 0 - disables the change in ds3 los defect condition interrupt. ` 1 - enables the change in ds3 los defect condition interrupt. bit 5 - change of ds3 ais def ect condition interrupt enable: this read/write bit-field is used to either enable or di sable the change in ds3 ais (alarm indication signal) defect condition interrupt within the XRT86SH328. if this interrupt is enabled, then the receive ds3 framer block will generate t able 251: ds3 f ramer b lock - r eceive ds3 i nterrupt e nable r egister (a ddress = 0 x 0e12) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 detection of cp-bit error interrupt enable change of ds3 los defect condition interrupt enable change of ds3 ais defect condition interrupt enable change of ds3 idle condition interrupt enable change of ds3 ferf/rdid efect condition interrupt enable change of aic state interrupt enable change of ds3 oof defect condition interrupt enable detection of p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 193 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications an interrupt in response to either of the following events. ? the instant that the receive ds3 framer block declares the ais defect condition. ? the instant that the receive ds3 framer block clears the ais defect condition. ` 0 - disables the change in ais defect condition interrupt. ` 1 - enables the change in ds3 ais defect condition interrupt. bit 4 - change of ds3 idle condition interrupt enable: this read/write bit-field is used to either enable or dis able the change in ds3 idle condition interrupt, within the receive ds3 framer block. if the user enables this inte rrupt then the receive ds3 framer block will generate an interrupt in response to either of the following conditions. ? the instant that the receive ds3 framer bloc k detects and declares the ds3 idle condition. ? the instant that the receive ds3 framer block clears the ds3 idle condition. ` 0 - disables the change in ds3 idle condition interrupt. ` 1 - enables the change in ds3 idle condition interrupt. bit 3 - change of ds3 ferf/rdi defect condit ion interrupt enable: this read/write bit-field is used to ei ther enable or disable the change in ds 3 ferf/rdi defect condition interrupt. if this interrupt is enabled, then the re ceive ds3 framer block will generate an interrupt in response to either of the following condition. ? the instant that the receive ds3 framer bl ock declares the ferf/rdi defect condition. ? the instant that the receive ds3 framer bl ock clears the ferf/rdi defect condition. ` 0 - disables the change in ds3 ferf/rdi defect condition interrupt. ` 1 - enables the change in ds3 ferf /rdi defect condition interrupt. bit 2 - change of aic state interrupt enable: this read/write bit-field is used to either enable or disabl e the change in aic state interr upt. if this interrupt is enabled, then the receive ds3 framer blo ck will generate an interrupt in response to it detecting a change in the aic bit-field, within the incoming ds3 data-stream. ` 0 - disables the change of aic state interrupt. ` 1 - enables the change of aic state interrupt. bit 1 - change of ds3 oof defect condition interrupt enable: this read/write bit-field is used to either enabl e or disable the change of ds3 oof defect condition interrupt. if this inte rrupt is enabled, then the receive ds3 framer block will generate an interrupt in response to either of the following conditions. ? the instant that the receive ds3 framer bl ock declares the ds3 oof defect condition. ? the instant that the receive ds3 framer block cleares the ds3 oof defect condition. ` 0 - disables the change in ds3 oof defect condition interrupt. ` 1 - enables the change in ds3 oof defect condition interrupt. bit 0 - detection of p-bit error interrupt enable: this read/write bit-field is used to either enable or disable the detection of p-bit error interrupt. if this interrupt is enabl ed, then the receive ds3 fram er block will generate an interrupt anytime it detects p-bit errors within the incoming ds3 data-stream. ` 0 - disables the detection of p-bit error interrupt ` 1 - enables the detection of p-bit error interrupt
XRT86SH328 preliminary 194 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - detection of cp-bit error interrupt status: this reset-upon-read bit-field indicates whether or not the detection of cp-bit error in terrupt has occurred since the last read of this register. ` 0 - indicates that the detection of cp-bit error interrupt has not occurred since the last read of this register. ` 1 - indicates that the detection of cp-bit error interru pt has occurred since the last read of this register. n ote : this bit-field is only active if the transmit and receive ds3 framer block are configured to operate in the c-bit parity framing format. bit6 - change of ds3 los defect condition interrupt status: this reset-upon-read bit-field indicates whether or no t the change in ds3 los defect condition interrupt has occurred since the last read of this register. ` 0 - indicates that the change in ds3 los defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in ds3 los defect condition interrupt has occurred since the last read of this register. bit 5 - change of ds3 ais def ect condition interrupt status: this reset-upon-read bit-field indicates whether or no t the change of ds3 ais defect condition interrupt has occurred since the last read of this register. ` 0 - indicates that the change of ds3 ais defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change of ds3 ais defect condition in terrupt has occurred since the last read of this register. bit 4 - change of ds3 idle condition interrupt status: this reset-upon-read bit-field indi cates whether or not th e change in ds3 idle condition interrupt has occurred since the last read of this register. ` 0 - indicates that the change of ds3 idle condition interr upt has not occurred since the last read of this register. ` 1 - indicates that the change of ds3 idle condition interr upt has occurred since the last read of this register. bit 3 - change of ds3 ferf/rdi defect condit ion interrupt status: this reset-upon-read bit-field indicates whether or not t he change of ds3 ferf/rdi defect condition interrupt has occurred since the last read of this register. ` 0 - indicates that the change of ds3 ferf/rdi defect c ondition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change in ds3 ferf/rdi defect condi tion interrupt has occurred since the last read of this register. bit 2 - change of aic state interrupt status: this reset-upon-read bit-field indicates whether or not the change in aic state interrupt has occurred since the last read of this register. ` 0 - indicates that the change in aic state interrupt ha s not occurred since the last read of this register. t able 252: ds3 f ramer b lock - r eceive ds3 i nterrupt s tatus r egister (a ddress = 0 x 0e13) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 detection of cp-bit error interrupt status change of ds3 los defect condition interrupt sta - tus change of ds3 ais defect condition interrupt sta - tus change of ds3 idle condition interrupt status change of ds3 ferf/rdid efect condition interrupt status change of aic state interrupt status change of ds3 oof defect condition interrupt status detection of p-bit error interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 195 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 1 - indicates that the change in ai c state interrupt has occurred since the last read of this register. bit 1 - change of ds3 oof defect condition interrupt status: this reset-upon-read bit-field indicates whether or no t the change in ds3 oof defect condition interrupt has occurred since the last read of this register. ` 0 - indicates that the change of ds3 oo f defect condition interrupt has not occurred since the last read of this register. ` 1 - indicates that the change of ds3 oof defect condition in terrupt has occurred since the last read of this register. bit 0 - detection of p-bit error interrupt status: this reset-upon-read bit-field indica tes whether or not the detection of p-bit error interr upt has occurred since the last read of this register. ` 0 - indicates that the detection of p- bit error interrupt has no t occurred since the last read of this register. ` 1 - indicates that the detection of p-bit error interrupt has occurred since the last read of this register. bit[7:2] - reserved: bit 1 - f-sync algorithm this read/write bit-field is used to select the f-bit ac quisition criteria when the receive ds3 framer block is operating in the f-bit search state. ` 0 - configures the receive ds3 framer block to move onto the m-bit search state, when it has properly located 10 consecutive f-bits. ` 1 - configures the receive ds3 framer block to move onto the m-bit search state, when it has properly located 16 consecutive f-bits. bit 0 - one and only: this read/write bit-field is used to select the f-bit acqui sition criteria that the receiv e ds3 framer block will use, whenever it is operating in the f-bi t search state, as described below. ` 0 - configures the receive ds3 framer block to move onto the m-bit search st ate, whenever it has properly located 10 (or 16) consecutive f-bits (as conf igured in bit 1 of this register). ` 1 - configures the receive ds3 framer block to move ont o the m-bit search state, whenever (1) it has properly located 10 (or 16) consecutive f-bits and (2) when it has located and identified only one viable f-bit alignment candidate. n ote : if this bit is set to 1, then the receive ds3 framer bl ock will not transition into the m-bit search state as long as at least two viable candidate sets of bits appears to function as the f-bits. bit7 - unused: bit[6:1] - receive feac code[5:0]: t able 253: ds3 f ramer b lock - r eceive ds3 s ync d etect r egister (a ddress = 0 x 0e14) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved f - sync algorithm one and only r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 t able 254: ds3 f ramer b lock - r eceive ds3 feac r egister (a ddress = 0 x 0e16) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused rxfeac_code[5:0] unused r/o r/o r/o r/o r/o r/o r/o r/o 0 1 1 1 1 1 1 0
XRT86SH328 preliminary 196 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 these read-only bit-fields contain the value of the most recently validated feac code word. n ote : these register bits are only active if the tran smit and receive ds3 framer blocks have been configured to operate in the c-bit parity framing format. bit 0 - unused: bits 7 - 5 - set to [0, 0, 0]: ` please set these three bit-fields to 0 (the default value) for normal operation. bit 4 - feac message valid: this read-only bit-field indicates that the feac code word (which resides within the receive ds3 feac register) has been validated by the receive feac controller block. the receive feac controller block will validate a feac codeword if it has received this same codewor d in 8 out of the last 10 feac messages. polled systems can monitor this bit-field when checking for a newly validated feac codeword. ` 0 - indicates that the feac message (residing in the receive ds3 feac register) is no longer validated. ` 1 - indicates that the feac message (residing in the receive ds3 feac register) has been validated. bit 3 - receive feac removal interrupt enable: this read/write bit-field is used to either enable or di sable the receive feac message removal interrupt. if this interrupt is enabled, then the receive ds3 framer block will generate an interrupt anytime t he most recently validated feac message has been removed. the receive feac cont roller will remove a validated feac codeword, if it has received a different codeword in 3 out of the last 10 feac messages. ` 0 - disables the receive feac message removal interrupt. ` 1 - enables the receive feac message removal interrupt. bit 2 - receive feac removal interrupt status: this reset-upon-read bit-field indicates whether or not the receive feac message removal interrupt has occurred since the last read of this register. ` 0 - indicates that the receive feac me ssage removal interrupt has not occurred since the last read of this register. ` 1 - indicates that the receive feac message removal interru pt has occurred since the last read of this register. bit 1 - receive feac valid interrupt enable: this read/write bit-field is used to either enable or disable the receive feac me ssage validation interrupt. if this interrupt is enable d, then the receive ds3 framer block will generate an interrupt anytime the receive feac controller block has validated a new feac code word. ` 0 - disables the receive feac message validation interrupt. ` 1 - enables the receive feac message validation interrupt. bit 0 - receive feac valid interrupt status: this reset-upon-read bit-field indicates whether or not the receive feac message validation interrupt has occurred since the last read of this register. ` 0 - indicates that the receive feac message validation in terrupt has not occurred since the last read of this t able 255: ds3 f ramer b lock - r eceive ds3 feac i nterrupt e nable /s tatus r egister (a ddress = 0 x 0e17) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set to [0, 0, 0] feac valid receive feac removal interrupt enable receive feac removal interrupt status receive feac valid interrupt enable receive feac valid interrupt status r/w r/w r/w r/o r/w rur r/w rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 197 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications register. ` 1 - indicates that the receive feac message validation inte rrupt has occurred since the last read of this register. bit7 - receive any kind of lapd message: this read/write bit-field is used to configure the receiv e lapd controller block to receive any kind of lapd message (or hdlc message) with a size of 82 bytes or less. if the user implements this op tion, then the receive lapd controller block will be capable of receiving any kind of hdlc message (with any value the header bytes). the only restriction is that the size of the hd lc message must not exceed 82 bytes. ` 0 - does not invoke the any ki nd of hdlc message feature. in this case, the receive lapd controller block will only receive hdlc messages that contains the bellcore gr-499- core values fo r sapi and tei. ` 1 - invokes this any kind of hdlc message feature. in this case, the receive lapd controller block will be able to receive hdlc messages that contains any header byte values. n ote : the user can determine the size (or byte count) of th e most recently received lapd/pmdl message by reading the contents of the receive lapd byte count register (address = 0x0e84). bit[6:3] - unused: bit 2 - receive lapd controller block enable: this read/write bit-field is used to either enable or di sable the receive lapd controller block within the receive ds3 framer block. if the user enables the receive lapd controller block, then it will immediately begin extracting out and monitoring the data (being carried via the dl bits) within the incoming ds3 data-stream. ` 0 - disables the receive lapd controller block. ` 1 - enables the receive lapd controller block. bit 1 - receive lapd message interrupt enable: this read/write bit-field is used to eit her enable or disable the receive lapd me ssage interrupt. if this interrupt is enabled, then the receive ds3 framer block will generate an interrupt anytime the receive lapd controller block receives a new pmdl message. ` 0 - disables the receive lapd message interrupt. ` 1 - enables the receive lapd message interrupt. bit 0 - receive lapd message interrupt status: this reset-upon-read bit-field indicates whether or not the receive lapd message interrupt ha s occurred since the last read of this register. ` 0 - indicates that the receive lapd message interrupt ha s not occurred since the last read of this register. ` 1 - indicates that the receive lapd message' interrupt has occurred since the last read of this register. t able 256: ds3 f ramer b lock - r eceive lapd c ontrol r egister (a ddress = 0 x 0e18) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive any kind of lapd message unused receive lapd controller block enable receive lapd message interrupt enable receive lapd message interrupt status r/w r/o r/o r/o r/o r/w r/w rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 198 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - unused: bit6 - receive abort: this read-only bit-field indicates that the receive lapd controller block has received an abort sequence (e.g., a string of seven consecutive 0s) within the incoming data-stream. ` 0 - indicates that the receive lapd controller block has not received an abort sequence. ` 1 - indicates that the receive lapd controller block has received an abort sequence. n ote : once the receive lapd controller block receives an abort sequence, it will set this bit-field high until it receives another lapd message. bit[5:4] - receive lapd message type[1:0]: these two read-only bit-fields indicate the type of lapd message that is residing with in the receive lapd message buffer. the relationship between the contents of these two bit-fields and the corresponding message type is presented below. bit 3 - receive c/r type: this read-only bit-field indicates the va lue of the c/r bit-field ( within one of the header byte s) of the most recently received lapd message. bit 2 - receive lapd fcs error detected: this read-only bit-field indicates whether or not the most recently received lapd message frame contained an fcs error or not. ` 0 - indicates that the most recently received lapd message frame does not contain an fcs error. ` 1 - indicates that the most recently receiv ed lapd message frame does contain an fcs error. bit 1 - end of message: this read-only bit-field indicates whether or not the re ceive lapd controller block ha s received a complete lapd message. ` 0 - indicates that the receive lapd controller block is cu rrently receiving a lapd message, but has not received the complete message. ` 1 - indicates that the receive lapd controller block has received a complete lapd message. n ote : once the receive lapd controller block sets this bit-fi eld high, this bit-field will remain high until the receive lapd controller block begins to receive a new lapd message. bit 0 - flag sequence present: t able 257: ds3 f ramer b lock - r eceive ds3 lapd s tatus r egister (a ddress = 0 x 0e19) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused receive abort rxlapd_msg_type[1:0] receive c/r type receive lapd fcs error detected end of message flag sequence present r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 message type r eceive lapd m essage t ype [1:0] m essage t ype 0 0 cl path identification 0 1 idle signal identification 1 0 test signal identification 1 1 itu-t path identification
preliminary XRT86SH328 199 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this read-only bit-field indicates whether or not the receiv e lapd controller block is currently receiving the flag sequence (e.g., a continuous stream of 0x7e octets within the data link channel). ` 0 - indicates that the receive lapd controller block is not currently receiving the flag sequence octet within the incoming data link channel. ` 1 - indicates that the receive lapd controller block is cu rrently receiving a continuous stream of flag sequence octets within the incoming data link channel. bit7, 5 - reserved bit 4 - set g.747 mode this read/write bit-field is used to configure the m1 2 mux and de-mux (associated with ds2 channel # 1) to operate in either the ds2 or the g.74 7 mode. if the user conf igures the m12 mux and de-mux to operate in the ds2 mode, then all of the following will be true. ? the m12 mux will multiplex four (4) ds1 signals into a ds2 signal, prior to routing it to the m23 mux. ? the m12 de-mux will accept a ds2 data-stream (from th e m23 de-mux) and it will de-multiplex this data- stream into four (4) ds1 signals (prior to being output to the egress direction rece ive ds1/e1 framer block). likewise, if the user configures the m12 mux and de-mux to operate in the g.747 mode, th en all of the following will be true. ? the m12 mux will multiplex three (3) e1 signals into a g.747 data-stream, prior to routing it to the m23 mux ? the m12 de-mux will accept a g.747 data-stream (from the m23 de-mux) and it will de-multiplex this data- stream into three (3) e1 signals (prior to being output to the egress direction receive ds1/e1 framer block). ` 0 - configures the m12 mux (a ssociated with ds2 channel # 1) to operate in the ds2 mode. ` 1 - configures the m12 mux (ass ociated with ds2 channel # 1) to operate in the g.747 mode. bit 3 - set g.747 reserved bit this read/write bit-field is used to configure m12 mux to set the reserved bit (within a g.747 data-stream) to either a 0 or 1. ` 0 - configures the m12 mux to set the g.747 reserv ed bit (within the outbound g.747 data-stream) to 0. ` 1 - configures the m12 mux to set the g.747 reserv ed bit (within the outbound g.747 data-stream) to 1. n ote : this bit-field is only active if the m12 mux/de-mu x has been configured to operate in the g.747 mode. bit 2 - set m12 ferf bit value bits 1, 0 - m12 loop-back code[1:0]: these read/write bit-fields are used to specify the coding (or the values that the m12 mux block will set the c-bits, within its outbound ds2 data-stream to) in order to request that the remote terminal equipment operate in the remote ds1 loop-back mode. t able 258: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 1 (a ddress = 0 x 0e1a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 200 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 n ote : anytime the m12 mux block has been configured to transmi t a ds2 loop-back request code, then it will set the c-bits to the appropriate value ( based upon the user-selection) as specified in the above table. bit [7:0] - see table 258 above, for bit descriptions, substituting channel 2 for channel 1. bit [7:0] - see table 258 above, for bit descriptions, substituting channel 3 for channel 1. bit [7:0] - see table 258 above, for bit descriptions, substituting channel 4 for channel 1. loop-back codes m12 l oop -b ack c odes [1:0] c-b it s ettings to r equest ds2 l oop - back c odes c omments 00/11 cj1 = cj2 = cj3* the m12 mux block will invert the state of the cj3 bit (from that of the corresponding cj1 and cj2 bits) within the outbound ds2 signal in order to request that the remote terminal execute a remote loop-back within the jth ds1 signal. 01 cj1 = cj2* = cj3 the m12 mux block will insert the state of the of the cj2 bit (from that of the corresponding cj1 and cj3 bits) within the outbound ds2 signal in order to request that the remote terminal execute a remote loop-back within the jth ds1 signal. 10 cj1* = cj2 = cj3 the m12 mux block will invert the state of the cj1 bit (from that of the corresponding cj2 and cj3 bits) in order to request that the remote terminal execute a remote loop-back within the jth ds1 signal. t able 259: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 2 (a ddress = 0 x 0e1b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 260: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 3 (a ddress = 0 x 0e1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 261: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 4 (a ddress = 0 x 0e1d) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 201 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - see table 258 above, for bit descriptions, substituting channel 5 for channel 1. bit [7:0] - see table 258 above, for bit descriptions, substituting channel 6 for channel 1. bit [7:0] - see table 258 above, for bit descriptions, substituting channel 7 for channel 1. bit7 - force receive ds1/e1 ais - ds1/e1 channel 4 this read/write bit-field is used to force the m12 de-mux block (associated with ds2 channel # 0) to overwrite the egress direction or de-multiplexed ds1/e1 signal associated wit h ds1/e1 channel 4, with a ds 1/e1 ais pattern as it is de-muxing this ds1/e1 signal from the incoming ds2 data-stream, as described below. ` 0 - configures the m12 de-mux block to not transmit the ds1/e1 ais pattern, via egress direction ds1/e1 channel 4. ` 1 - configures the m12 de-mux block to transmit the ds1/ e1 ais pattern, via egress direction ds1/e1 channel 4. t able 262: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 5 (a ddress = 0 x 0e1e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 263: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 6 (a ddress = 0 x 0e1f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 264: ds3 f ramer b lock - m12 c onfiguration r egister - ds2 c hannel # 7 (a ddress = 0 x 0e20) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved set g.747 mode set g.747 reserved bit m12 ferf bit setting m12 loop-back code[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 265: ds3 f ramer b lock - m12 d e -mux f orce ds1/e1 ais r egister - ds2 c hannel # 1 (a ddress = 0 x 0e21) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 4 force receive ds1/e1 ais - ds1/e1 channel 3 force receive ds1/e1 ais - ds1/e1 channel 2 force receive ds1/e1 ais - ds1/e1 channel 1 force transmit ds1/e1 ais - ds1/e1 channel 4 force transmit ds1/e1 ais - ds1/e1 channel 3 force transmit ds1/e1 ais - ds1/e1 channel 2 force transmit ds1/e1 ais - ds1/e1 channel 1 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 202 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 figure 15 presents an illustration of the functional bloc k diagram of the XRT86SH328, whenever a given m12 de-mux block has been configured to transmit the ds1/e1 ais indicator (within a given ds1/e1 signal) in the egress direction. n ote : for normal operation, the user must set this bit-field to 0. bit6 - force receive ds1/e1 ais - ds1/e1 channel 3 see description of bit7. bit 5 - force receive ds1/e1 ais - ds1/e1 channel 2 see description of bit7. bit 4 - force receive ds1/e1 ais - ds1/e1 channel 1 see description of bit7. bit 3 - force transmit ds1/e1 ais - ds1/e1 channel 4 this read/write bit-field is used to force the m12 mux block (associated with ds2 channel # 0) to overwrite the ingress direction ds1/e1 signal (associated with ds1/e1 channel 4, with a ds1/e1 ais pattern. if the user invoke this feature, then the m12 mux block will tran smit a ds1/e1 ais pattern (within ds 1/e1 channel 4) towards the m23 mux block. ` 0 - configures the m12 mux block to not transmit the ds1/e1 ais pattern, via the ingress direction ds1/e1 channel 3. ` 1 - configures the m12 mux block to transmit the ds1/e1 ais pattern, via the ingress direction ds1/e1 channel 3. n ote : for normal operation, the user must set this bit-field to 0. bit 2 - force transmit ds1/e1 ais - ds1/e1 channel 3 see description of bit 3. bit 1 - force transmit ds1/e1 ais - ds1/e1 channel 2 f igure 15. a n i llustration of the f unctional b lock diagram of the XRT86SH328, whenever a given m12 d e -mux block has been configured to transmit the ds1/e1 ais indicator ( within a given ds1/e1 signal ) in the e gress d irection sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 ds1/e1 ais in egress direction
preliminary XRT86SH328 203 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications see description of bit 3. bit 0 - force transmit ds1/e1 ais - ds1/e1 channel 1 see description of bit 3. bit [7:0] - see figure 265 above, for bit descriptions, substituting ds2 channel 1 for ds2 channel 0 and receive bit [7:0] - see figure 265 above, for bit descriptions, substituting ds2 channel 2 for ds2 channel 0 and receive bit [7:0] - see figure 265 above, for bit descriptions, substituting ds2 channel 3 for ds2 channel 0 and receive ds1/e1 ais - ds1/e1 channel [15:12] recei ve ds1/e1 ais - ds1/e1 channel [3:0]. t able 266: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 1 (a ddress = 0 x 0e22) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 7 force receive ds1/e1 ais - ds1/e1 channel 6 force receive ds1/e1 ais - ds1/e1 channel 5 force receive ds1/e1 ais - ds1/e1 channel 4 force transmit ds1/e1 ais - ds1/e1 channel 7 force transmit ds1/e1 ais - ds1/e1 channel 6 force transmit ds1/e1 ais - ds1/e1 channel 5 force transmit ds1/e1 ais - ds1/e1 channel 4 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 267: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 2 (a ddress = 0 x 0e23) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 11 force receive ds1/e1 ais - ds1/e1 channel 10 force receive ds1/e1 ais - ds1/e1 channel 9 force receive ds1/e1 ais - ds1/e1 channel 8 force transmit ds1/e1 ais - ds1/e1 channel 11 force transmit ds1/e1 ais - ds1/e1 channel 10 force transmit ds1/e1 ais - ds1/e1 channel 9 force transmit ds1/e1 ais - ds1/e1 channel 8 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 268: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 3 (a ddress = 0 x 0e24) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 15 force receive ds1/e1 ais - ds1/e1 channel 14 force receive ds1/e1 ais - ds1/e1 channel 13 force receive ds1/e1 ais - ds1/e1 channel 12 force transmit ds1/e1 ais - ds1/e1 channel 15 force transmit ds1/e1 ais - ds1/e1 channel 14 force transmit ds1/e1 ais - ds1/e1 channel 13 force transmit ds1/e1 ais - ds1/e1 channel 12 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 204 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - see figure 265 above, for bit descriptions, substituting ds2 channel 4 for ds2 channel 0 and receive ds1/e1 ais - ds1/e1 channel [19:16] recei ve ds1/e1 ais - ds1/e1 channel [3:0]. bit [7:0] - see figure 265 above, for bit descriptions, substituting ds2 channel 5 for ds2 channel 0 and receive ds1/e1 ais - ds1/e1 channel [23:20] recei ve ds1/e1 ais - ds1/e1 channel [3:0]. bit [7:0] - see figure 265 above, for bit descriptions, substituting ds2 channel 5 for ds2 channel 0 and receive ds1/e1 ais - ds1/e1 channel [27:21] recei ve ds1/e1 ais - ds1/e1 channel [3:0]. t able 269: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 4 (a ddress = 0 x 0e25) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 19 force receive ds1/e1 ais - ds1/e1 channel 18 force receive ds1/e1 ais - ds1/e1 channel 17 force receive ds1/e1 ais - ds1/e1 channel 16 force transmit ds1/e1 ais - ds1/e1 channel 19 force transmit ds1/e1 ais - ds1/e1 channel 18 force transmit ds1/e1 ais - ds1/e1 channel 17 force transmit ds1/e1 ais - ds1/e1 channel 16 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 270: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 5 (a ddress = 0 x 0e26) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 23 force receive ds1/e1 ais - ds1/e1 channel 22 force receive ds1/e1 ais - ds1/e1 channel 21 force receive ds1/e1 ais - ds1/e1 channel 20 force transmit ds1/e1 ais - ds1/e1 channel 23 force transmit ds1/e1 ais - ds1/e1 channel 22 force transmit ds1/e1 ais - ds1/e1 channel 21 force transmit ds1/e1 ais - ds1/e1 channel 20 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 271: ds3 f ramer b lock - m12 ais r egister - ds2 c hannel # 6 (a ddress = 0 x 0e27) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force receive ds1/e1 ais - ds1/e1 channel 27 force receive ds1/e1 ais - ds1/e1 channel 26 force receive ds1/e1 ais - ds1/e1 channel 25 force receive ds1/e1 ais - ds1/e1 channel 21 force transmit ds1/e1 ais - ds1/e1 channel 27 force transmit ds1/e1 ais - ds1/e1 channel 26 force transmit ds1/e1 ais - ds1/e1 channel 25 force transmit ds1/e1 ais - ds1/e1 channel 24 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 205 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 - m12 remote loop-b ack mode - ds1 channel 3 this read/write bit-field is used to configure ds1 channel 3 to operate in the m12 remote loop-back mode. if the user configures ds1 channel 3 to operate in the m12 re mote loop-back mode, then the egress direction ds1 channel 3 signal (as it is de-multiplexed from the ds2 signal by t he m12 de-mux block) will be internally looped back into the ingress direction (back towards the m12 mux block). ` 0 - configures ds1 channel 3 to not operate in the m12 remote loop-back mode (normal operation) ` 1 - configures ds1 channel 3 to operat e in the m12 remote loop-back mode. figure 16 presents an illustration of the functional block diagram of the XRT86SH328, whenever it has been configured to operate in the m12 remote loop-back mode. bit6 - m12 remote loop-b ack mode - ds1 channel 2 see description of bit7. bit 5 - m12 remote loop-b ack mode - ds1 channel 1 t able 272: ds3 f ramer b lock - m12 l oop - back r egister - 1 (a ddress = 0 x 0e28) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 3 m12 remote loop-back mode - ds1 channel 2 m12 remote loop-back mode - ds1 channel 1 m12 remote loop-back mode - ds1 channel 0 m12 loop- back request - ds1 channel 3 m12 loop- back request - ds1 channel 2 m12 loop- back request - ds1 channel 1 m12 loop- back request - ds1 channel 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 f igure 16. i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever it has been configured to operate in the m12 r emote l oop - back m ode sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 m12 remote loop-back path
XRT86SH328 preliminary 206 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 see description of bit7. bit 4 - m12 remote loop-b ack mode - ds1 channel 0 see description of bit7. bit 3 - m12 loop-back request - ds1 channel 3 this read/write bit-field is used to command the m12 mux block to transmit the loop-back request indicator for ds1 channel 3. ` 0 - the m12 mux block will not transmit the loop-back request for ds1 channel 3 (normal operation). ` 1 - the m12 mux block will transmit the loop-back request for ds1 channel 3. n ote : whenever the user executes this command, then the m12 mux blo ck (associated with ds2 channel # 0) will invert the appropriate c-bits of the three (e.g., c41, c42 or c43) within the outbound ds2 data-stream based upon the user's settings of bits 1 and 0 (m12 loop-back codes[1:0]) within the ds3 framer block - m12 configuration register - ds2 channel # 0 (address = 0x0e1a). bit 2 - m12 loop-back request - ds1 channel 2 see description of bit 3. bit 1 - m12 loop-back request - ds1 channel 1 see description of bit 3. bit 0 - m12 loop-back request - ds1 channel 0 see description of bit 3. bit [7:0] see table 272 above for bit descriptions, substitu ting channel [7:4] for channel [3:0}. bit [7:0] see table 272 above for bit description s, substituting channel [11:8] fo r channel [3:0}. t able 273: ds3 f ramer b lock - m12 l oop - back r egister - 2 (a ddress = 0 x 0e29) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 7 m12 remote loop-back mode - ds1 channel 6 m12 remote loop-back mode - ds1 channel 5 m12 remote loop-back mode - ds1 channel 4 m12 loop- back request - ds1 channel 7 m12 loop- back request - ds1 channel 6 m12 loop- back request - ds1 channel 5 m12 loop- back request - ds1 channel 4 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 274: ds3 f ramer b lock - m12 l oop - back r egister - 3 (a ddress = 0 x 0e2a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 11 m12 remote loop-back mode - ds1 channel 10 m12 remote loop-back mode - ds1 channel 9 m12 remote loop-back mode - ds1 channel 8 m12 loop- back request - ds1 channel 11 m12 loop- back request - ds1 channel 10 m12 loop- back request - ds1 channel 9 m12 loop- back request - ds1 channel 8 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 207 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] see table 272 above for bit description s, substituting channel [15:12] fo r channel [3:0}. bit [7:0] see table 272 above for bit description s, substituting channel [19:16] fo r channel [3:0}. bit [7:0] see table 272 above for bit description s, substituting channel [23:20] fo r channel [3:0}. t able 275: ds3 f ramer b lock - m12 l oop - back r egister - 4 (a ddress = 0 x 0e2b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 15 m12 remote loop-back mode - ds1 channel 14 m12 remote loop-back mode - ds1 channel 13 m12 remote loop-back mode - ds1 channel 12 m12 loop- back request ds1 channel 15 m12 loop- back request ds1 channel 14 m12 loop- back request ds1 channel 13 m12 loop- back request ds1 channel 12 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 276: ds3 f ramer b lock - m12 l oop - back r egister - 5 (a ddress = 0 x 0e2c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 19 m12 remote loop-back mode - ds1 channel 18 m12 remote loop-back mode - ds1 channel 17 m12 remote loop-back mode - ds1 channel 16 m12 loop- back request - ds1 channel 19 m12 loop- back request - ds1 channel 18 m12 loop- back request - ds1 channel 17 m12 loop- back request - ds1 channel 16 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 277: ds3 f ramer b lock - m12 l oop - back r egister - 6 (a ddress = 0 x 0e2d) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 23 m12 remote loop-back mode - ds1 channel 22 m12 remote loop-back mode - ds1 channel 21 m12 remote loop-back mode - ds1 channel 20 m12 loop- back request - ds1 channel 23 m12 loop- back request - ds1 channel 22 m12 loop- back request - ds1 channel 21 m12 loop- back request - ds1 channel 20 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 278: ds3 f ramer b lock - m12 l oop - back r egister - 7 (a ddress = 0 x 0e2e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 m12 remote loop back mode - ds1 channel 27 m12 remote loop-back mode - ds1 channel 26 m12 remote loop-back mode - ds1 channel 25 m12 remote loop-back mode - ds1 channel 24 m12 loop- back request - ds1 channel 27 m12 loop- back request - ds1 channel 26 m12 loop- back request - ds1 channel 25 m12 loop- back request - ds1 channel 24 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 208 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] see table 272 above for bit description s, substituting channel [27:24] for channel [3:0}. bit7 - force transmit ds3 ferf/rdi indicator this read/write bit-field is used to force the transmit ds3 framer block to transmit the ferf/rdi indicator to the remote terminal equipment by setting both of th e x-bits (within each outbound ds3 frame) to 0. ` 0 - does not force the transmit ds3 framer block to transmit the ds3 ferf/rdi indicator. in this case, the transmit ds3 framer block will set the x bits (within each outbound ds 3 frame) to the appropriate value, depending upon receive conditions (as detected by th e receive ds3 framer block). ` 1 - forces the transmit ds3 framer blo ck to transmit the ds3 ferf/rdi indica tor. in this case, the transmit ds3 framer block will force the x bits (wit hin each outbound ds3 frame) to 0. n ote : for normal operation (e.g., where the transmit ds3 fr amer block will automatically transmit the ferf/rdi indicator whenever the receive ds3 framer block declares either the los, ais or lof/oof defect conditions) the user must set this bit-field to 0. bit6 - force x-bits to 1 this read/write bit-field is used to force the transmit ds3 framer block to set the x-bits (within each outbound ds3 frame) to 1. ` 0 - configures the transmit ds3 framer block to automatica lly set the x bits to the appropriate value, depending upon the receive conditions (as detected by the receive ds3 framer block). ` 1 - configures the transmit ds3 framer block to force all of the x bits (within the outbou nd ds3 data-stream) to 1. in this configuration setting, the tran smit ds3 framer block will set all x bits to 1 independent of whether the receive ds3 framer block is currently declaring any defect conditions. n ote : for normal operation (e.g., where t he transmit ds3 framer block will au tomatically transmit the ferf/rdi indicator whenever the receive ds3 framer block declar es the los, ais or lof/oo f defect condition) the user must set this bit-field to 0. bit 5 - transmit ds3 idle signal this read/write bit-field is used to force the transmit ds3 framer block to transmit the ds3 idle signal pattern to the remote terminal equipment, as described below. ` 0 - configures the transmit ds3 framer block to tr ansmit normal traffic to the remote terminal equipment. ` 1 - configures the transmit ds3 framer block to transmit the ds3 idle pattern to the remote terminal equipment. n otes : 1. this bit-field is ignored if bits 3 (transmit los indicator) or 4 (transmit ais indicator) are set to 1. 2. the exact pattern that the transmit ds3 framer block will transmit (whenever this bit-field is set to 1) depends upon the contents within bits 3 through 0 (tra nsmit ds3 idle pattern[3:0]) within the ds3 framer block - transmit ds3 pattern register (address = 0x0e4c). bit 4 - transmit ais indicator this read/write bit-field is used to force the transmit ds 3 framer block to transmit the ds3 ais indicator to the remote terminal equipment as described below. ` 0 - configures the transmit ds3 fram er block to transmit normal traffic ( based upon t1/e1 data that has been multiplexed into a ds3 data-stream) to the remote terminal equipment. ` 1 - configures the transmit ds3 framer block to transmit the ds3 ais indicator to the remote terminal equipment. n otes : t able 279: ds3 f ramer b lock - t ransmit ds3 c onfiguration r egister (a ddress = 0 x 0e30) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force ds3 tx ferf/rdi force x-bits to 1 transmit ds3 idle signal transmit ais indicator transmit los indicator transmit ferf/rdi upon los transmit ferf/rdi upon lof transmit ferf/rdi upon ais r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 1 1
preliminary XRT86SH328 209 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 1. this bit-field is ignored if bit 3 (transmit los indicator) is set to 1. 2. whenever this bit-field is set to 1, the transmit ds3 framer block will either transmit a framed repeating 1, 0, 1, 0, ?. pattern, or an un framed all ones pattern, depending upon the state of bit7 (transmit ais - unframed all ones), within the transmit ds3 pattern register (address = 0x0e4c). bit 3 - transmit los indicator this read/write bit-field is used to force the transmit ds3 framer block to transmit the los pattern to the remote terminal equipment, as described below. ` 0 - configures the transmit ds3 framer block to tr ansmit normal traffic to the remote terminal equipment. ` 1 - configures the transmit ds3 framer block to transmit the los pattern (e.g., either an all zeros or all ones pattern, depending upon user configuration). n ote : whenever this bit-field is set to 1, it will transmit eith er an all zero pattern or an unframed all ones pattern, depending upon the state of bit 4 (tra nsmit los pattern - all ones pattern) within the transmit ds3 pattern register (address = 0x0e4c). bit 2 - transmit fe rf/rdi upon los this read/write bit-field is used to configure the transmit ds3 framer block to automatically transmit the ferf/rdi indicator, anytime (and for the duration that) the receiv e ds3 framer block declares the los defect condition. ` 0 - configures the transmit ds3 framer block to not automatically transmit the ferf/rdi indicator, whenever (and for the duration that) the receive ds3 framer block declares the los defect condition. ` 1 - configures the transmit ds3 framer block to automati cally transmit the ferf/rdi indicator, whenever (and for the duration that) the receive ds3 framer block declares the los defect condition. bit 1 - transmit ferf/rdi upon lof/oof: this read/write bit-field is used to configure the transmit ds3 framer block to automatically transmit the ferf/rdi indicator, anytime (and for the durati on that) the receive ds3 framer block de clares the oof defect condition, as described below. ` 0 - configures the transmit ds3 framer block to not automatically transmit the ferf/rdi indicator, whenever (and for the duration that) the receive ds3 framer block declares the oof defect condition. ` 1 - configures the transmit ds3 framer block to automa tically transmit the ferf/rdi indicator whenever (and for the duration that) the receive ds3 framer block declares the oof defect condition. bit 0 - transmit fe rf/rdi upon ais this read/write bit-field is used to configure the transmit ds3 framer block to automatically transmit the ferf/rdi indicator, anytime (and for the durati on that) the receive ds3 framer block de clares the ais defect condition, as described below. ` 0 - configures the transmit ds3 framer block to not automatically transmit the ferf/rdi indicator, whenever (and for the duration that) the receive ds3 framer block declares the ais defect condition. ` 1 - configures the transmit ds3 framer block to automati cally transmit the ferf/rdi indicator, whenever (and for the duration that) the receive ds3 framer block declares the ais defect condition. bit [7:5] - unused: please set these bits to [0, 0, 0] for normal operation. bit 4 - transmit feac interrupt enable: t able 280: ds3 f ramer b lock - t ransmit ds3 feac c onfiguration & s tatus r egister (a ddress = 0 x 0e31) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit feac interrupt enable transmit feac interrupt status transmit feac controller enable transmit feac message transmit feac busy r/o r/o r/o r/w rur r/w r/w r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 210 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this read/write bit-field is used to either enable or disable the transmit feac interrupt. if the user enables this interrupt, then the transmit feac controller block (within the transmit ds3 framer block) will generate an interrupt, once it has completed its 10th transmission of a gi ven feac message to the remote terminal equipment. ` 0 - disables the transmit feac interrupt ` 1 - enables the transmit feac interrupt. n ote : this bit-field is only active if the transmit and receive ds3 framer blo cks have been configur ed to support the c-bit parity framing format. bit 3 - transmit feac interrupt status: this reset-upon-read bit-fi eld indicates whether or not the transmit feac cont roller block has generated the transmit feac interrupt since the last read of this register. ` 0 - indicates that the transmit feac interrupt has not occurred since the last read of this register. ` 1 - indicates that the transmit feac interrupt has occurred since the last read of this register. bit 2 - transmit feac controller enable: this read/write bit-field is used to either enable or disable the transmit feac controller, within the transmit ds3 framer block. ` 0 - disables the transmit feac controller block. ` 1 - enables the transmit feac controller block bit 1 - transmit feac message: ` a 0 to 1 transition, within this bit-fiel d configures the transmit feac controller block to begin its transmission of the feac message (which consists of the feac code, as specified within the transmit ds3 feac register. n ote : the user is advised to perform a write operation that rese ts this bit-field back to 0, following execution of the command to transmit a feac message. bit 0 - transmit feac busy: this read-only bit-field indicates whether or not the tran smit feac controller block is currently busy transmitting a feac message to the remote terminal. ` 0 - indicates that the transmit feac controller is not currently busy transmitting a given feac message. ` 1 - indicates that the transmit feac controller is currently busy transmitting a given feac message to the remote terminal equipment. bit 7 - unused: bit [6:1] - txfeac_code[5:0]: these six (6) read/write bit-fields permit the user to spec ify the feac code word that the transmit feac controller block (within the transmit ds3 framer block) shou ld transmit to the re mote terminal equipment. once the user enables the transmit feac controller and co mmands it to begin its transmission, the transmit feac controller will then (1) encapsulate this six-bit code word in to a 16-bit structure, and (2) pr oceed to transmit this 16-bit structure 10 times, repeatedly, and then halt. n ote : these bit-fields are ignored if the user does not enable and use the transmit feac controller. bit 0 - unused: t able 281: ds3 f ramer b lock - t ransmit ds3 feac r egister (a ddress = 0 x 0e32) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txfeac_code[5:0] unused r/o r/w r/w r/w r/w r/w r/w r/o 0 1 1 1 1 1 1 0
preliminary XRT86SH328 211 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - transmit lapd any: this read/write bit-field is used to configure the trans mit lapd controller block to transmit any kind of lapd message (or hdlc message) with a size of 82 bytes or less. if the user implements this opt ion, then the transmit lapd controller block will be capable of transmitting any kind of hdlc frame (with any value of header bytes). the only restriction is that the size of the hdlc frame must not exceed 82 bytes. ` 0 - does not invoke this any kind of hdlc message featur e. in this case, the transmit lapd controller block will only transmit hdlc messages that contains the bellcore gr-499- core values for sapi and tei. ` 1 - invokes this any kind of hdlc message feature. in this case, the transmit lapd controller block will be able to transmit hdlc messages that contains any header byte values. n ote : if the any kind of hdlc message feature is invoked, then the size of the information payload (in terms of bytes) within the transmit lapd byte count regist er address = 0x0e83) must be indicated. bit [6:4] - unused: bit 3 - auto retransmit this read/write bit-field is used to configure the tr ansmit lapd controller block to transmit pmdl messages, repeatedly at one-second intervals. once the user enables this featur e, and then commands the transmit lapd controller block to transmit a given pmdl message, then the transmit lapd controller block will then proceed to transmit this pmdl message (based upon the contents with in the transmit lapd message buffer) repeatedly at one second intervals. ` 0 - disables the auto-retransmit feature: in this case, the transmit lapd controller block will on ly transmit a given pmdl message once. afterwards the transmit lapd controller block will proceed to transmit a co ntinuous stream of flag sequence octets (0x7e) via the dl bits, within each output ds3 frame. no more pmdl messages will be transmitted un til the user commands another transmission. ` 1 - enables the auto-retransmit features in this case, the transmit lapd controller block will tran smit pmdl messages (based upon the contents within the transmit lapd message buffer) repeatedly at one-second interval.s n ote : this bit-field is ignored if the transmit lapd controller block is disabled. bit 2 - reserved: bit 1 - transmit lapd message length: this read/write bit-field is used to specify the length of the payload data within the outbound lapd/pmdl message, as indicated below. ` 0 - configures the transmit lapd controller block to tr ansmit a lapd/pmdl message that has a payload data size of 76 bytes. ` 1 - configures the transmit lapd controller block to tr ansmit a lapd/pmdl message that has a payload data size of 82 bytes. bit 0 - transmit lapd controller enable: this read/write bit-field is used to enable the transmit lapd controller block within the chip. once the user enables the transmit lapd controller block, it will immediately begin transmitting the flag sequence octet (0x7e) to the remote terminal via the dl within the outbound ds3 data-stream. the transmit lapd cont roller block will continue to do this until the user commands the transmit lapd co ntroller block to transmit a pmdl message. ` 0 - disables the transmit lapd controller block. t able 282: ds3 f ramer b lock - t ransmit ds3 lapd c onfiguration r egister (a ddress = 0 x 0e33) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit lapd any unused auto retransmit reserved transmit lapd mes - sage length transmit lapd con - troller enable r/w r/o r/o r/o r/w r/o r/w r/w 0 0 0 0 1 0 0 0
XRT86SH328 preliminary 212 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 1 - enables the transmit lapd controller block. bit [7:4] - unused: bit 3 - transmit lapd message start: ` a 0 to 1 transition within this bit-field commands the transm it lapd controller block to begin the following activities. ? reading out the contents of the transmit lapd message buffer. ? zero-stuffing of this data ? fcs calculation and insertion ? fragmentation of this composite pmdl message, and in sertion into the dl bit-fields, within each outbound ds3 frame. bit 2 - transmit lapd controller busy: this read-only bit-field indicates whet her or not the transmit lapd controller block is currently busy transmitting a pmdl message to the remote terminal equipment. the user ca n continuously poll this bit-field in order to check for completion of transmission of the lapd/pmdl message. ` 0 - indicates that the transmit lapd controller bloc k is not currently busy tran smitting a pmdl message. ` 1 - indicates that the transmit lapd controller bl ock is currently busy tran smitting a pmdl message. bit 1 - transmit lapd message interrupt enable: this read/write bit-field is used to either enable or disabl e the transmit lapd message interrupt. if the user enables this interrupt, then the transmit ds3 framer block will gener ate an interrupt anytime the transmit lapd controller block has completed its transmission of a given l apd/pmdl message to t he remote terminal. ` 0 - disables the transmit lapd message interrupt. ` 1 - enables the transmit lapd message interrupt. bit 0 - transmit lapd message interrupt status: this reset-upon-read bit-field indicates whether or not the transmit lapd message interrupt has occurred since the last read of this register. ` 0 - indicates that the transmit lapd message interrupt has not occurred since the last read of this register. ` 1 - indicates that the transmit lapd message interrupt has occurred since the last read of this register. bits 7 - 5 - txfebedat[2:0] these read/write bit-fields, along with bit 4 (febe register enable) are used to configure the transmit ds3 framer block to transmit the user-spec ified febe values (to the remo te terminal equipment) based upon the contents of these bit-fields. t able 283: ds3 f ramer b lock - t ransmit ds3 lapd s tatus /i nterrupt r egister (a ddress = 0 x 0e34) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit lapd mes - sage start transmit lapd con - troller busy transmit lapd inter - rupt enable transmit lapd inter - rupt status r/o r/o r/o r/o r/w r/o r/w rur 0 0 0 0 0 0 0 0 t able 284: ds3 f ramer b lock - t ransmit ds3 m-b it m ask r egister (a ddress = 0 x 0e35) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txfebedat[2:0] febe regis - ter enable transmit p- bit error txm_bit_mask[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 213 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications if the user sets the febe register enable bit-field to '1, then the transmit ds3 framer block will wsrite the contents of these bit-fields into the febe bit-fi elds within each outbound ds3 frame. if the user sets the febe register enable bit-fiel d to 0, then these register bits will be ignored. bit 4 - febe register enable this read/write bit-field is used to configure the transmit ds3 framer block to transmit user-specified febe values (to the remote terminal equipment) per regi ster setting via the txfebeda t[2:0] bit-fields. this option is used to exercise software control over the outbound febe va lues, within the out bound ds3 data-stream. ` 0 - configures the transmit ds3 framer block to set the febe bit-fields ( within each outbound ds3 frame) to the appropriate values based upon receive conditions, as determined by the receive ds3 framer block. ` 1 - configures the transmit ds3 framer block to set the write the contents of the txfebedat[2:0] bi t-fields into the febe bit-positions within each outbound ds3 frame. bit 3 - transmit p-bit error this read/write bit-field is used to configure the transmi t ds3 framer block to transmit ds3 frames with erred p- bits as indicated below. ` 0 - configures the transmit ds3 framer block to generate and transmit ds3 frames (with correct p-bit values) to the remote terminal equipment. ` 1 - configures the transmit ds3 framer block to generate and transmit ds3 fr ames (with erred p-bit values) to the remote terminal equipment. bit[2:0] - txm_bit_mask[2:0] these read/write bit-fields are used to configure the transmit ds3 framer bl ock to transmit ds3 frames with erred m-bits. these three (3) bit-fields corresponding to each of the th ree m-bits, within each outbound ds3 frame. the transmit ds3 framer block will perform an xor operation with the contents of these bit-fields and the va lues of the three m-bits. the results of this calculation will be written back into the m-bit position within each outbound ds3 frame. n ote : the user should set these bit-fields to 0, 0, 0 for normal (e.g., un-erred) operation. bit[7:4] - unused bit 3 - f-bit mask[27]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 28th f-bit with in a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 28th f-bit. the results of this calculation will be written back into the 28th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 2 - f-bit mask[26]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 27th f-bit with in a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 27th f-bit. the results of this calculation will be written back into the 27th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 1 - f-bit mask[25]: t able 285: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egisters # 1 (a ddress = 0 x 0e36) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused f-bit mask[27] f-bit mask[26] f-bit mask[25] f-bit mask[24] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 214 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 26th f-bit within a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 26th f-bit. the results of this calculation will be written back into the 26th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 0 - f-bit mask[24]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 25th f-bit within a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 25th f-bit. the results of this calculation will be written back into the 25th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit7 - f-bit mask[23]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 24th f-bit within a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 24th f-bit. the results of this calculation will be written back into the 24th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit6 - f-bit mask[22]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 23rd f-bit within a given outbound ds 3 frame. the transmit ds3 framer block will perform an xor operation with the c ontents of this bit-field and the value of the 23rd f-bit. the results of this calculation will be written back into the 23rd f-bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 5 - f-bit mask[21]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 22nd f-bit within a given outbound ds 3 frame. the transmit ds3 framer block will perform an xor operation with t he contents of this bit-field and the value of the 22nd f-bit. the results of this calculation will be written back into the 22nd f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 4 - f-bit mask[20]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 21st f-bit within a given outbound ds 3 frame. the transmit ds3 framer block will perform an xor operation with the contents of this bit-fi eld and the value of the 21st f-bit. the results of this calculation will be written back into the 21st f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 3 - f-bit mask[19]: t able 286: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egister # 2 (a ddress = 0 x 0e37) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f-bit mask[23] f-bit mask[22] f-bit mask[21] f-bit mask[20] f-bit mask[19] f-bit mask[18] f-bit mask[17] f-bit mask[16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 215 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 20th f-bit with in a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 20th f-bit. the results of this calculation will be written back into the 20th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 2 - f-bit mask[18]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 19th f-bit with in a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 19th f-bit. the results of this calculation will be written back into the 19th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 1 - f-bit mask[17]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 18th f-bit with in a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 18th f-bit. the results of this calculation will be written back into the 18th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit 0 - f-bit mask[16]: this read/write bit-field is used to configure the trans mit ds3 framer block to transmit ds3 frames with a single/particular erred f-bit. this particular f-bit corresponds with the 17th f-bit with in a given outbound ds3 frame. the transmit ds3 framer block will perform an xor operation wit h the contents of this bit-field and the valu e of the 17th f-bit. the results of this calculation will be written back into the 17th f- bit position, within each outbound ds3 frame. n ote : the user should set this bit-field to 0 for normal (e.g., un-erred) operation. bit [7:0] - see table 286 above, for bit descriptions, substituting mask [15:8] for mask[23:16] bit [7:0] - see table 286 above, for bit descriptions, substituting mask [7:0] for mask[23:16] t able 287: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egister # 3 (a ddress = 0 x 0e38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f-bit mask[15] f-bit mask[14] f-bit mask[13] f-bit mask[12] f-bit mask[11] f-bit mask[10] f-bit mask[9] f-bit mask[8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 288: ds3 f ramer b lock - t ransmit ds3 f-b it m ask r egister # 4 (a ddress = 0 x 0e39) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f-bit mask[7] f-bit mask[6] f-bit mask[5] f-bit mask[4] f-bit mask[3] f-bit mask[2] f-bit mask[1] f-bit mask[0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 216 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - unused: bit 6 - one and only: this read/write bit-field is used to select the f-bit acqu isition criteria that the m12 demux block will use, whenever it is operating in the f-bit se arch state, as described below. ` 0 - configures the m12 de-mux block to move onto the m-bi t search state, whenever it has properly located 8 (or 16) consecutive f-bits (as configured in bit 4 of this register). ` 1 - configures the m12 de-mux block to move onto the m-bit search state, whenever it has (1) properly located 8 (or 16) consecutive f-bits and (2) when it has located and identified only one viable f-bit alignment candidate. n ote : if the user sets this bit-field to 1, then the m12 de-mux block will not transition into the m-bit search state as long as at least two viable candidate sets of bits appears to function as the f-bits. bit 5 - ds2 m-sync: this read/write bit-field is used to select the m-bit acquisition criteria whenever the m12 de-mux block is operating in the m-bit search state. ` 0 - configures the m12 de-mux block to declare the in-frame state, when it has properly located 4 consecutive m- bits (while detecting no f-bit errors). ` 1 - configures the m12 de-mux block to declare the in-frame state, when it has proper ly located 8 consecutive m- bits (while detecting no f-bit errors). bit 4 - ds2 f-sync: this read/write bit-field is used to select the f-bit ac quisition criteria whenever t he m12 de-mx block is operating in the f-bit search state. ` 0 - configures the m12 de-mux block to move onto the m- bit search state, when it has properly located 8 consecutive f-bits. ` 1 - configures the m12 de-mux block to move onto the m- bit search state, when it has properly located 16 consecutive f-bits. bit 3 - ds2 lof - f bits/g.747 fas bit error count the exact function of this bit-field depends upon whether the m12 mux/de-mux block has been configured to operate in the ds2 or in the g.747 mode, as described below. if m12 mux/m12 de-mux # 1 is configured to operate in the ds2 mode: this read/write bit-field is used to select the f-bit lof (loss of frame) defect criteria for the m12 de-mux associated with ds2 channel 1. ` 0 - configures the m12 de-mux block to declare the ds 2 lof defect condition whenever the m12 de-mux block detects two (2) f-bit errors within the four (4) most recently received f-bits within the incoming ds2 data-stream. ` 1 - configures the m12 de-mux block to declare the ds 2 lof defect condition whenever the m12 de-mux defect two (2) f-bit errors within the five (5) most recently received f-bits within the incoming ds2 data-stream. if m12 mux/m12 de-mux # 1 is configured to operate in the g.747 mode: this read/write bit-field is used to specify how the m1 2 de-mux increments g.747 framing alignment signal (fas) errors. the user can configure the m12 de-mux to increment the pmon ds2 # 1 framing bit error count register on either t able 289: ds3 f ramer b lock - m12 ds2 # 1 f ramer c onfiguration r egister (a ddress = 0 x 0e3a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g. 7 4 7 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 217 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications a per-bit or per-frame basis, as described below. per-bit basis: the m12 de-mux will increment the ds3 framer block - pmon ds2 # 1 framing bit error count register once for each bit-error that it detects within the fas bit-fields of the inco ming g.747 data-stream. per-frame basis: the m12 de-mux will increment the ds3 framer block - pmon ds2 # 1 framing bit error count register once for each time it detects at least one bit-error within th e fas bit-fields of a given incoming g.747 frame. ` 0 - configures the m12 de-mux to in crement the ds3 framer block - pmon ds2 # 1 framing bit error count register on a per-bit basis. ` 1 - configures the m12 de-mux block to increment the ds 3 framer block - pmon ds2 # 1 framing bit error count register on a per-frame basis. bit 2 - ds2 lof - m bits this read/write bit-field is used to select the m-bit lof (loss of frame) defect criter ia for the m12 de-mux block associated with ds2 channel 1. ` 0 - configures the m12 de-mux block to declare the ds 2 lof defect condition whenever the m12 de-mux block detects m-bit errors within three (3) out of the four (4) most recently received ds2 m-frames. ` 1 - configures the m12 de-mux block to declares the ds 2 lof defect condition whenever the m12 de-mux block detects m-bit errors within two (2) out of the four (4) most recently received ds2 m-frames. bit 1 - ds2 lof - m bits disable this read/write bit-field is used to configure the m12 de-m ux block to not use m-bit errors as a reason/criteria for declaring the ds2 lo f defect condition. ` 0 - configures the m12 de-mux block to declare the ds 2 lof defect condition, base d upon the number of m-bit errors (as selected in bit 2 within this register). ` 1 - configures the m12 de-mux block to not declare the ds2 lof defect condition, based upon the occurrences of any m-bit errors. bit 0 - ds2 reframe: ` a 0 to 1 transition, within this bit-field commands the m1 2 de-mux block to exit the frame maintenance mode, and go back and enter the frame acquisition mode. n ote : the user should go back and set this bit-field to 0 following execution of the reframe command. bit [7:0] - see bit description for table 289 , above. t able 290: ds3 f ramer b lock - m12 ds2 # 2 f ramer c onfiguration r egister (a ddress = 0 x 0e3b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g.747 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 218 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - see bi t description for table 289 , above. bit [7:0] - see bi t description for table 289 , above. bit [7:0] - see bi t description for table 289 , above. t able 291: ds3 f ramer b lock - m12 ds2 # 3 f ramer c onfiguration r egister (a ddress = 0 x 0e3c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g.747 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 292: ds3 f ramer b lock - m12 ds2 # 4 f ramer c onfiguration r egister (a ddress = 0 x 0e3d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g.747 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 293: ds3 f ramer b lock - m12 ds2 # 5 f ramer c onfiguration r egister (a ddress = 0 x 0e3e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g.747 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 219 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - see bit description for table 289 , above. bit [7:0] - see bit description for table 289 , above. bit7 - transmit ais - unframed all ones: this read/write bit-field is used to configure the transmi t ds3 framer block to transmit either of the following patterns, anytime it is configured to transmit the ais indicator. ? a framed, repeating 1, 0, 1, 0? patt ern (per bellcore gr-499-core) or ? an unframed all ones pattern. ` 0 - configures the transmit ds3 framer block to transmit th e framed, repeating 1, 0, 1, 0,? pattern, whenever it is configured to transmit the ais indicator. ` 1 - configures the transmit ds3 framer block to transmit an unframed, all ones pattern, whenever it is configured to transmit the ais indicator. bit6 - transmit ais - c bits not forced to 0 t able 294: ds3 f ramer b lock - m12 ds2 # 6 f ramer c onfiguration r egister (a ddress = 0 x 0e3f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g.747 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 295: ds3 f ramer b lock - m12 ds2 # 7 f ramer c onfiguration r egister (a ddress = 0 x 0e40) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused one and only ds2 m-sync ds2 f-sync ds2 lof - f bits/ g.747 fas bit error count ds2 lof - m bits ds2 lof - m bits disable ds2 reframe r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 296: ds3 f ramer b lock - t ransmit ds3 p attern r egister (a ddress = 0 x 0e4c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit ais - unframed all ones transmit ais - c bits not forced to 0 transmit ais - ignore overhead data from txds3oh port transmit los pattern - all ones pattern ds3 idle pattern[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 1 1 0 0
XRT86SH328 preliminary 220 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this read/write bit-field (along with the tr ansmit ais - unframed all ones bit-field) is used to define the type of ais data-stream that the transm it ds3 framer block will transmit, as described below. ` 0 - configures the transmit ds3 framer bl ock to force all of the c bits to 0 when it is configured to transmit a framed ais signal. ` 1 - configures the transmit ds3 framer block to not force all of the c bits to 0 when it is configured to transmit a framed ais signal. in this case, the c bits can be used to transport feac or pmdl messages. n ote : this bit-field is ignored if the tr ansmit ds3 framer block has been conf igured to transmit an unframed - all ones type of ais signal. bit 5 - transmit ais - ignore overhead data from txds3oh port this read/write bit-field permits the transmit ds3 framer block to either accept or ignore externally supplied ds3 overhead data, whenever it (the transmit ds3 fr amer block) is transmitting the ais indicator. if this feature is used , then (for the duration that the transmit ds3 framer block is commanded to transmit the ds3 ais indicator) the transmit ds3 framer block will not allow the us ers to externally insert their ds3 oh bits within the outbound ds3 data-stream, even if the txoh source bit-field is set to 1 and if the corresponding f-bit mask bit-field is set to 0. conversely, if the user does not use th is feature, then the transm it ds3 framer block will allow the users to externally insert theirr own ds3 oh bits (within the outbound ds3 dat a-stream) even when the transmit ds3 framer block is transmitting the ds3 ais indicator to the remote terminal equipment. ` 0 - does not invoke the ignore txds3oh port during ais feature ` 1 - invokes the ignore the txds 3oh port during ais feature. bit 4 - transmit los pattern select: this read/write bit-field is used to c onfigure the transmit ds3 framer block to transmit either an all zeros or an all ones pattern, anytime it is configured to transmit the lo s pattern to the remote terminal equipment, as described below. ` 0 - configures the transmit ds3 framer block to transmit an all zeros pattern whenever it is configured to transmit the los pattern. ` 1 - configures the transmit ds3 framer block to transmit an all ones pattern w henever it is configured to transmit the los pattern. bit[3:0] - transmit ds3 idle pattern[3:0] these read/write bit-fields are used to specify the type of fram ed, repetitive four-bit patt ern that the transmit des3 framer block should generate and transmit, whenever it is configured to transmit the ds3 idle pattern. n ote : setting these bit-fields to [1, 1, 0, 0] configures the transmit ds3 framer blo ck to transmit the standard framed, repeating 1, 1, 0, 0, ? pattern (per bellcore gr-499-core) requirements. bits 7 - 5 - unused bit 4 - auto ds1/e1 ai s upon ds3 los defect this read/write bit-field is used to configure all of the egress directio n transmit ds1/e1 framer blocks (within the XRT86SH328) to automatically transmit the ds1/e1 ais indica tor via the downstream ds1/e1 signals, anytime (and for the duration that) the receive ds3 framer block declares the los defect condition. ` 0 - does not configure all egress direction transmit ds1/e1 framer blocks to automatical ly transmit the ds1/e1 ais indicators via the downstream ds1/e1 signals, anytime the receive ds3 framer block declares the los defect t able 297: ds3 f ramer b lock - a uto t1/e1 ais upon ds3 d efect c ondition r egister (a ddress = 0 x 0e4d) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused auto ds1/e1ais upon ds3 los defect unused auto ds1/e1 ais upon ds3 oof defect unused auto ds1/e1 ais upon ds3 ais defect r/o r/o r/o r/w r/o r/w r/o r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 221 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications condition. ` 1 - configures all egress direction tr ansmit ds1/e1 framer blocks to auto matically transmit the ds1/e1 ais indicators via the downstream ds1/e1 signals anytim e the receive ds3 framer block declares the los defect condition. n ote : this bit-field is only active if the XRT86SH328 has been configured to operate in either the m13 mux or the m13 mux which is asynchronously mapped into sts-1/sts-3 mode. bit 3 - unused bit 2 - auto ds1/e1 ais upon ds3 oof defect this read/write bit-fiel d is used to configure all of the egress direct ion transmit ds1/e1 framer blocks (within the XRT86SH328) to automatically transmit the ds1/e1 ais indica tor via the downstream ds1/e1 signals, anytime (and for the duration that) the receive ds3 framer bl ock declares the lof/oof defect condition. ` 0 - does not configure all egress direction transmit ds1/e1 framer blocks to automatical ly transmit the ds1/e1 ais indicators via the downstream ds1/e1 signals, anytime t he receive ds3 framer block de clares the lof/oof defect condition. ` 1 - configures all egress direction tr ansmit ds1/e1 framer blocks to auto matically transmit the ds1/e1 ais indicators via the downstream ds1/e1 signals anytime the receive ds3 framer block declares the lof/oof defect condition. n ote : this bit-field is only active if the XRT86SH328 has been configured to operate in either the m13 mux or the m13 mux which is asynchronously mapped into sts-1/sts-3 mode. bit 1 - unused bit 0 - auto ds1/e1 ais upon ds3 ais defect this read/write bit-fiel d is used to configure all of the egress direct ion transmit ds1/e1 framer blocks (within the XRT86SH328) to automatically transmit the ds1/e1 ais indica tor via the downstream ds1/e1 signals, anytime (and for the duration that) the receive ds3 framer block declares the ais defect condition. ` 0 - does not configure all egress direction transmit ds1/e1 framer blocks to automatical ly transmit the ds1/e1 ais indicators via the downstream ds1/e1 signals, anytime the receive ds3 framer blo ck declares the ais defect condition. ` 1 - configures all egress direction tr ansmit ds1/e1 framer blocks to auto matically transmit the ds1/e1 ais indicators via the downstream ds1/e1 signals anytime the receive ds3 framer block declares the ais defect condition. n ote : this bit-field is only active if the XRT86SH328 has been configured to operate in either the m13 mux or the m13 mux which is asynchronously mapped into sts-1/sts-3 mode. bit [7:0] - pmon exz _event_count[15:8]: these reset-upon-read bits, along with that within the pmon excessive zero c ount register - lsb combine to reflect the cumulative number of instances in which the rece ive ds3 framer block has dete cted a string of three or more consecutive zeros within the incoming ds3 dat a-stream, since the last read of this register. this register contains the most signif icant byte of this 16-bit expression. t able 298: ds3 f ramer b lock - pmon e xcessive z ero (exz) e vent c ount r egister - msb (a ddress = 0 x 0e4e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon exz even t count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 222 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - pmon exz _event_count[7:0]: these reset-upon-read bits, along with t hat within the pmon excessive zero count register -msb combine to reflect the cumulative number of instances in which the rece ive ds3 framer block has dete cted a string of three or more consecutive zeros within the incoming ds3 dat a-stream, since the last read of this register. this register contains the least signif icant byte of this 16-bit expression. bit [7:0] - pmon lc v_event_count[15:8]: these reset-upon-read bits along with that within the pmon line code violation count - lsb register combine to reflect the cumulative number of line code violation events that the receive ds3 framer block has detected within the incoming ds3 data-stream, since the last read of this register. this register contains the most sign ificant byte of this 16-bit expression. bit [7:0] - pmon lcv_event_count[7:0]: these reset-upon-read bits along with that within the pm on line code violation count - msb register combine to reflect the cumulative number of line code violation events that the receive ds3 framer block has detected within the incoming ds3 data-stream, since the last read of this register. this register contains the least sign ificant byte of this 16-bit expression. t able 299: ds3 f ramer b lock - pmon e xcessive z ero (exz) e vent c ount r egister - lsb (a ddress = 0 x 0e4f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon exz event count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 300: ds3 f ramer b lock - pmon l ine c ode v iolation (lcv) e vent c ount r egister - msb (a ddress = 0 x 0e50) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon lcv event count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 301: ds3 f ramer b lock - pmon l ine c ode v iolation (lcv) e vent c ount r egister - lsb (a ddress = 0 x 0e51) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon lcv event count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 302: ds3 f ramer b lock - pmon f raming b it e rror c ount r egister - msb (a ddress = 0 x 0e52) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_framing_bit_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 223 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0]: pmon framin g bit errorcount[15:8]: these reset-upon-read bits, along with that within the ds3 framer block - pm on framing bit error count register - lsb combine to reflect the cumulative number of framing bit errors that the receive ds3 framer block has detected since the last read of this re gister. this register contains the most significant byte of this 16-bit expression. n ote : the receive ds3 framer block will increment this register each time that it detects f or m bit errors within the incoming ds3 data-stream. bit [7:0]: pmon framin g bit errorcount[7:0]: these reset-upon-read bits, along with that within the ds3 framer block - pm on framing bit error count register - msb combine to reflect the cumulative number of framing bit errors that the receive ds3 framer block has detected since the last read of this re gister. this register contai ns the least significant byte of this 16-bit expression. n ote : the receive ds3 framer block will increment this register each time that it detects f or m bit errors within the incoming ds3 data-stream. bit [7:0]: pmon p-bi t error count[15:8]: these reset-upon-read bits, al ong with that within the ds3 framer block - pmon p-bit error count register - lsb combine to reflect the cumulative number of p-bit errors that the receive ds3 framer block has detected within the incoming ds3 data-stream, since the last read of this register. this register contains the most significant byte of this 16-bit expression. bit [7:0] - pmon p-bit error count[7:0]: these reset-upon-read bits, al ong with that within the ds3 framer block - pmon p-bit error co unt register - msb combine to reflect the cumulative number of p-bit errors that the receive ds3 framer block has detected within the incoming ds3 data-stream, since the last read of this register. this register cont ains the least significant byte of this 16-bit expression. t able 303: ds3 f ramer b lock - pmon f raming b it e rror c ount r egister - lsb (a ddress = 0 x 0e53) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_framing_bit_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 304: ds3 f ramer b lock - pmon p-b it e rror c ount r egister - msb (a ddress = 0 x 0e54) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_p_bit _error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 305: ds3 f ramer b lock - pmon p-b it e rror c ount r egister - lsb (a ddress = 0 x 0e55) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_p_bit_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 224 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - pmon febe event count[15:8]: these reset-upon-read bits, along with that within the pm on febe event count register - lsb combine to reflect the cumulative number of febe/rei events that the receive ds3 fram er block has detected within the in coming ds3 data-stream, since the last read of this register. this regist er contains the most significant byte of this 16-expression. bit [7:0] - pmon febe event count[7:0]: these reset-upon-read bits, along with that within the pm on febe event count register - msb combine to reflect the cumulative number of febe/rei events that the receive ds3 fram er block has detected within the in coming ds3 data-stream, since the last read of this register. this register contains the leas t significant byte of this 16-expression. bit [7:0] - pmon cp-bit error count[15:8]: these reset-upon-read bits, along with that within the ds3 framer block - pmon cp-bit error count register - lsb combine to reflect the cumulative number of cp bit errors that the receive ds3 framer block has detected since the last read of this register. this register contains the most significant byte of this 16-bit expression. n ote : these register bits are not active if the transmit and receive ds3 framer blocks have not been configured to support the ds3 c-bit parity framing format. bit [7:0] - pmon cp-bit error count[7:0]: these reset-upon-read bits, al ong with that within the ds3 framer block - pmon cp-bit error count register - msb combine to reflect the cumulative number of cp bit erro rs that the receive ds3 framer block has detected since the last read of this register. this register contains the least significant byte of this 16-bit expression. t able 306: ds3 f ramer b lock - pmon febe e vent c ount r egister - msb (a ddress = 0 x 0e56) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_febe_even t_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 307: ds3 f ramer b lock - pmon febe e vent c ount r egister - lsb (a ddress = 0 x 0e57) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_febe_event _count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 308: ds3 f ramer b lock - cp-b it e rror c ount r egister - msb (a ddress = 0 x 0e58) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_cp_bit_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 309: ds3 f ramer b lock - cp-b it e rror c ount r egister - lsb (a ddress = 0 x 0e59) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_cp_bit_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 225 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : these register bits are not active if the transmit a nd receive ds3 framer blocks have not been configured to support the ds3 c-bit parity framing format. bit [7:0] - pmon ds2 # 1 - framing bit error count[7:0]/g.747 fas error count[7:0]: the function of this bit-field depends upon whether m12 mux/de-mux # 1 has bee n configured to operate in the ds2 or in the g.747 mode. if m12 mux/de-mux # 1 has been configured to operate in the ds2 mode: these reset-upon-read bi t-fields reflects the cumulative number of f and m bit errors that the m12 de-mux block (associated with ds2 channel 1) has detected since the last read of this register. if m21 mux/de-mux # 1 has been configured to operate in the g.747 mode: this reset-upon-read bit-fields reflects the cumula tive number of fas errors that the m12 de-mux block (associated with ds2 channel 1) has detect ed since the last read of this register. bit [7:0] see figure 310 above, for bi t descriptions bit [7:0] see figure 310 above, for bi t descriptions bit [7:0] see figure 310 above for bit descriptions t able 310: ds3 f ramer b lock - pmon ds2 # 1 f raming b it e rror c ount r egister (a ddress = 0 x 0e5a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 1 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 311: ds3 f ramer b lock - pmon ds2 # 2 f raming b it e rror c ount r egister (a ddress = 0 x 0e5b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 2 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 312: ds3 f ramer b lock - pmon ds2 # 3 f raming b it e rror c ount r egister (a ddress = 0 x 0e5c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 3 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 313: ds3 f ramer b lock - pmon ds2 # 4 f raming b it e rror c ount r egister (a ddress = 0 x 0e5d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 4 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 226 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] see figure 310 above, for bi t descriptions bit [7:0] see figure 310 above, for bi t descriptions bit [7:0] see figure 310 above for bit descriptions bit [7:0] - pmon g.747 # 1 - parity error count[7:0]: this reset-upon-read bit-field reflects the cumulative number of p-bit errors that the m12 de-mux block (associated with g.747 channel # 1) has detected since the last read of this register. n ote : these bit-fields are only active if m12 mux/de-mux # 1 has been configured to operate in the g.747 mode. bit [7:0] - see table 317 above, for bit descrptions, substituting channel # 2 for channel # 1. t able 314: ds3 f ramer b lock - pmon ds2 # 5 f raming b it e rror c ount r egister (a ddress = 0 x 0e5e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 5 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 315: ds3 f ramer b lock - pmon ds2 # 6 f raming b it e rror c ount r egister (a ddress = 0 x 0e5f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 6 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 316: ds3 f ramer b lock - pmon ds2 # 7 f raming b it e rror c ount r egister (a ddress = 0 x 0e60) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_ds2 # 7 framing bit error count[7:0]/g.747 fas error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 317: ds3 f ramer b lock - pmon g.747 # 1 p arity b it e rror c ount r egister (a ddress = 0 x 0e61) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 1 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 318: ds3 f ramer b lock - pmon g.747 # 2 p arity b it e rror c ount r egister (a ddress = 0 x 0e62) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 2 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 227 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - see table 317 above, for bit descrptions, substituting channel # 3 for channel # 1. bit [7:0] - see table 317 above, for bit descrptions, substituting channel # 4 for channel # 1. bit [7:0] - see table 317 above, for bit descrptions, substituting channel # 5 for channel # 1. bit [7:0] - see table 317 above, for bit descrptions, substituting channel # 6 for channel # 1. bit [7:0] - see table 317 above, for bit descrptions, substituting channel # 7 for channel # 1. t able 319: ds3 f ramer b lock - pmon g.747 # 3 p arity b it e rror c ount r egister (a ddress = 0 x 0e63) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 3 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 320: ds3 f ramer b lock - pmon g.747 # 4 p arity b it e rror c ount r egister (a ddress = 0 x 0e64) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 4 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 321: ds3 f ramer b lock - pmon g.747 # 5 p arity b it e rror c ount r egister (a ddress = 0 x 0e65) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 5 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 322: ds3 f ramer b lock - pmon g.747 # 6 p arity b it e rror c ount r egister (a ddress = 0 x 0e66) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 6 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 323: ds3 f ramer b lock - pmon g.747 # 7 p arity b it e rror c ount r egister (a ddress = 0 x 0e67) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_g.747 # 7 - parity error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 228 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - prbs error count - upper byte: these reset-upon-read bits, along with t hat within the ds3 framer block - pr bs bit error count register - lsb combine to reflect the cumulative number of prbs bit errors that the prbs receiver (within the receive ds3 framer block) has detected since the last read of this register. this regist er contains the most signifi cant byte of this 16-bit expression. n ote : this register is only active of the prbs receiver (within the receive ds3 fram er block) has been enabled. bit [7:0] - prbs error count - lower byte: these reset-upon-read bits, along with t hat within the ds3 framer block - pr bs bit error count register - msb combine to reflect the cumulative number of prbs bit errors that the prbs receiver (within the receive ds3 framer block) has detected since the last read of this register. this regist er contains the least signif icant byte of this 16-bit expression. n ote : this register is only active of the prbs receiver (within the receive ds3 fram er block) has been enabled. bit [7:2] - unused: bit 1 - erred second: this read-only bit-field indicates whether or not the re ceive ds3 framer block has declared the last one-second accumulation period as an erred second. the receive ds3 framer block will declare an erred second if it detects any of the following events, within a given one- second period. ? p-bit errors ? cp-bit errors ? framing bit (f or m) errors ` 0 - indicates that the receive ds3 framer block has not de clared the last one-second accumulation period as being an erred second. t able 324: ds3 f ramer b lock - prbs b it e rror c ount r egister - msb (a ddress = 0 x 0e68) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 prbs error count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 325: ds3 f ramer b lock - prbs b it e rror c ount r egister - lsb (a ddress = 0 x 0e69) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 prbs error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 326: ds3 f ramer b lock - o ne s econd e rror s tatus r egister (a ddress = 0 x 0e6d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused erred second severely erred second r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 229 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 1 - indicates that the receive ds3 framer block has declar ed the last one-second accumulation period as being an erred second. bit 0 - severely erred second: this read-only bit-field indicates whether or not th e receive ds3 framer block has declared the last one- second accumulation period as being a severely erred second. the receive ds3 framer block will declare s a given one-second period as bei ng a severely erre d second if it determines that the ber (bit error rate) during this one-second accumulation period is greater than 10-3 errors/second. ` 0 - indicates that the receive ds3 framer block has not de clared the last one-second accumulation period as being a severely-erred second. ` 1 - indicates that the receive ds3 framer block has declar ed the last one-second accumulation period as being a severely-erred second. bit [7:0] - one-second lcv accumulation count[15:8]: these read-only bits, along with that within the ds3 framer block - one se cond lcv accumulation count register - msb combine to reflect the cumulative number of line code violations that the receive ds3 framer block has detected within the incoming ds3 data-strea m, during the last one-second accumula tion period. this register contains the most significant byte of this 16-bit expression. n ote : this register is only active if the XRT86SH328 has been configured to operate in the m13 mux mode. bit [7:0] - one-second lc v accumulation count[7:0]: these read-only bits, along with that within the ds3 framer block - one se cond lcv accumulation count register - lsb combine to reflect the cumulative number of line code violations that the receive ds3 framer block has detected within the incoming ds3 data-strea m, during the last one-second accumula tion period. this register contains the least significant byte of this 16-bit expression. n ote : this register is only active if the XRT86SH328 has been configured to operate in the m13 mux mode. bit [7:0] - one-second p-bit er ror accumulation count[15:8]: t able 327: ds3 f ramer b lock - lcv o ne s econd a ccumulator r egister - msb (a ddress = 0 x 0e6e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_lcv_accum_count[15:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 328: ds3 f ramer b lock - lcv o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 0e6f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_lcv_accum_count[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 329: ds3 f ramer b lock - p-b it e rror o ne s econd a ccumulator r egister - msb (a ddress = 0 x 0e70) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_p_bit_error_accum_count[15:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 230 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 these read-only bits, along with that within the ds3 fr amer block - one second p-bit error accumulation count register - lsb combine to reflect the cumulative number of p-bit errors that the receive ds3 framer block has detected within the incoming ds3 data-stream, during the last one-seco nd accumulation period. this register contains the most significant byte of this 16-bit expression. bit [7:0] - one-second p-bit error accumulation count[7:0]: these read-only bits, along with that within the ds3 fr amer block - one second p-bit error accumulation count register - msb combine to reflect the cumulative number of p-bit errors t hat the receive ds3 framer block has detected within the incoming ds3 data-strea m, during the last one-second accumula tion period. this register contains the least significant byte of this 16-bit expression. bit [7:0] - one-second cp-bit error accumulation count[15:8]: these read-only bits, along with that within the ds3 framer block - one second cp-bit error accumulation count register - lsb combine to reflect the cumulative number of cp-bit errors that the receive ds3 framer block has detected within the incoming ds3 data-strea m, during the last one-second accumula tion period. this register contains the most significant byte of this 16-bit expression. n ote : this register is only active if the transmit and receiv e ds3 framer blocks have been configured to operate in the ds3, c-bit parity framing format. bit [7:0] - one-second cp-bit error accumulati on count[7:0]: these read-only bits, along with that within the ds3 framer block - one second cp-bit error accumulation count register - msb combine to reflect the cumulative number of cp-bit errors that the receive ds3 framer block has detected within the incoming ds3 data-strea m, during the last one-second accumula tion period. this register contains the least significant byte of this 16-bit expression. n ote : this register is only active if the transmit and receiv e ds3 framer blocks have been configured to operate in the ds3, c-bit parity framing format. t able 330: ds3 f ramer b lock - p-b it e rror o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 0e71) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_p_bit_error_accum_count[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 331: ds3 f ramer b lock - cp-b it e rror o ne s econd a ccumulator r egister - msb (a ddress = 0 x 0e72) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_cp_bit_erro r_accum_count[15:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 332: ds3 f ramer b lock - cp-b it e rror o ne s econd a ccumulator r egister - lsb (a ddress = 0 x 0e73) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_cp_bit_error_accum_count[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 231 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - transmit lapd message size[7:0]: these read/write bit-fields permit the user to specify t he size of the information payload (in terms of bytes) within the very next outbound lapd/pmdl message whenever bit 7 (transmit lapd any) within the ds3 framer block - transmit lapd configuration register has been set to 1. bit [7:0] - receive lapd message size[7:0]: these read-only bit-fields indicate the size of the most recently received lapd/pmdl message, whenever bit 7 (receive lapd any) within the ds3 framer block - receive lapd control register has been set to 1. the contents of this register reflect the rece ive lapd message size, in terns of bytes. bit7 - reserved: bit6 - change of ds2 loop-back requ est - ds2 channel 6 interrupt enable: this read/write bit-field is used to either enable or disable the change of ds2 loop-back request interrupt associated with ds2 channel 6. if th is interrupt is enabled, then the xr t86sh328 will generate an interrupt in response to either of the following events. ? whenever the receive ds3 framer block detects and flags the ds2 loop-back request for ds2 channel 6. ? whenever the receive ds3 framer block clears the ds2 loop-back request for ds2 channel 6. ` 0 - disables the change of ds2 loop-back request interrupt for ds2 channel 6. ` 1 - enables the change of ds2 loop-back request interrupt for ds2 channel 6. bit 5 - change of ds2 loop-back request - ds2 channel 5 interrupt enable: t able 333: ds3 f ramer b lock - t ransmit lapd b yte c ount r egister (a ddress = 0 x 0e83) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tx_lapd_message_size[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 334: ds3 f ramer b lock - r eceive lapd b yte c ount r egister (a ddress = 0 x 0e84) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rx_lapd_message_size[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 335: ds3 f ramer b lock - r eceive ds2 l oop -b ack r equest i nterrupt e nable r egister (a ddress = 0 x 0e90) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved change of ds2 loop- back request - ds2 channel 6 interrupt enable change of ds2 loop- back request - ds2 channel 5 interrupt enable change of ds2 loop- back request - ds2 channel 4 interrupt enable change of ds2 loop- back request - ds2 channel 3 interrupt enable change of ds2 loop- back request - ds2 channel 2 interrupt enable change of ds2 loop- back request - ds2 channel 1 interrupt enable change of ds2 loop- back request - ds2 channel 0 interrupt enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 232 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 see description of bit6. bit 4 - change of ds2 loop-back request - ds2 channel 4 interrupt enable see description of bit6. bit 3 - change of ds2 loop-back request - ds2 channel 3 interrupt enable see description of bit6. bit 2 - change of ds2 loop-back request - ds2 channel 2 interrupt enable see description of bit6. bit 1 - change of ds2 loop-back request - ds2 channel 1 interrupt enable see description of bit6. bit 0 - change of ds2 loop-back request - ds2 channel 0 interrupt enable see description of bit6. bit7 - reserved: bit6 - change of ds2 loop-back requ est - ds2 channel 6 interrupt status: this reset-upon-read bit-field indicates whether or not the change of ds2 loop-back request status interrupt for ds2 channel 6 has occurred since the last read of this register. the XRT86SH328 will generate this interrupt in response to either of the following conditions. ? whenever the receive ds3 framer block detects and fl ags the ds2 loop-back request, for ds2 channel 6. ? whenever the receive ds3 framer block clears the ds2 loop-back request for ds2 channel 6. ` 0 - indicates that the change of ds2 loop-back request stat us interrupt has not occurred since the last read of this register ` 1 - indicates that the change of ds2 loop-back request stat us interrupt has occurred since the last read of this register. bit 5 - change of ds2 loop-back request - ds2 channel 5 interrupt status see description of bit6. bit 4 - change of ds2 loop-back request - ds2 channel 4 interrupt status see description of bit6. bit 3 - change of ds2 loop-back request - ds2 channel 3 interrupt status see description of bit6. bit 2 - change of ds2 loop-back request - ds2 channel 2 interrupt status see description of bit6. bit 1 - change of ds2 loop-back request - ds2 channel 1 interrupt status see description of bit6. t able 336: ds3 f ramer b lock - r eceive ds2 l oop -b ack r equest i nterrupt s tatus r egister (a ddress = 0 x 0e91) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved change of ds2 loop- back request - ds2 channel 6 interrupt status change of ds2 loop- back request - ds2 channel 5 interrupt status change of ds2 loop- back request - ds2 channel 4 interrupt status change of ds2 loop- back request - ds2 channel 3 interrupt status change of ds2 loop- back request - ds2 channel 2 interrupt status change of ds2 loop- back request - ds2 channel 1 interrupt status change of ds2 loop- back request - ds2 channel 0 interrupt status r/o rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 233 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 0 - change of ds2 loop-back request - ds2 channel 0 interrupt status see description of bit6. bit7 - reserved: bit6 - receive ds2 loop-back request on - ds2 channel 6: this read-only bit-field indicates whether or not th e receive ds3 framer block has detected a ds2 loop-back request (associated with ds2 channel # 6) within the in coming ds3 data-stream. the re ceive ds3 framer block will detect and flag a ds2 loop-back request if it detects the ds2 loop-back codes (pertaining to a given ds2 channel) for 5 consecutive ds3 frames. ` 0 - indicates that the receive ds3 framer block is not currently flagging a ds2 loop-back request associated with ds2 channel 6. ` 1 - indicates that the receive ds2 fr amer block is currently flagging a ds2 loop-back request associated with ds2 channel 6. bit 5 - receive ds2 loop-back request on - ds2 channel 5 see description of bit6. bit 4 - receive ds2 loop-back request on - ds2 channel 4 see description of bit6. bit 3 - receive ds2 loop-back request on - ds2 channel 3 see description of bit6. bit 2 - receive ds2 loop-back request on - ds2 channel 2 see description of bit6. bit 1 - receive ds2 loop-back request on - ds2 channel 1 see description of bit6. bit 0 - receive ds2 loop-back request on - ds2 channel 0 see description of bit6. t able 337: ds3 f ramer b lock - r eceive ds2 l oop - back r equest s tatus r egister (a ddress = 0 x 0e92) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved receive ds2 loop-back request on - ds2 channel 6 receive ds2 loop-back request on - ds2 channel 5 receive ds2 loop-back request on - ds2 channel 4 receive ds2 loop-back request on - ds2 channel 3 receive ds2 loop-back request on - ds2 channel 2 receive ds2 loop-back request on - ds2 channel 1 receive ds2 loop-back request on - ds2 channel 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 234 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - change of m12 loop-back request condition - ds1 channel 3 interrupt status this reset-upon-read bit-field indicates whether or no t the m12 de-mux block (associated with ds2 channel 0) has generated the change of m12 loop-back request condition inte rrupt, for ds1 channel 3, since the last read of this register. the m12 de-mux block will generate this particular interrupt in response to either of the following events. ? ? whenever it detects the m12 loop-back request indicator for ds1 channel 3 (within the incoming ds2 signal) ? whenever it ceases to detect the m12 loop-back request indicator for ds1 channel 3 (within the incoming ds2 signal). ` 0 - indicates that the change of m12 loop-back request condition interrupt, for ds1 channel 3, has not occurred since the last read of this register. ` 1 - indicates that the change of m12 loop-back request c ondition interrupt, for ds1 channel 3, has occurred since the last read of this register. bit6 - change of m12 loop-back request condition - ds1 channel 2 interrupt status see description of bit7. bit 5 - change of m12 loop-back request condition - ds1 channel 1 interrupt status see description of bit7. bit 4 - change of m12 loop-back request condition - ds1 channel 0 interrupt status see description of bit7. bit 3 - change of m12 loop-back request condition - ds1 channel 3 interrupt enable this read/write bit-field is used to either ena ble or disable the change of m12 loop-back request condition interrupt for ds1 channel 3. if this interrupt is enabled, then the xr t86sh328 will generate an interrupt in response to either of the following conditions. ? whenever the m12 de-mux block (associated with ds2 channel 0) detects the m12 loop-back request indicator for ds1 channel 3 (within the incoming ds2 signal). ? whenever the m12 de-mux block ceases to detect the m12 loop-back request indicator for ds1 channel 3 (within the incoming ds2 signal). ` 0 - disables the change of m12 loop-back request condition interrupt for ds1 channel 3. ` 1 - enables the change of m12 loop-back request condition interrupt for ds1 channel 3. bit 2 - change of m12 loop-back request condition - ds1 channel 2 interrupt enable see description of bit 3. bit 1 - change of m12 loop-back request condition - ds1 channel 1 interrupt enable see description of bit 3. t able 338: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 1 (a ddress = 0 x 0e93) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 3 interrupt status change of m12 loop- back request condition - ds1 channel 2 interrupt status change of m12 loop- back request condition - ds1 channel 1 interrupt status change of m12 loop- back request condition - ds1 channel 0 interrupt status change of m12 loop- back request condition - ds1 channel 3 interrupt enable change of m12 loop- back request condition - ds1 channel 2 interrupt enable change of m12 loop- back request condition - ds1 channel 1 interrupt enable change of m12 loop- back request condition - ds1 channel 0 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 235 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 0 - change of m12 loop-back request condition - ds1 channel 0 interrupt enable see description of bit 3. bit7 - 4 - reserved: bit 3 - m12 loop-back reques t status - ds1 channel 3: this read/write bit-field indicates whether or not th e m12 de-mux block (associated with ds2 channel 0) is currently detecting the m12 loop-back request for ds 1 channel 3, within the incoming ds2 data-stream. ` 0 - indicates that the m12 de-mux block (associated with ds2 channel 0) is not currently detecting the m12 loop- back request for ds1 channel 3, wi thin the incoming ds2 data-stream. ` 1 - indicates that the m12 de-mux block (associated with ds2 channel 0) is currently detecting the m12 loop-back request for ds1 channel 3, within the incoming ds2 data-stream. bit 2 - m12 loop-back reques t status - ds1 channel 2: see description of bit 3. bit 1 - m12 loop-back reques t status - ds1 channel 1: see description of bit 3. bit 0 - m12 loop-back reques t status - ds1 channel 0: see description of bit 3. see table 338 above for bit descriptions, substituting channel [7:4] for channel [3:0]. t able 339: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 1 (a ddress = 0 x 0e94) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request status - ds1 channel 3 m12 loop- back request status - ds1 channel 2 m12 loop- back request status - ds1 channel 1 m12 loop- back request status - ds1 channel 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 340: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 2 (a ddress = 0 x 0e95) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 7 interrupt sta - tus change of m12 loop- back request condition - ds1 channel 6 interrupt sta - tus change of m12 loop- back request condition - ds1 channel 5 interrupt sta - tus change of m12 loop- back request condition - ds1 channel 4 interrupt sta - tus change of m12 loop- back request condition - ds1 channel 7 interrupt enable change of m12 loop- back request condition - ds1 channel 6 interrupt enable change of m12 loop- back request condition - ds1 channel 5 interrupt enable change of m12 loop- back request condition - ds1 channel 4 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 236 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - see table 339 above, for bit descriptions, substituting channel [7:4] for channel [3:0]. see table 338 above for bit descriptions, substituting channel [11:8] for channel [3:0]. bit [7:0] - see table 339 above, for bit descriptions, substituting channel [11:8] for channel [3:0]. t able 341: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 2 (a ddress = 0 x 0e96) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request status - ds1 channel 7 m12 loop- back request status - ds1 channel 6 m12 loop- back request status - ds1 channel 5 m12 loop- back request status - ds1 channel 4 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 342: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 3 (a ddress = 0 x 0e97) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 11 interrupt status change of m12 loop- back request condition - ds1 channel 10 interrupt status change of m12 loop- back request condition - ds1 channel 9 interrupt status change of m12 loop- back request condition - ds1 channel 8 interrupt status change of m12 loop- back request condition - ds1 channel 11 interrupt enable change of m12 loop- back request condition - ds1 channel 10 interrupt enable change of m12 loop- back request condition - ds1 channel 9 interrupt enable change of m12 loop- back request condition - ds1 channel 8 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 343: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 3 (a ddress = 0 x 0e98) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request status - ds1 channel 11 m12 loop- back request status - ds1 channel 10 m12 loop- back request status - ds1 channel 9 m12 loop- back request status - ds1 channel 8 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 237 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications see table 338 above for bit descriptions, substituting channel [15:12] for channel [3:0]. bit [7:0] - see table 339 above, for bit descriptions, substituting channel [15:12] for channel [3:0]. see table 338 above for bit descriptions, substituting channel [19:16] for channel [3:0]. t able 344: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 4 (a ddress = 0 x 0e99) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 15 interrupt status change of m12 loop- back request condition - ds1 channel 14 interrupt status change of m12 loop- back request condition - ds1 channel 13 interrupt status change of m12 loop- back request condition - ds1 channel 12 interrupt status change of m12 loop- back request condition - ds1 channel 15 interrupt enable change of m12 loop- back request condition - ds1 channel 14 interrupt enable change of m12 loop- back request condition - ds1 channel 13 interrupt enable change of m12 loop- back request condition - ds1 channel 12 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 345: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 4 (a ddress = 0 x 0e9a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request sta - tus - ds1 channel 15 m12 loop- back request sta - tus - ds1 channel 14 m12 loop- back request sta - tus - ds1 channel 13 m12 loop- back request sta - tus - ds1 channel 12 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 346: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 5 (a ddress = 0 x 0e9b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 19 interrupt status change of m12 loop- back request condition - ds1 channel 18 interrupt status change of m12 loop- back request condition - ds1 channel 17 interrupt status change of m12 loop- back request condition - ds1 channel 16 interrupt status change of m12 loop- back request condition - ds1 channel 19 interrupt enable change of m12 loop- back request condition - ds1 channel 18 interrupt enable change of m12 loop- back request condition - ds1 channel 17 interrupt enable change of m12 loop- back request condition - ds1 channel 16 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 238 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - bit - see table 339 above, for bit description s, substituting channel [19:16] fo r channel [3:0]. see table 338 above for bit descriptions, substituti ng channel [23:20] for channel [3:0]. bit [7:0] - see table 339 above, for bit descriptions, substitu ting channel [23:20] for channel [3:0]. t able 347: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 5 (a ddress = 0 x 0e9c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request status - ds1 channel 19 m12 loop- back request status - ds1 channel 18 m12 loop- back request status - ds1 channel 17 m12 loop- back request status - ds1 channel 16 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 348: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 6 (a ddress = 0 x 0e9d) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 23 interrupt status change of m12 loop- back request condition - ds1 channel 22 interrupt status change of m12 loop- back request condition - ds1 channel 21 interrupt status change of m12 loop- back request condition - ds1 channel 20 interrupt status change of m12 loop- back request condition - ds1 channel 23 interrupt enable change of m12 loop- back request condition - ds1 channel 22 interrupt enable change of m12 loop- back request condition - ds1 channel 21 interrupt enable change of m12 loop- back request condition - ds1 channel 20 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 349: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 6 (a ddress = 0 x 0e9e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request sta - tus - ds1 channel 23 m12 loop- back request sta - tus - ds1 channel 22 m12 loop- back request sta - tus - ds1 channel 21 m12 loop- back request sta - tus - ds1 channel 20 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 239 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications see table 338 above for bit descriptions, substituting channel [27:24] for channel [3:0]. bit [7:0] - see table 339 above, for bit descriptions, substituting channel [27:24] for channel [3:0]. bit [7:6] - unused: bit 5 - ds2 cofa (change of framing alignment) interrupt enable: this read/write bit-field is used to either enable or di sable the ds2 change of framin g alignment interrupt for ds2 channel # 1. if the user enables this interrupt, then t he m12 de-mux block will generate an interrupt anytime it has detected a change in ds2 framing alignment within the incoming ds2 data-stream. ` 0 - disables the ds2 cofa interrupt for ds2 channel 1. ` 1 - enables the ds2 cofa interrupt for ds2 channel 1. t able 350: ds3 f ramer b lock - m12 l oop - back i nterrupt s tatus /e nable r egister - 7 (a ddress = 0 x 0e9f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 change of m12 loop- back request condition - ds1 channel 27 interrupt status change of m12 loop- back request condition - ds1 channel 26 interrupt status change of m12 loop- back request condition - ds1 channel 25 interrupt status change of m12 loop- back request condition - ds1 channel 24 interrupt status change of m12 loop- back request condition - ds1 channel 27 interrupt enable change of m12 loop- back request condition - ds1 channel 26 interrupt enable change of m12 loop- back request condition - ds1 channel 25 interrupt enable change of m12 loop- back request condition - ds1 channel 24 interrupt enable rur rur rur rur r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 351: ds3 f ramer b lock - m12 l oop - back s tatus r egisters - 7 (a ddress = 0 x 0ea0) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m12 loop- back request sta - tus - ds1 channel 27 m12 loop- back request sta - tus - ds1 channel 26 m12 loop- back request sta - tus - ds1 channel 25 m12 loop- back request sta - tus - ds1 channel 24 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 352: ds3 f ramer b lock - ds2 # 1 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ea1) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect condition interrupt enable change of ds2 ferf/rdi defect condition interrupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect condition interrupt enable change of state of reserved bit (g.747) interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 240 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 4 - change of ds2 lof def ect condition interrupt enable: this read/write bit-field is used to either enable or di sable the change of ds2 lof defect condition interrupt for ds2 channel 1. if the user enables this interrupt, then th e m12 de-mux block will generate an interrupt in response to either of the following conditions. ? whenever the m12 de-mux block declares the ds2 lof defect condition, or ? whenever the m12 de-mux block clear s the ds2 lof defect condition. ` 0 - disables the change of ds2 lof defect condition interrupt for ds2 channel 1. ` 1 - enables the change of ds2 lof defe ct condition interrupt for ds2 channel 1. bit 3 - change of ds2 ferf/rdi defect condit ion interrupt enable: this read/write bit-field is used to either enable or disa ble the change of ds2 ferf/rdi defect condition interrupt for ds2 channel 1. if the user enables this interrupt, t hen the m12 de-mux block will generate an interrupt in response to either of the following conditions. ? whenever the m12 de-mux block declares the ds2 ferf/rdi defect condition, or ? whenever the m12 de-mux block clears the ds2 ferf/rdi defect condition. ` 0 - disables the change of ds2 ferf/rdi de fect condition interrupt for ds2 channel 1. ` 1 - enables the change of ds2 ferf/rdi de fect condition interrupt for ds2 channel 1. bit 2 - change of ds2 red alarm defect condit ion interrupt enable: this read/write bit-field is used to either enable or di sable the change of ds2 red alarm defect condition interrupt for ds2 channel 1. if the user enables this interrupt, t hen the m12 de-mux block will generate an interrupt in response to either of the following conditions. ? whenever the m12 de-mux block declares the ds2 red alarm defect condition, or ? whenever the m12 de-mux block clears the ds2 red alarm defect condition. ` 0 - disables the change of ds2 red alarm defect condition interrupt for ds2 channel 1. ` 1 - enables the change of ds2 red alarm defect condition interrupt for ds2 channel 1. bit 1 - change of ds2 ais def ect condition interrupt enable: this read/write bit-field is used to either enable or di sable the change of ds2 ais defect condition interrupt for ds2 channel 1. if the user enables this interrupt, then th e m12 de-mux block will generate an interrupt in response to either of the following conditions. ? whenever the m12 de-mux block declares the ds2 ais defect condition, or ? whenever the m12 de-mux block clears the ds2 ais defect condition. ` 0 - disables the change of ds2 ais defect condition interrupt for ds2 channel 1. ` 1 - enables the change of ds2 ais defect condition interrupt for ds2 channel 1. bit 0 - change of state of reserved bit (g.747) interrupt enable: this read/write bit-field is used to either enable or disa ble the change of state of the g.747 reserved bit interrupt. if the user enables this inte rrupt, then the m12 de-mux block will generate an interrupt anytime it detects a change of state in the reserved bit within the g.747 da ta stream associated with g.747 channel # 1. ` 0 - disables the change of state of the g.747 reserved bit interrupt for m12 de-mux block channel 1. ` 1 - enables the change of state of the g.747 reserved bit interrupt for m12 de-mux block channel 1. n ote : this bit-field is only active if m12 de-mux block # 1 has been configured to operate in the g.747 mode.
preliminary XRT86SH328 241 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:6] - unused: bit 5 - ds2 cofa interrupt status: this reset-upon-read bit-field indicates whether or not the ds2 cofa interrupt (associated with m12 de-mux # 1) has occurred since the last read of this register. ` 0 - indicates that the ds2 cofa inte rrupt (associated with m12 de-mux # 1) has not occurred since the last read of this register. ` 1 - indicates that the ds2 cofa interrupt (associated with m12 de-mux # 1) has occurred since the last read of this register. bit 4 - change of ds2 lof defect condition interrupt status: this reset-upon-read bit-filed indicates whether or no t the change of ds2 lof defect condition interrupt has occurred (within m12 de-mux # 1) since the last read of this register. ` 0 - indicates that the change of ds2 lof defect conditi on interrupt (associated with m12 de-mux # 1) has not occurred since the last read of this register. ` 1 - indicates that the change of ds2 lof defect conditi on interrupt (associated with m12 de-mux # 1) has occurred since the last read of this register. bit 3 - change of ds2 ferf/rdi defect condit ion interrupt status: this reset-upon-read bit-filed indicate s whether or not the chan ge of ds2 ferf/rdi defect condition interrupt has occurred (within m12 de-mux # 1) since the last read of this register. ` 0 - indicates that the change of ds2 ferf/rdi defect condition interrupt (associated with m12 de-mux # 1) has not occurred since the last read of this register. ` 1 - indicates that the change of ds2 ferf/rdi defect condition interrupt (associated with m12 de-mux # 1) has occurred since the last read of this register. bit 2 - change of ds2 red alarm defect condition interrupt status: this reset-upon-read bit-filed indicates whether or not the change of ds2 red alarm defect condition interrupt has occurred (within m12 de-mux # 1) since the last read of this register. ` 0 - indicates that the change of ds2 red alarm defect condition interrupt (associated with m12 de-mux # 1) has not occurred since the last read of this register. ` 1 - indicates that the change of ds2 red alarm defect condition interrupt (associated with m12 de-mux # 1) has occurred since the last read of this register. bit 1 - change of ds2 ais def ect condition interrupt status: this reset-upon-read bit-filed indicates whether or no t the change of ds2 ais defect condition interrupt has occurred (within m12 de-mux # 1) since the last read of this register. ` 0 - indicates that the change of ds2 ais defect conditi on interrupt (associated with m12 de-mux # 1) has not occurred since the last read of this register. ` 1 - indicates that the change of ds2 ais defect conditi on interrupt (associated with m12 de-mux # 1) has occurred since the last read of this register. bit 0 - change of state of reserved bit (g.747) interrupt status: t able 353: ds3 f ramer b lock - ds2 # 1 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0ea2) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt status change of ds2 red alarm defect condition interrupt status change of ds2 ais defect con - dition interrupt status change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 242 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this reset-upon-read bit-field indicates whether or not the change of state of the g.747 reserved bit interrupt has occurred (within m12 de-mux # 1) since the last read of this register. ` 0 - indicates that the change of stat e of the g.747 reserved bit interrupt (a ssociated with m12 de-mux # 1) has not occurred since the last read of this register. ` 1 - indicates that the change of stat e of the g.747 reserved bit interrupt (a ssociated with m12 de-mux # 1) has occurred since the last read of this register. n ote : this bit-field is only active if m12 de-mux block # 1 has been configured to operate in the g.747 mode. bit [7:5] - unused: bit 4 - ds2 lof defect declared: this read-only bit-field indicates whether or not m12 de -mux block # 1 is currently declaring the ds2 lof defect condition. ` 0 - indicates that m12 de-mux block # 1 is not currently declaring the ds2 lof defect condition. ` 1 - indicates that m12 de-mux block # 1 is currently declaring the ds2 lof defect condition. bit 3 - ds2 ferf/rdi defect declared: this read-only bit-field indicates whether or not m12 de -mux block # 1 is currently declaring the ds2 ferf/rdi defect condition. ` 0 - indicates that m12 de-mux block # 1 is not curre ntly declaring the ds2 ferf/rdi defect condition. ` 1 - indicates that m12 de-mux block # 1 is currently declaring the ds2 ferf/rdi defect condition. bit 2 - ds2 red alarm defect declared: this read-only bit-field indicates whether or not m12 de -mux block # 1 is currently declaring the ds2 red alarm defect condition. ` 0 - indicates that m12 de-mux block # 1 is not currently declaring the ds2 red alarm defect condition. ` 1 - indicates that m12 de-mux block # 1 is currently declaring the ds2 red alarm defect condition. bit 1 - ds2 ais defect declared: this read-only bit-field indicates whether or not m12 de -mux block # 1 is currently declaring the ds2 ais defect condition. ` 0 - indicates that m12 de-mux block # 1 is not cu rrently declaring the ds2 ais defect condition. ` 1 - indicates that m12 de-mux block # 1 is currently declaring the ds2 ais defect condition. bit 0 - current state of reserved bit (g.747): this read-only bit-field reflects the current state of the g.747 reserve bit, as relieved by m12 de-mux block # 1. t able 354: ds3 f ramer b lock - ds2 # 1 f ramer s tatus r egister (a ddress = 0 x 0ea3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 243 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - for bit descriptions see table 352 above, substituting channel 2 for channel 1 and de-mux #2 for de- mux #1. bit [7:0] - for bi t descriptions see table 353 above, substituting de-mux #2 for de-mux #1. bit [7:0] - for bi t descriptions see table 354 above, substituting de-mux #2 for de-mux #1. t able 355: ds3 f ramer b lock - ds2 # 2 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ea4) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect condition interrupt enable change of ds2 ferf/rdi defect condition interrupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect condition interrupt enable change of state of reserved bit (g.747) interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 356: ds3 f ramer b lock - ds2 # 2 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0ea5) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt status change of ds2 red alarm defect condition interrupt status change of ds2 ais defect condition interrupt sta - tus change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 357: ds3 f ramer b lock - ds2 # 2 f ramer s tatus r egister (a ddress = 0 x 0ea6) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 244 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - for bit descriptions see table 352 above, substituting channel 3 for channel 1 and de-mux #3 for de- mux #1. bit [7:0] - for bit descriptions see table 353 above, substituting de-mux #3 for de-mux #1. bit [7:0] - for bit descriptions see table 354 above, substituting de-mux #3 for de-mux #1. t able 358: ds3 f ramer b lock - ds2 # 3 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ea7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect con - dition inter - rupt enable change of ds2 ferf/rdi defect con - dition inter - rupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect con - dition inter - rupt enable change of state of reserved bit (g.747) inter - rupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 359: ds3 f ramer b lock - ds2 # 3 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0ea8) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt status change of ds2 red alarm defect condition interrupt status change of ds2 ais defect condition interrupt sta - tus change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 360: ds3 f ramer b lock - ds2 # 3 f ramer s tatus r egister (a ddress = 0 x 0ea9) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 245 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - for bit descriptions see table 352 above, substituting channel 4 for channel 1 and de-mux #4 for de- mux #1. bit [7:0] - for bi t descriptions see table 353 above substituting de -mux #4 for de-mux #1. bit [7:0] - for bi t descriptions see table 354 above, substituting de-mux #4 for de-mux #1. t able 361: ds3 f ramer b lock - ds2 # 4 f ramer i nterrupt e nable r egister (a ddress = 0 x 0eaa) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect condition interrupt enable change of ds2 ferf/rdi defect condition interrupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect condition interrupt enable change of state of reserved bit (g.747) interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 362: ds3 f ramer b lock - ds2 # 4 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eab) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt status change of ds2 red alarm defect condition interrupt status change of ds2 ais defect condition interrupt status change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 363: ds3 f ramer b lock - ds2 # 4 f ramer s tatus r egister (a ddress = 0 x 0eac) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 246 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - for bit descriptions see table 352 above, substituting channel 5 for channel 1 and de-mux #5 for de- mux #1. bit [7:0] - for bit descriptions see table 353 above substituting de -mux #5 for de-mux #1. bit [7:0] - for bit descriptions see table 354 above, substituting de-mux #5 for de-mux #1. t able 364: ds3 f ramer b lock - ds2 # 5 f ramer i nterrupt e nable r egister (a ddress = 0 x 0ead) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect condition interrupt enable change of ds2 ferf/rdi defect condition interrupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect condition interrupt enable change of state of reserved bit (g.747) interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 365: ds3 f ramer b lock - ds2 # 5 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eae) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt status change of ds2 red alarm defect condition interrupt status change of ds2 ais defect con - dition interrupt status change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 366: ds3 f ramer b lock - ds2 # 5 f ramer s tatus r egister (a ddress = 0 x 0eaf) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 247 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - for bit descriptions see table 352 above, substituting channel 2 for channel 6 and de-mux #6 for de- mux #1. bit [7:0] - for bi t descriptions see table 353 above substituting de -mux #6 for de-mux #1. bit [7:0] - for bi t descriptions see table 354 above, substituting de-mux #6 for de-mux #1. t able 367: ds3 f ramer b lock - ds2 # 6 f ramer i nterrupt e nable r egister (a ddress = 0 x 0eb0) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect condition interrupt enable change of ds2 ferf/rdi defect condition interrupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect condition interrupt enable change of state of reserved bit (g.747) interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 368: ds3 f ramer b lock - ds2 # 6 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eb1) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt status change of ds2 red alarm defect condition interrupt status change of ds2 ais defect con - dition interrupt status change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 369: ds3 f ramer b lock - ds2 # 6 f ramer s tatus r egister (a ddress = 0 x 0eb2) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 248 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - for bit descriptions see table 352 above, substituting channel 7 for channel 1 and de-mux #7 for de- mux #1. bit [7:0] - for bit descriptions see table 353 above, substituting de-mux #7 for de-mux #1. bit [7:0] - for bit descriptions see table 354 above, substituting de-mux #7 for de-mux #1. t able 370: ds3 f ramer b lock - ds2 # 7 f ramer i nterrupt e nable r egister (a ddress = 0 x 0eb3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt enable change of ds2 lof defect condition interrupt enable change of ds2 ferf/rdi defect condition interrupt enable change of ds2 red alarm defect condition interrupt enable change of ds2 ais defect condition interrupt enable change of state of reserved bit (g.747) interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 371: ds3 f ramer b lock - ds2 # 7 f ramer i nterrupt s tatus r egister (a ddress = 0 x 0eb4) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 cofa interrupt status change of ds2 lof defect condition interrupt status change of ds2 ferf/rdi defect condition interrupt sta - tus change of ds2 red alarm defect condition interrupt status change of ds2 ais defect condition interrupt status change of state of reserved bit (g.747) interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 372: ds3 f ramer b lock - ds2 # 7 f ramer s tatus r egister (a ddress = 0 x 0eb5) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds2 lof defect declared ds2 ferf/rdi defect declared ds2 red alarm defect declared ds2 ais defect declared current state of reserved bit (g.747) r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 249 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:4] - unused: bit 3 - auto ds1/e1 ai s upon ds2 lof defect: this read/write bit-field is used to configure all of the egress direction transmit ds1/e1 framer blocks (associated with a given m12 de-mux block) to automat ically transmit the ds1/e1 ais indicato r via each of its three or four down- stream ds1/e1 signals, anytime (and for the duration t hat) the corresponding m12 de-mux block declares the ds2 lof defect condition. ` 0 - does not configure each of the m12 de-mux blocks to force all of its corresponding egress direction transmit ds1/e1 framer blocks (within the xrt86s h328) to automatically transmit the ds 1/e1 ais indicator via its downstream ds1/e1 signals, anytime (and for the duration that) the m12 de-mux block de clares the ds2 lof defect condition. ` 1 - configures each of the m12 de-mux blocks to force al l of its corresponding egress direction transmit ds1/e1 framer blocks (within the XRT86SH328) to automatically transmit the ds1/e1 ai s indicator via its downstream ds1/e1 signals, anytime (and for the duration that) the m12 de-mux block declares t he ds2 lof defect condition. n ote : this bit-setting applies to eac h of the seven (7) m12 de-mux blocks within the XRT86SH328. bit 2 - unused: bit 1 - auto ds1/e1 ais upon ds2 ais defect: this read/write bit-field is used to configure all of the egress direction transmit ds1/e1 framer blocks (associated with a given m12 de-mux block) to automat ically transmit the ds1/e1 ais indicato r via each of its three or four down- stream ds1/e1 signals, anytime (and for the duration th at) the corresponding m12 de-mux block declares the ds2 ais defect condition. ` 0 - does not configure each of the m12 de-mux blocks to force all of its corresponding egress direction transmit ds1/e1 framer blocks (within the xrt86s h328) to automatically transmit the ds 1/e1 ais indicator via its downstream ds1/e1 signals, anytime (and for the duration that) the m12 de-mux block de clares the ds2 ais defect condition. ` 1 - configures each of the m12 de-mux blocks to force al l of its corresponding egress direction transmit ds1/e1 framer blocks (within the XRT86SH328) to automatically transmit the ds1/e1 ai s indicator via its downstream ds1/e1 signals, anytime (and for the duration that) the m12 de-mux block declares the ds2 ais defect condition. n ote : this bit-setting applies to each of the seven (7) m12 de-mux blocks within the XRT86SH328328. bit 0 - unused: 2.12 t1/e1 liu channel control registers ? (n ranges from 0x01 to 0x1c) bit7 - prbs/qrss: these bits are used to select between qrss and prbs. to send the a qrss or prbs pattern, the txtest[2:0] bits in register 0xn002h must be programmed. t able 373: ds3 f ramer b lock - m13 d e -mux r egister (a ddress = 0 x 0eb8) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused auto ds1/e1 ais upon ds2 oof defect unused auto ds1/e1 ais upon ds2 ais defect unused r/o r/o r/o r/o r/w r/o r/w r/o 0 0 0 0 0 0 0 0 t able 374: liu c hannel c ontrol r egister 0 (a ddress = 0 x n000) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prbs/qrss prbs_rx_tx rxon eqc[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 250 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 0 = qrss ` 1 = prbs bit6 - prbs/qrss direction select rx/tx: this bit is used to select which direction is used to se nd the prbs/qrss pattern if enabled within the txtest[2:0] bits in register 0xn002h. ` 0 = line interface (ttip/tring) ` 1 = system side interface (clock/data) bit 5 - rxon receiver enable: this bit is used enable the receiver line interface. by default, the receivers are turned off to support redundancy. ` 0 = disabled. ` 1 = enabled. bit [4:0] - equalizer control and line build out: these bits are used to select the equalizer control and line build out. bit7 - rxtsel: this bit is used for the receive line interface to select bet ween internal (automatic line impedance) and external (high impedance) modes. ` 0 = external impedance ` 1 = internal impedance bit6 - txtsel: this bit is used for the transmit line interface to select be tween internal (automatic line impedance) and external (high impedance) modes. ` 0 = external impedance ` 1 = internal impedance bit [5:4] - tersel[1:0]: selection chart for equalizer control and line build-out eqc[4:0] t1/e1 m ode r eceive s ensitivity t ransmit lbo c able c oding 01000 t1 short haul 0 - 133 ft (0.6db) 100w tp b8zs 01001 t1 short haul 0 - 133 ft (0.6db) 100w tp b8zs 01010 t1 short haul 0 - 133 ft (0.6db) 100w tp b8zs 01011 t1 short haul 0 - 133 ft (0.6db) 100w tp b8zs 01100 t1 short haul 0 - 133 ft (0.6db) 100w tp b8zs 01101 t1 short haul arbitrary pulse 100w tp b8zs 11100 e1 short haul itu g.703 75w coax hdb3 11101 e1 short haul itu g.703 120w tp hdb3 t able 375: liu c hannel c ontrol r egister 0 (a ddress = 0 x n001) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxtsel txtsel tersel[1:0] jasel[1:0] jabw fifos r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 251 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications these bits are used to select the line impedance for internal termination control. ` 00 = 100w ` 01 = 110w ` 10 = 75w ` 11 = 120w bit [3:2] - jasel[1:0]: these bits are used to select which path the jitter attenuator is placed. ` 00 = disabled. ` 01 = transmit line interface path ` 10 = receive line interface path ` 11 = receive line interface path ` bit 1 - jitter attenuator band width: the jitter band width is a global setting that is applied in both transmit and receive directions. ` 0 = 10 hz ` 1 = 1.5 hz bit 0 - first in first out bit depth: this bit is used for the transmit line interface to select be tween internal (automatic line impedance) and external (high impedance) modes. ` 0 = 32-bit ` 1 = 64-bit bit7 - invert qrss: invqrss is used to invert the transmit qrss pattern set by the txtest[2:0] bits. by default, invqrss is disabled and the qrss will be transmitted with normal polarity. ` 0 = external impedance ` 1 = internal impedance bit [6:4] - tx test pattern [2:0]: these bits are used to select a test patter n to be sent to the transmit line interfac e. if bit 6 in register 0xn000h is set high, then the test pattern will be sent out on the receive ds-1/e1 system side. ` 0xx = no test pattern ` 100 = tx qrss ` 101 = tx taos ` 110 = reserved ` 111 = reserved bit 3 - txon transmitter enable: this bit is used enable the transmitter line interface. by default, the transmitters are turned off to support redundancy. ` 0 = disabled. ` 1 = enabled. bit [2:0] - loop back mode select [2:0]: t able 376: liu c hannel c ontrol r egister 0 (a ddress = 0 x n002) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 invqrss txtest[2:0] txon loop[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 252 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 these bits are used to select a loop back mode for diagnostic testing. these bits only represent the loop back modes supported in the liu section of voyager. for other loop ba ck mode options, see the register map in other modes of operation. ` 0xx = no loop back ` 100 = dual loop back ` 101 = analog loop back ` 110 = remote loop back ` 111 = digital loop back bit [7:6] - receiver fi xed external termination: rxres[1:0] are used to select the value for a high precision external resistor to improve return loss. ` 00 = none ` 01 = 240w ` 10 = 210w ` 11 = 150w bit 5 - codes encoding / decoding select: this bit is used to select the type of encoding/ decoding the transmitter and receiver will generate/process. ` 0 = hdb3 (e1), b8zs (t1) ` 1 = ami coding bit 4 - reserved: bit 3 - e1arbitrary pulse select: this bit is used to enable the arbitrary pulse generator for shaping the transmit pulse when e1 mode is selected. ` 0 = disabled (normal e1 pulse shape itu g.703) ` 1 = arbitrary pulse enabled bit 2 - insert bipolar violation: when this bit transitions from low to high, a bipolar viol ation will be inserted in the transmitted data from tpos, qrss/prbs pattern. the state of this bit will be sampled on the rising edge of tclk. to ensure proper operation, it is recommended to write a 0 to this bit before writing a 1. ` 0 to 1 transition = insert one bipolar violation bit 1 - insert bit error: when this bit transitions from low to high, a bit error wil l be inserted in the transmitte d qrss/prbs pattern. the state of this bit will be sampled on the rising edge of tclk. to ensure proper operation, it is recommended to write a 0 to this bit before writing a 1. ` 0 to 1 transition = insert one bit error bit 0 - reserved: t able 377: liu c hannel c ontrol r egister 0 (a ddress = 0 x n003) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxres[1:0] codes reserved e1arbit insbpv insber reserved r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 253 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 - reserved: bit6 - digital monitor ou tput interr upt enable: ` 0 = masks the dmo function ` 1 = enables interrupt generation for dmo bit 5 - fifo limit status interrupt enable: ` 0 = masks the fls function ` 1 = enables interrupt generation for fls bit 4 - line code violation interrupt enable: ` 0 = masks the lcv function ` 1 = enables interrupt generation for lcv bit 3 - reserved: bit 2 - alarm indication si gnal interrupt enable: ` 0 = masks the ais function ` 1 = enables interrupt generation for ais bit 1 - receive loss of signal interrupt enable: ` 0 = masks the rl os function ` 1 = enables interrupt generation for rlos bit 0 - quasi random pattern detection interrupt enable: ` 0 = masks the qrpd function ` 1 = enables interrupt generation for qrpd bit6 - digital monitor output: this bit indicates the dmo activity. an interrupt will not occur unless the dmoie is set high in register 0xn004h and the global interrupt enable has been set. ` 0 = no alarm ` 1 = transmit output driver has failures bit 5 - fifo limit status: this bit indicates whether the rd/wr point ers are within 3-bits. an interrupt will not occur unless the flsie is set high in register 0xn004h and the global interrupt enable has been set. ` 0 = no alarm ` 1 = rd/wr fifo pointers are within 3-bits bit 4 - line code violation: t able 378: liu c hannel c ontrol r egister 0 (a ddress = 0 x n004) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dmoie flsie lcvie reserved aisdie rlosie qrpdie r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 379: liu c hannel c ontrol r egister 0 (a ddress = 0 x n005) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dmo fls lcv reserved aisd rlos qrpd ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 254 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 this bit serves a dual purpose. by default, this bit monitors the line code violation activity. however, if bit 7 in register 0x0101h is set high, this bit monitors the overflow status of the internal lcv counter. an interrupt will not occur unless the lcv/ofie is set high in register 0xn004h and the global interrupt enable has been set. ` 0 = no alarm ` 1 = a line code violation, bipolar violation, or excessive zeros has occurred bit 3 - reserved: bit 2 - alarm indication signal: this bit indicates the ais activity. an interrupt will not o ccur unless the aisie is set high in register 0xn004h and the global interrupt enable has been set. ` 0 = no alarm ` 1 = an all ones signal is detected bit 1 - receive loss of signal: this bit indicates the rlos activity. an interrupt will not occur unless the rlosie is set high in register 0xn004h and the global interrupt enable has been set. ` 0 = no alarm ` 1 = an rlos condition is present bit 0 - quasi random pattern detection: this bit indicates that a qrpd has been detected. an interru pt will not occur unless the qrpdie is set high in register 0xn004h and the global interrupt enable has been set. ` 0 = no alarm ` 1 = a qrp is detected n ote : these register bits are reset upon read. they will be set high anytime a change in status occurs. once these bits are read back, they will automatically be set low. bit7 - reserved: bit6 - digital monitor ou tput interrupt enable: ` 0 = no change ` 1 = change in status occurred bit 5 - fifo limit status interrupt enable: ` 0 = no change ` 1 = change in status occurred bit 4 - line code violation interrupt enable: ` 0 = no change ` 1 = change in status occurred bit 3 - reserved: bit 2 - alarm indication si gnal interrupt enable: ` 0 = no change ` 1 = change in status occurred bit 1 - receive loss of signal interrupt enable: ` 0 = no change t able 380: liu c hannel c ontrol r egister 0 (a ddress = 0 x n006) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dmois flsis lcvis reserved aisdis rlosis qrpdis rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 255 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 1 = change in status occurred bit 0 - quasi random pattern detection interrupt enable: ` 0 = no change ` 1 = change in status occurred bit7 - enable rom for lcv counter: this bit is used to enable data from an internal lcv counter to be read back. ` 0 = disabled. ` 1 = enabled. bit [6:5] - reserved: bit 4 - reset all internal lcv counters: this bit is used to reset all 28 internal lcv counters to their default state 0000h. this bit must be set high for a minimum of 1ms. ` 0 = normal operation ` 1 = resets all lcv counters bit 3 - update all lcv counters: this bit is used to latch the contents of all 28 internal lc v counters so that the values can be read. when the hi/lo bit is set low, initiating this update bit places the lower 8 bits of the 16-bit word in register 0xn011h. when the hi/lo bit is set high, initiating this update bit places the u pper 8 bits of the 16-bit word in register 0xn010h. ` 0 = normal operation ` 1 = updates all lcv counters bit 2 - high byte / low byte select: this bit is used to select which byte of the 16-bit lcv value will be placed in the read back registers. ` 0 = lower byte lcv[7:0] ` 1 = upper byte lcv[15:8] bit 1 - update lcv counter: this bit is used to latch the contents of the internal lcv counter for this channel so that the value can be read. when the hi/lo bit is set low, initiating this update bit places the lo wer 8 bits of the 16-bit word in register 0xn011h. when the hi/lo bit is set high, initiating this update bit places the upper 8 bits of the 16-bit word in register 0xn010h. ` 0 = normal operation ` 1 = update lcv counter bit 0 - reset internal lcv counter: this bit is used to reset th e internal lcv for this channel to its defaul t state 0000h. this bit must be set high for a minimum of 1ms. ` 0 = normal operation ` 1 = reset lcv counter t able 381: liu c hannel c ontrol r egister 0 (a ddress = 0 x n007) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 enrom reserved reserved rstall updateall hi/lo update rst r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 256 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 1: the transmit output pulse is divided into 8 individual segments . this register is used to program the first segment which corresponds to the overshoot of the puls e amplitude. there are four segments fo r the top portion of the pulse and four segments for the bottom portion of the pulse. segment number 5 corresponds to the undershoot of the pulse. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 2: the transmit output pulse is divided into 8 individual segment s. this register is used to program the second segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 3: the transmit output pulse is divided into 8 individual segmen ts. this register is used to program the third segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction t able 382: liu c hannel c ontrol r egister 0 (a ddress = 0 x n008) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s1 b5s1 b4s1 b3s1 b2s1 b1s1 b0s1 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 383: liu c hannel c ontrol r egister 0 (a ddress = 0 x n009) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s2 b5s2 b4s2 b3s2 b2s2 b1s2 b0s2 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 384: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00a) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s3 b5s3 b4s3 b3s3 b2s3 b1s3 b0s3 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 257 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 4: the transmit output pulse is divided into 8 individual segments. this register is used to program the fourth segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 5: the transmit output pulse is divided into 8 individual segments. this register is used to program the fifth segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 6: the transmit output pulse is divided into 8 individual segments. this register is used to program the si xth segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction t able 385: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00b) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s4 b5s4 b4s4 b3s4 b2s4 b1s4 b0s4 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 386: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s5 b5s5 b4s5 b3s5 b2s5 b1s5 b0s5 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 387: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00d) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s6 b5s6 b4s6 b3s6 b2s6 b1s6 b0s6 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 258 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 7: the transmit output pulse is divided into 8 individual segments . this register is used to program the seventh segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction bit7 - reserved: bit [6:0] - arbitrary puls e generation segment 8: the transmit output pulse is divided into 8 individual segments. this register is used to program the eighth segment of the pulse amplitude. the msb of each segment is the sign bit. ? if sign bit (bit6) =: ` 0 - negative direction ` 1 - positive direction bit [7:0] - internal lc v counter high byte: once the internal lcv counter has been enabled and updated, these bits contain the upper byte of the 16-bit lcv counter word. t able 388: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00e) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s7 b5s7 b4s7 b3s7 b2s7 b1s7 b0s7 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 389: liu c hannel c ontrol r egister 0 (a ddress = 0 x n00f) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b6s8 b5s8 b4s8 b3s8 b2s8 b1s8 b0s8 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 390: liu c hannel c ontrol r egister 0 (a ddress = 0 x n010) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcvhi7 lcvhi6 lcvhi5 lcvhi4 lcvhi3 lcvhi2 lcvhi1 lcvhi0 ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 0
preliminary XRT86SH328 259 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] - internal lcv counter low byte: once the internal lcv counter has been enabled and updated, these bits contain the lower byte of the 16-bit lcv counter word. 2.13 ds1/e1 framer block re gisters - ds1 applications the register map for the ds1/e1 framer blocks (for ds1 applications) is presented in the table below. additionally, a detailed description of each of the ds1/e1 framer block register is presented below. n ote : the register map/descrip tion for the ds1/e1 framer blocks (for e1 applications) is pr esented in section _. in order to provide some orientatio n for the reader, an illustration of the functional block diagram for the XRT86SH328 device, with both the ingress and egress direction transmit/receive ds1/e1 framer blocks highlighted is presented below in figure 17 .. some comments about addressing ds1/e1 framer block registers t able 391: liu c hannel c ontrol r egister 0 (a ddress = 0 x n011) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcvlo7 lcvlo6 lcvlo5 lcvlo4 lcvlo3 lcvlo2 lcvlo1 lcvlo0 ro ro ro ro ro ro ro ro 0 0 0 0 0 0 0 0 f igure 17. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the t rans - mit /r eceive ds1/e1 f ramer blocks highlighted sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
XRT86SH328 preliminary 260 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 throughout the XRT86SH328 data sheet, the user can co ntrol/monitor the function/p erformance of the t1/e1 framer blocks consists of t he following sets of registers. ? channel control registers ? receive signaling array registers ? lapd buffer 0 data registers ? lapd buffer 1 data registers ? channel - framer performance monitor registers ? channel - framer interrupt register in the XRT86SH328 data sheet, we indicate that the following sets of register have the following address locations. n ote : the XRT86SH328 has a total of 28 ingress direction transmit/receive ds1/e1 framer blocks and 28 egress direction transmit/receive ds1/e1 fr amer blocks. hence, the xrt86sh 328 device contains a total of 56 transmit/receive ds1/e1 framer blocks. therefore, in t able _-1, the value of n can ra nge in value from 0x01 to 0x38. obvious question: what value of n pertains to which of the 56 t1/e1 framer blocks within the chip? the answer to this question depends upon whether the XRT86SH328 has been configured to operate in the vt-mapper (with t1/e1 framing) or in the m13 mux (with t1/e1 framing) mode. table 393 and table 394 present the values for n (for each t1/e1 framer block) as a function of channel number and signal direction for vt- mapper (with t1/e1 framing) and m13 mux (with t1/e1 framing) applications, respectively. further, figure 18 (which depicts an illustration of the various t1/e1 framer blocks within a given channel) can be used as a point of reference when looking at table 393 and table 394 . t able 392: m emory m ap - t1/e1 f ramer b lock a ddress l ocation r egister s et 0xn100 - 0xn1ff channel x - control registers 0xn200 - 0xn2ff reserved 0xn300 - 0xn3ff channel x - channel control registers 0xn400 - 0xn4ff reserved 0xn500 - 0xn5ff channel x - receive signaling array registers 0xn600 - 0xn6ff channel x - lapd buffer 0 data register 0xn700 - 0xn7ff channel x - lapd buffer 1 data register 0xn800 - 0xn8ff reserved 0xn900 - 0xn9ff channel x - framer performance monitor registers 0xna00 - 0xnaff reserved 0xnb00 - 0xnbff channel x - framer interrupt registers
preliminary XRT86SH328 261 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications f igure 18. i llustration of the f unctional b lock d iagram of the XRT86SH328 device with both the i ngress and e gress d irection t1/e1 f ramer blocks ( of a given t1/e1 c hannel ) highlighted t able 393: r elationship between v alue of n and c hannel n umber , s ignal d irection - vt-m apper ( with t1/e1 f raming ) m ode a pplications i ngress d irection e gress d irection c hannel n umber r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock 1 0x1d 0x01 0x01 0x1d 2 0x1e 0x02 0x02 0x1e 3 0x1f 0x03 0x03 0x1f 4 0x20 0x04 0x04 0x20 5 0x21 0x05 0x05 0x21 6 0x22 0x06 0x06 0x22 7 0x23 0x07 0x07 0x23 8 0x24 0x08 0x08 0x24 9 0x25 0x09 0x09 0x25 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
XRT86SH328 preliminary 262 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 10 0x26 0x0a 0x0a 0x26 11 0x27 0x0b 0x0b 0x27 12 0x28 0x0c 0x0c 0x28 13 0x29 0x0d 0x0d 0x29 14 0x2a 0x0e 0x0e 0x2a 15 0x2b 0x0f 0x0f 0x2b 16 0x2c 0x10 0x10 0x2c 17 0x2d 0x11 0x11 0x2d 18 0x2e 0x12 0x12 0x2e 19 0x2f 0x13 0x13 0x2f 20 0x30 0x14 0x14 0x30 21 0x31 0x15 0x15 0x31 22 0x32 0x16 0x16 0x32 23 0x33 0x17 0x17 0x33 24 0x34 0x18 0x18 0x34 25 0x35 0x19 0x19 0x35 26 0x36 0x1a 0x1a 0x36 27 0x37 0x1b 0x1b 0x37 28 0x38 0x1c 0x1c 0x38 t able 394: r elationship between v alue of n and c hannel n umber , s ignal d irection - m13 mux ( with t1/e1 f raming ) m ode a pplications i ngress d irection e gress d irection c hannel n umber r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock 1 0x01 0x1d 0x1d 0x01 2 0x02 0x1e 0x1e 0x02 3 0x03 0x1f 0x1f 0x03 4 0x04 0x20 0x20 0x04 5 0x05 0x21 0x21 0x05 6 0x06 0x22 0x22 0x06 t able 393: r elationship between v alue of n and c hannel n umber , s ignal d irection - vt-m apper ( with t1/e1 f raming ) m ode a pplications i ngress d irection e gress d irection c hannel n umber r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock
preliminary XRT86SH328 263 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 - reserved 7 0x07 0x23 0x23 0x07 8 0x08 0x24 0x24 0x08 9 0x09 0x25 0x25 0x09 10 0x0a 0x26 0x26 0x0a 11 0x0b 0x27 0x27 0x0b 12 0x0c 0x28 0x28 0x0c 13 0x0d 0x29 0x29 0x0d 14 0x0e 0x2a 0x2a 0x0e 15 0x0f 0x2b 0x2b 0x0f 16 0x10 0x2c 0x2c 0x10 17 0x11 0x2d 0x2d 0x11 18 0x12 0x2e 0x2e 0x12 19 0x13 0x2f 0x2f 0x13 20 0x14 0x30 0x30 0x14 21 0x15 0x31 0x31 0x15 22 0x16 0x32 0x32 0x16 23 0x17 0x33 0x33 0x17 24 0x18 0x34 0x34 0x18 25 0x19 0x35 0x35 0x19 26 0x1a 0x36 0x36 0x1a 27 0x1b 0x37 0x37 0x1b 28 0x1c 0x38 0x38 0x1c t able 395: t1 f ramer b lock - c lock s elect r egister (a ddress = 0 x n100, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused set t1 mode force all channels to sync to 8khz unused clock source select[1:0] r/o r/w r/w r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 1 t able 394: r elationship between v alue of n and c hannel n umber , s ignal d irection - m13 mux ( with t1/e1 f raming ) m ode a pplications i ngress d irection e gress d irection c hannel n umber r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock r eceive ds1/e1 f ramer b lock t ransmit ds1/e1 f ramer b lock
XRT86SH328 preliminary 264 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit6 - set t1 mode: this read/write bit-field is used to configure the channel to operate in either the t1 or e1 mode. ` 0 - configures the framer chann el to operate in the e1 mode ` 1 - configures the framer chann el to operate in the t1 mode bit 5 - force all channels to sync to 8khz: this read/write bit-field is used to configure all active (either 28 or 56) transmit ds1 framer blocks to synchronize their transmit output frame ali gnment with the 8khz signal that is derived from the mclk pll. ` 0 - does not configure each of the transmit ds1 framer bl ocks to synchronize their tr ansmit output frame alignment with the 8khz signal (from the mclk pll). ` 1 - configures each of the transmit ds 1 framer blocks to synchronize their tr ansmit output fram e alignment with the 8khz signal (from the mclk pll). n ote : this feature should only be used if the XRT86SH328 has been configured to operate in the 28-channel ds1 framer/liu combo mode. the user must not use this feature if the XRT86SH328 has been configured to operate in any of the aggregation modes. bit [4:2] - reserved bit [1:0] - clock source select[1:0]: these two read/write bit-fields is used to specify the ti ming source for the ingress and direction transmit ds1 framer block, within this particular channel. the relationship between the clock source select[1:0] bit-fields and the resulting timing source for the transmit ds1 framer block, within this particular channel c lock s ource s elect [1:0] t iming s ource for t ransmit ds1 f ramer b lock 00 loop-timing mode:the transmit ds1 framer block will derive its timing from the received or recovered clock signal within the corresponding receive ds1 framer block.note: this timing option is only available if the user has config - ured the XRT86SH328 to operate in the 28-channel ds1 framer/liu combo mode 01 local-timing mode (txds1clk_n input)the transmit ds1 framer block will either use up-stream timing or the txds1clk_n input as its timing source.note: for aggregation applicati ons, the user must configure all active ds1 framer blocks to oper ate in this timing mode. 10 local-timing mode (mclk pll input)the transmit ds1 framer block will derive its timing from the mclk pll.note: this timing option is only available if the user has configured the XRT86SH328 to operate in the 28-channel ds1 framer/liu combo mode. 11 loop-timing modethe transmit ds1 framer block will derive its timing from the received or recovered clock signal within the corresponding receive ds1 framer blocknote: this timing option is only available if the user has config - ured the XRT86SH328 to operate in the 28-channel ds1 framer/liu combo mode. t able 396: t1 f ramer b lock - l ine i nterface c ontrol r egister (a ddress = 0 x n101, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit los pattern reserved framer loop-back[1:0] reserved r/w r/o r/w r/w r/o r/o r/o r/o 0 1 0 0 0 0 0 0
preliminary XRT86SH328 265 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 - transmit los pattern: this read/write bit-field configures the transmit ds1 framer block to generat e and transmit the los pattern to the remote terminal. ` 0 - configures the transmit ds1 framer block to transmit normal ds1 traffic ` 1 - configures the transmit ds1 fram er block to transmit the los pattern. n ote : the user must set this bit-field to 0 for normal operation. bit6 - reserved: bit [5:4] - framer loop-back[1:0]: these two read/write bit-fields are us ed to configure the transmit/receive ds1 framer blocks to operate in a variety of possible loop-back modes, as depicted in the table below. bit7 - signaling update on super frame boundaries: this read/write bit-field is used to either enable or di sable signaling update on super-frame boundaries, in both the transmit and receive directions, as described below. in the receive direction if the user enables this feature, then signaling data will update (via the receiv e signaling array registers) only upon the super-frame boundaries. if the user does not to enabl e this feature, then signaling data will be updated (within the receive signaling array registers) as soon as they are received within t he incoming ds1 data-stream. in the transmit direction if the user enables this feature, then any signaling data that occu r (within the transmit output ds1 data-stream) will be updated upon the super-frame boundaries. if the user does not to enable this feat ure, then signaling data (within the outbound ds1 data-stream) will be upda ted as soon as it is changed. ` 0 = disables the signaling update on super-frame boundaries features. ` 1 = enables the signaling update on super-frame boundaries features. bit6 - force crc errors: this read/write bit-field is used to force the transmit ds1 framer block to transmit crc errors within the outbound ds1 data-stream. ` 0 = configures the transmit ds1 framer block to transmit ds1 data with correct crc values relationship between the framer loop-back[1:0] bit-fields and the corresponding loop-back mode within the ds1 framer block f ramer l oop - back [1:0] r esulting l oop -b ack m ode ( within f ramer b lock ) 00 normal operation (no loop-back) mode 01 local loop-back mode 10 remote loop-back mode 11 reserved t able 397: t1 f ramer b lock - f raming s elect r egister (a ddress = 0 x n107, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 signaling update on super frame boundaries force crc errors set j1 mode one & only fast sync ds1 framing format select[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 266 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 1 = configures the transmit ds1 framer block to transmit ds1 data with erred crc values. n ote : the transmit ds1 framer block will transmit ds1 data, with erred crc values, for the duration that this bit-field is set to 1. bit 5 - set j1 mode: this read/write bit-field, along with bit6 (set t1 mode ) within the t1/e1 framer block - clock select register (address = 0xn100) is used to configure t he channel to operate in the j1 mode. bit 4 - one & only: bit 3 - fast sync: bit [2:0] - ds1 framin g format select[2:0]: these three read/write bit-fields is used to select the framing format that the ds1 framer channel will operate ini. bit7 - yellow alarm - one second rule: this read/write bit-field is used to configure the transmit ds1 framer to tr ansmit the rai (or yellow alarm) indicator per the one second rule (as describ ed in the ansi standards). transmission of the rai indi cator per the one second rule if the user invokes the one second rule, then the following will happen. ? whenever the transmit ds1 framer blo ck generates and transmits the rai indicator, it will do so for at least one second (for both the esf and the sf framing formats) the relationship between the states of the set t1 mode and the set j1 mode bit-fields and the corresponding mode of channel s et j1 m ode s et t1 m ode (bit6 in 0 x n100) o perating m ode of c hannel 0 0 e1 mode 0 1 t1 mode 1 0 e1 mode 1 1 j1 mode the relationship between the state of the ds 1 framing format select[2:0] bits and the resulting framing format of the channel ds1 f raming f ormat s elect [2:0] r esulting f raming f ormat 0xx ds1, esf - extended super-frame 100 do not use 101 ds1, sf - super-frame 11x do not use t able 398: t1 f ramer b lock - a larm g eneration r egister (a ddress = 0 x n108, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 yellow alarm - one sec - ond rule transmit yel - low alarm yellow alarm format[1:0] transmit ais pattern select[1:0] ais defect declaration cri - teria[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 267 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ? the transmit ds1 framer block will insure that there is a minimum of a one-second delay between the time that it terminates transmission of the rai indicator, and the instant that it proceeds to transmit the rai indicator again. transmission of the rai indicator when the one second rule is not in-force if the user does not invoke the one se cond rule, then the following will happen. ? whenever the transmit ds1 framer blo ck generates and transmits the rai indicator, it will do so for at least one second (for both the esf and the sf framing formats). ? the transmit ds1 framer block will not insure that th ere is a minimum of a one-second delay between the time that it terminates transmission of the rai indicator, and the instant that it pr oceeds to transmit the rai indicator again. ` 0 = does not configure the transmit ds1 framer block to transmit the rai indicator per the one second rule. ` 1 = configures the transmit ds1 framer block to transmit the rai indicator per the one second rule. bit6 - transmit yellow alarm: bit [5:4] - yellow alarm format[1:0]: bit [3:2] - transmit ais pattern select[1:0]: these two read/write bit-fields serves the following two functions. ? to command the transmit ds1 framer block to transm it the ais indicator (per software command), and ? to specify the type of ais pattern that the transmit ds1 framer block will transmit, whenever it has been commanded to transmit the ais indicator to the remote terminal equipment. bit [1:0] - ais defect declaration criteria[1:0]: these two read/write bit-fields are used to select the ty pe of ais pattern that the receive ds1 framer block will look for in order to determine whether or not it should declare or clear the ais defect condition the relationship between transmit ais pattern select[1:0] and the resulting behavior of the transmit ds1 framer block t ransmit ais p attern s elect [1:0] t ransmit ds1 f ramer b lock a ction 00/10 transmits normal traffictransmit ds1 framer block does not transmit the ais indi - cator. it will (instead) transmit normal traffic 01 unframed all ones patternthe transmit ds1 framer block will transmit an unframed all ones pattern (as an ais pattern) for the dura tion that these bit-fields are set to [0, 1]. 11 framed all ones patternthe transmit ds1 framer block will transmit a framed all ones pattern (as an ais pattern) for the duration that these bit-fields are set to [1, 0]. the relationship between ais defect declaration crit eria[1:0] and the resulting ais pattern that the receive ds1 framer block will look for in declaring/clearing the ais defect condition ais d efect d eclaration c riteria [1:0] r eceive ds1 f ramer b lock - ais d efect d eclaration c riteria 00/10 ais defect declaration is disabledthe re ceive ds1 framer block will not declare the ais defect condition at all. 01 unframed and framed all ones pattern:the receive ds1 framer block will declare the ais defect condition whenever it receives either the framed or unframed all ones pattern for at least 42ms. 11 framed all ones pattern:the receive ds1 framer block will only declare the ais defect condition whenever it receives the fr amed all ones pattern for at least 42ms.
XRT86SH328 preliminary 268 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:2] - reserved bit 1 - crc-6 source select: this read/write bit-field is used to specify the sour ce of the crc-6 bits, within the outbound ds1 data-stream. ` 0 = configures the transmit ds1 framer block to interna lly compute and insert the cr c-6 bits within the outbound ds1 data-stream. ` 1 = configures the transmit ds1 framer block to externa lly accept data from the txds 1data_n input pin (or from upstream circuitry) and to insert this data into t he crc-6 bit-fields within the outbound ds1 data-stream. bit 0 - framing bits source select: this read/write bit-field is used to specify the source of the framing bits, within the outbound ds1 data-stream. ` 0 = configures the transmit ds1 framer block to internally generate and insert the framing bits within the outbound ds1 data-stream ` 1 = configures the transmit ds1 framer block to externa lly accept data from the txds 1data_n input pin (or from upstream circuitry) and to insert th is data into the framing bit-fields within the outbound ds1 data-stream. bit [7:6] - reserved: bit [5:4] - transmit data link bandwidth[1:0]: these two read/write bit-fields are used to select the data link bandwidth (for the transmission of data link messages) within the outbound ds 1 data-stream. data link messages can be transmitted at a rate of either 4khz or 2khz. t able 399: t1 f ramer b lock - s ynchronization mux r egister (a ddress = 0 x n109, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved crc-6 source select framing bits source select r/o r/w r/w r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0 t able 400: t1 f ramer b lock - t ransmit d ata l ink s elect r egister (a ddress = 0 x n10a, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved transmit data link band - width[1:0] transmit d/e time source select[1:0] transmit data link source select[1:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 the relationship between transmit data link bandwidth[1:0] and the resulting bits/bandwidth available for the transport of data link messages within the outbound ds1 data-stream t ransmit d ata l ink b andwidth [1:0] r esulting b andwidth available to transport d ata l ink m essages within outbound ds1 data - stream 00 data link bandwidth = 4khzdata link messages are being transported via every single dl bit-field within the outbound ds1 data-stream 01 data link bandwidth = 2khz (frames 1, 5, 9, ?.)data link messages are being trans - ported via every other dl bit-field wit hin the outbound ds1 data-stream.
preliminary XRT86SH328 269 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : this bit-field only applies if the channel has been c onfigured to operate in t he t1-esf framing format. bit [3:2] - transmit d/e time source select[1:0]: these two read/write bit-fields are us ed to specify the source of the data that is to be transported via the d/e time-slots within the outbound transmit ds1 data-stream. n ote : these two register bits are only active if the user ha s configured one of the time-slots (within the outbound ds1 data-stream) to function as the d/e channel. bit [1:0] - transmit data link source select[1:0]: these two read/write bit-fields are used to specify the source for the data that will be transported via the data link bits, within the outbound ds1 data-stream. 10 data link bandwidth = 2khz (frames 3, 7, 11,?)data link messages are being trans - ported via every other dl bit-field within the outbound ds1 data-stream. 11 do not use the relationship between transmit d/e time source select[1:0] and the resulting source of the d/e- time-slot data within the outbound ds1 data-stream t ransmit d/e t ime s ource s elect [1:0] s ource for t ransmit d/e t ime -s lot d ata 00 upstream circuitry (for a ggregation applications) or the txds1data_n input (for 28-channel ds1 framer/liu combo mode applications). 01 the transmit lapd controller block 10 reserved - do not use 11 the relationship between transmit data link source select[1:0] and the resulting source of the data (which is to be transported via the data link bits, within the outbound ds1 data-stream) t ransmit d ata l ink s ource s elect [1:0] r esulting s ource of d ata l ink d ata 00 transmit lapd controller block (within the transmit ds1 framer block) 01 upstream circuitry (for aggregation applications) or the txds1data_n input (for 28-channel ds1 framer/liu combo mode applications) 10 reserved 11 data link bits are each forced to 1. the relationship between transmit data link bandwidth[1:0] and the resulting bits/bandwidth available for the transport of data link messages within the outbound ds1 data-stream t ransmit d ata l ink b andwidth [1:0] r esulting b andwidth available to transport d ata l ink m essages within outbound ds1 data - stream
XRT86SH328 preliminary 270 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - reframe: this read/write bit-field is used to command a reframe to the receive ds1 framer block. a 0 to 1 transition (within this bit-field) will force the receive ds1 framer block to restart the frame synchronizati on process. the receive ds1 framer block will automatically clear this bit-field to 0 onc e it has reacquired frame synchronization with the incoming ds1 data-stream. bit6 - framing with crc checking: this read/write bit-field is used to configure the receive ds1 framer block to also include checking for correct crc- 6 values as a part of in-frame declarati on criteria. more specifically, if the us er enables this feat ure, then the receive ds1 framer block will also check and verify that the inco ming ds1 data-stream contains correct crc data, prior to declaring the in-frame condition. ` 0 = crc verification is not included in the framing alignment process. ` 1 = the receive ds1 framer block will also check for corre ct crc values prior to declaring the in-frame condition. bit [5:3] - lof tolerance[2:0]: n ote : these read/write bit-fields along with the lof range[ 2:0] bit-fields are used to define the lof defect declaration criteria. the receive ds1 framer block will declare the lof defect condition anytime it detects lof_tolerance[2:0](or more) framing bit errors, withi n any sliding window (consisting of lof_range[2:0] framing the recommended value for lof_tolerance[2:0] is 2. bit [2:0] - lof range[2:0]: these read/write bit-fields along wi th the lof_tolerance[2:0] bit-fields are used to define the lof defect declaration criteria. the receive ds1 framer block wi ll declare the lof defect condition anytime it detects lof_tolerance[2:0] (or more) framing bit errors, within any sliding window (consisting of lof_ range[2:0] framing alignments) within the in coming ds1 data-stream. bit [7:6] - reserved: bit [5:4] - received data link bandwidth[1:0]: these two read/write bit-fields is used to select the data link bandwidth (for the reception of data link messages) within the incoming ds1 data-stream. data link messages can be received at a rate of either 4khz or 2khz. t able 401: t1 f ramer b lock - f raming c ontrol r egister (a ddress = 0 x n10b, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reframe framing with crc checking lof tolerance[2:0] lof range[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 0 0 0 0 0 t able 402: t1 f ramer b lock - r eceive s ignaling & d ata l ink s elect r egister (a ddress = 0 x n10c, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved receive data link band - width[1:0] receive d/e time-slot des - tination select[1:0] receive data-link destina - tion select[1:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 271 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : this bit-field only applies if the channel has been c onfigured to operate in t he t1-esf framing format. bit [3:2] - receive d/e time-s lot destination select[1:0]: these two read/write bit-fields are used to specify the source of the data that is to be transported via the d/e time- slots within the incoming receive ds1 data-stream. n ote : these two register bits are only active if the user has configured one of the time-slots (within the incoming ds1 data-stream) to function as the d/e channel. bit [1:0] - receive data link destination select[1:0]: these two read/write bit-fields are used to specify the source for the data t hat will be transported via the data link bits, within the incoming ds1 data-stream. the relationship between receive data link bandwidth[1:0] and the resulting bits/bandwidth available for the transport of data link messages within the incoming ds1 data-stream r eceive d ata l ink b andidth [1:0] r esulting b andwidth available to transport d ata l ink m essages within incoming ds1 data - stream 00 data link bandwidth = 4khzdata link messages are being transported via every single dl bit-field within the incoming ds1 data-stream 01 data link bandwidth = 2khz (frames 1, 5, 9, ?.)data link messages are being transported via every other dl bit-field within the incoming ds1 data- stream. 10 data link bandwidth = 2khz (frames 3, 7, 11,?)data link messages are being transported via every other dl bit-field within the incoming ds1 data- stream. 11 do not use the relationship between receive d/e time source select[1:0] and the resulting source of the d/e- time-slot data within the incoming ds1 data-stream r eceive d/e t ime s ource s elect [1:0] d estination of the incoming r eceive d/e t ime -s lot d ata 00 downstream circuitry (for aggregation applications) or the rxds1data_n output (for 28-channel ds1 framer/liu combo mode applications). 01 the receive lapd controller block 10 reserved - do not use 11 the relationship between receive data link source se lect[1:0] and the resulting source of the data (which is to be transported via the data li nk bits, within the incoming ds1 data-stream) t ransmit d ata l ink s ource s elect [1:0] r esulting d estination of d ata l ink d ata 00 receive lapd controller block (within the receive ds1 framer block) 01 downstream circuitry (for aggregation appl ications) or the rxds 1data_n output (for 28-channel ds1 framer/liu combo mode applications) 10 reserved 11 data link bits are ignored
XRT86SH328 preliminary 272 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:0] - receive signaling change - channel n=[0:7]: these reset-upon-read bit-fields indicate whether the channel associated signaling data associated with time- slots 0 through 7 (within the incoming ds1 data-stream) has changed since the last read of this register. ` 0 = indicates that cas data (for time -slots 0 through 7) has not changed since the last read of this register. ` 1 = indicates that cas data (for time-slots 0 through 7) has change d since the last read of this register. n ote : this register is only active if the incoming ds1 data-stream is using channel associated signaling. bit [7:0] - receive signaling change - channel n=[8:15]: these reset-upon-read bit-fields indicate whether the channel associated signaling data associated with time- slots 8 through 15 (within the incoming ds1 data-strea m) has changed since the last read of this register. ` 0 = indicates that cas data (for time -slots 8 through 15) has not changed si nce the last read of this register. ` 1 = indicates that cas data (for time-slots 8 through 15) has changed since the last read of this register. bit [7:0] - receive signaling change - channel n=[16:23]: these reset-upon-read bit-fields indicate whether the channel associated signaling data associated with time- slots 16 through 23 (within the incoming ds1 data-str eam) has changed since the last read of this register. t able 403: t1 f ramer b lock - r eceive s ignaling c hange r egister - 0 (a ddress = 0 x n10d, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive signaling change - channel 0 receive signaling change - channel 1 receive signaling change - channel 2 receive signaling change - channel 3 receive signaling change - channel 4 receive signaling change - channel 5 receive signaling change - channel 6 receive signaling change - channel 7 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 404: t1 f ramer b lock - r eceive s ignaling c hange r egister - 1 (a ddress = 0 x n10e, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive signaling change - channel 8 receive signaling change - channel 9 receive signaling change - channel 10 receive signaling change - channel 11 receive signaling change - channel 12 receive signaling change - channel 13 receive signaling change - channel 14 receive signaling change - channel 15 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 405: t1 f ramer b lock - r eceive s ignaling c hange r egister - 2 (a ddress = 0 x n10f, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive signaling change - channel 16 receive signaling change - channel 17 receive signaling change - channel 18 receive signaling change - channel 19 receive signaling change - channel 20 receive signaling change - channel 21 receive signaling change - channel 22 receive signaling change - channel 23 rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 273 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 0 = indicates that cas data (for time-s lots 16 through 23) has not changed since the last read of this register. ` 1 = indicates that cas data (for time -slots 16 through 23) has changed since the last read of this register. n ote : this register is only active if the incoming ds1 data-stream is using channel associated signaling. bit7 - in frame state: this read-only bit-field indicates whether or not the rece ive ds1 framer block is currently declaring the in-frame condition within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block is curren tly declaring the lof (loss of frame) defect condition. ` 1 = indicates that the receive ds1 framer block is curren tly declaring itself to be in the in-frame condition. bit [6:0] - reserved bit7 - reserved bit6 - mos abort disable: this bit is used to either enable or di sable the automatic mos abort feature with in the transmit hdlc controller. if the user enables this feature, then the transmit hdlc controller will automatically transmit the abort sequence (e.g., a zero followed by a string of 7 consecutive 1's) whenever it abruptly transitions from transmitting a mos type of message to transmitting a bos type of message. ` 0 = enables the automatic mos abort feature ` 1 = disabled bit 5 - receive frame check sequence disable: this bit is used to configure the receive hdlc controller to compute and verify the fcs value within each incoming lapd message frame. ` 0 = enables fcs verification ` 1 = disabled bit 4 - auto receive: this bit configures the receive hdlc controller to discard any incoming bos or lapd message frame that exactly match which is currently stored in the receive hdlc buffer. ` 0 = disabled ` 1 = enables this auto discard feature bit 3 - transmit abort: this bit configures the transmit hdlc controller to transmit an abort sequence (string of 7 or more consecutive 1's) to t able 406: t1 f ramer b lock - r eceive e xtra -b its r egister (a ddress = 0 x n112, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 in frame state reserved r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 407: t1 f ramer b lock - d ata l ink c ontrol r egister (a ddress = 0 x n113, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mos abort disable rx_fcs_di s autorx tx_abort tx_idle tx_fcs_en mos/bos r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 274 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 the remote terminal. ` 0 = disabled ` 1 = transmit the abort sequence bit 2 - transmit idle (flag sequence byte): this bit configures the transmit hdlc controller to unconditi onally transmit a repeating string of flag sequence octets (0x7e) in the data link channel to the remote terminal. in normal conditions, the transmit hdlc controller will repeatedly transmit the flag sequence octet whenever there is no mo s message to transmit to the remote terminal equipment. however, if the user invokes this transmit idle s equence feature, then the tr ansmit hdlc controller will unconditionally transmit a r epeating stream of the flag sequence octe t (thereby overwrit ing all outbound mos data link messages). ` 0 = disabled ` 1 = transmit a repeating string of flag sequence octets (0x7e) n ote : this bit is ignored if the transmit hdlc controller is operating in the bos mode (bit 0 within this register is set to 0). bit 1 - transmit frame check sequence enable: this bit is used to configure the transmit hdlc controlle r to compute and append fcs octets to the back end of each outbound mos data link message. ` 0 = disabled ` 1 = compute and append the fcs octets to the ba ck end of each outbound mos data link message n ote : this bit is ignored if the transmit hdlc controller ahs been configured to operate in the bos mode - bit 0 within this register is set to 0). bit 0 - mos / bos: this bit is used to configure transmit and receive the hdlc to be transmitting and receiving either bos (bit oriented signaling) or mos (message oriented signaling) frames. ` 0 = transmit and receive bos messages ` 1 = transmit and receive mos messages bit7 - transmit hdlc buffer available: this bit has different functions depending upon whether th e user is writing to or reading from this register. if user is writing data into this register bit ` 0 = configures the transmit hdlc controll er to read out and transmit the data, residing within the transmit hdlc buffer 0 via the data link channel to the remote terminal equipment. ` 1 = configures the transmit hdlc controll er to read out and transmit the data, residing within the transmit hdlc buffer 1 via the data link channel to the remote terminal equipment. if user is reading data from this register bit ` 0 = indicates that transmit buffer 0 is the next available buffer. in this case, to write in the contents of a new outbound data link message into the transmit hdlc message buffe r, the message should be written into buffer 0. ` 1 = indicates that transmit buffer 1 is the next available buffer. in this case, to write in the contents of a new outbound data link message into the transmit hdlc message buffe r, the message should be written into buffer 1. t able 408: t1 f ramer b lock - t ransmit d ata l ink c ontrol r egister (a ddress = 0 x n114, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txhdlc bufavail transmit hdlc message byte count r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 275 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : if one of these transmit hdlc buffers contain a message which has yet to be completely read in and processed for transmission by the transmit hdlc controller, then th is bit will automatically reflect the value corresponding to the next available buffer when it is read. chang ing this bit to the in use buffer is not permitted. bit [6:0] - transmit hdlc message byte count: the exact function of these bits depends on whether the transmit hdl c controller is configured to transmit mos or bos messages to the remote terminal equipment. in bos mode: these bit fields contain the number of repetitions the bos message must be transmitted before the transmit hdlc controller generates the transmit end of transfer (txeot) interrupt and halts transmission. if these fields are set to 0000000, then the bos message will be trans mitted for an indefinite number of times. in mos mode: these bit fields contain the length, in number of octets, of the message to be tr ansmitted. the length of mos message specified in these bits include header bytes such as the sa pi, tei, and control field. however, it does not include the fcs bytes. bit7 - receive hd lc buffer pointer: this bit identifies which receive hdlc buffer cont ains the most recently received hdlc message. ` 0 = indicates that receive hdlc buff er 0 contains the contents of the most recently received hdlc message. ` 1 = indicates that receive hdlc buffer 1 contains the contents of the mo st recently received hdlc message. bit [6:0] - receive hdlc message byte count: the exact function of these bits depend s on whether the receive hdlc controller is configured to receive mos or bos messages. in bos mode: these seven bits contain the number of repetitions t he bos message must be received before the receive hdlc controller generates the receiv e end of transfer (rxeot) interrupt. if these bits are set to 0000000, the message will be received indefinitely and no rxeot interrupt will be generated. in mos mode: these seven bits contain the size in bytes of the hdlc me ssage that has been received and written into the receive hdlc buffer. the length of mos message shown in these bits include header bytes such as the sapi, tei, control field, and the fcs bytes. bit [3:2] - ci alarm tr ansmit (only in esf) these two bits are used to enable or disable ais-ci or ra i-ci generation in t1 esf mode only. ais-ci and rai-ci are t able 409: t1 f ramer b lock - r eceive d ata l ink c ontrol r egister (a ddress = 0 x n115, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rbufptr receive hdlc message byte count r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 410: t1 f ramer b lock - c ustomer i nstallation a larm g eneration r egisters (a ddress = 0 x n11c, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused customer installation alarm generation[1:0] customer installation alarm detection[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 276 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 intended for use in a network to differentiate between an i ssue within the network or the customer installation (ci). ais-ci ais-ci is an all ones with an embedded signature of 01111100 11111111 (right-to-left) which recurs at 386 bit intervals in the ds-1 signal. rai-ci remote alarm indication (rai-ci) is a repe titive pattern with a period of 1.08 se conds. it comprises 0.99 seconds of rai message (00000000 11111111 right-to-left) and a 90 ms of rai-ci signature (00111110 11111111 right-to-left) to form an rai-ci signal. ` 00/11 = disabled ` 01 = enables unframed ais-ci alarm generation ` 10 = enables rai-ci alarm generation bit [1:0] - ci alarm detect (only in esf) these two bits are used to enable or disable ai s-ci or rai-ci alarm detection in t1 esf only. ` 00/11 = disabled ` 01 = enables unframed ais-ci alarm detection ` 10 = enables rai-ci alarm detection bit7 - reset by register: this read/write bit-field is used to execute a software reset to the t1/e1 framer bl ock, within a given channel. ` 0 = configures the t1/e1 framer block to operate normally. ` 1 = configures the t1/e1 framer block (of the correspondi ng channel) to operate in the software reset condition. n ote : once the t1/e1 framer block exits th e software reset state, it will autom atically clear this bit-field to 0. bit [6:4] - reserved these bits are reserved bit 3 - prbs switch: this read/write bit-field is used to specify the direction that the prbs pattern will be transmitted. ` 0 = prbs pattern will be generated and transmitted towards tran smit output of the transmit ds1 framer block. this prbs pattern will also be monitored at the receive input of the corresponding re ceive ds1 framer block. ` 1 = prbs pattern will be generated and tr ansmitted towards the system side output of the receive ds1 framer block. this prbs pattern will also be monitored at the system-side input of the transmit ds1 framer block. bit [2:1] ber control[1:0]: these read/write bit-fields is used to configure the prbs generator (within the transmit ds1 framer block) to insert bit-errors. t able 411: t1 f ramer b lock - ds1 t est r egister - 2 (a ddress = 0 x n121, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset by register unused prbs switch ber control[1:0] unframed prbs r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 resulting errors generated by the prbs generator ber c ontrol [1:0] r esulting e rrors g enerated by the prbs g enerator 00 no bit error inserted
preliminary XRT86SH328 277 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 0 - unframed prbs: this read/write bit-field is used to configure the transmit ds1 framer block to generate and transmit either a framed or unframed prbs pattern. likewise, th is bit-field also configures the co rresponding receive ds1 framer block to expect either a framed or unframed prbs pattern. ` 0 = transmit and receive ds1 framer block will handle framed prbs pattern. ` 1 = transmit and receive ds1 framer block will handle unframed prbs pattern. bit7 - prbs type: this read/write bit-field is used to specify the type of random pattern that the prbs generator and prbs receiver will handle. ` 0 = a prbs pattern with the polynomial of x^15 + x^14 + 1. ` 1 = a qrts pattern bit6 - error insert: this read/write bit-field is used to configure the prbs ge nerator to insert a single bit-error into the outbound prbs data-stream. ` a 0 to 1 transition, within this bit-field causes the prbs g enerator to insert a single bit-error into the outbound prbs data-stream. bit 5 - data invert: this read/write bit-field is used to (1) configure the pr bs generator to invert all of its outbound traffic (as it generates and transmits this data), and (2) configures the prbs receiver to invert all of the incoming prbs pattern data prior to processing. ` 0 = no inversion by either the prbs generator or the prbs receiver ` 1 = configures inversion by both the prbs generator and prbs receiver bit 4 - receive prbs lock: this read-only bit-field indicates whether or not the prbs receiver is currently declaring prbs lock with the incoming prbs data-stream. ` 0 = prbs receiver is not currently declaring prbs lock. ` 1 = prbs receiver is currently declaring prbs lock. bit 3 - receive prbs detection/generation enable: this read/write bit-field is used to either enable or disable the prbs receiver. ` 0 = disables the prbs receiver 01 1 erred bit per 1,000 bits is inserted 10 1 erred bit per 1,000,000 bits is inserted 11 no bit error inserted t able 412: t1 f ramer b lock - ds1 t est r egister - 1 (a ddress = 0 x n123, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 prbs type error insert data invert receive prbs lock receive prbs enable transmit prbs enable receive ds1 by pass transmit ds1 by pass r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 resulting errors generated by the prbs generator ber c ontrol [1:0] r esulting e rrors g enerated by the prbs g enerator
XRT86SH328 preliminary 278 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ` 1 = enables the prbs receiver bit 2 - transmit prbs generation enable: this read/write bit-field is used to ei ther enable or disable the prbs generator. ` 0 = disables the prbs generator ` 1 = enables the prbs generator bit 1 - receive ds1 by-pass: this bits enables the receive t1 framer bypass mode ` 0 = disabled ` 1 = enables receive framer bypass bit 0 - transmit ds1 by-pass: this bits enables the transmit t1 framer bypass mode ` 0 = disabled ` 1 = enables transmit framer bypass bit [7:6] - receive loop-back code activatio n length[1:0]: these two read/write bit-fields are used to specify the length of the loop- back activation code that the receive ds1 framer block will will use (for code 0). bit [5:4] - receive loop-back co de deactivation length[1:0]: these two read/write bit-fields are used to specify the length of the loop-back deact ivation code that the receive ds1 framer block will use (for code 0). t able 413: t1 f ramer b lock - l oop - back c ode c ontrol r egister - c ode 0(a ddress = 0 x n124, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive loop-back code activation length[1:0] receive loop-back code deactivation length[1:0] transmit loop-back code length[1:0] framed loop-back code loop-back automati - cally r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 receive loop-back code activation length r eceive l oop -b ack c ode a ctivation l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence 10 6 bit sequence 11 7 bit sequence receive loop-back code de-activation length r eceive l oop -b ack c ode d e - activation l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence
preliminary XRT86SH328 279 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [3:2] - transmit loop -back code length[1:0]: these two read/write bit-fields are used to specify the le ngth of the loop-back codes that the transmit ds1 framer block will transmit to the remote terminal equipment anyt ime the user commands it to transmit the user-specified loop- code to the remote terminal equipment.. bit 1 - framed loop-back code: this read/write bit-field is used to configure the transm it ds1 framer and receive ds1 framer blocks to transmit and detect either framed or un-framed loop-codes (for code 0).. ` 0 = configures the transmit ds1 framer block to tran smit loop-codes within an un framed ds1 data-stream, and configures the receive ds1 framer block to dete ct loop-codes within an unframed ds1 data-stream. ` 1 = configures the transmit ds1 framer block to tr ansmit loop-codes within a framed ds1 data-stream, and configures the receive ds1 framer block to dete ct loop-codes within a framed ds1 data-stream. bit 0 - loop-back automatically: this read/write bit-field is used to configure the chann el to operate in the auto loop-back mode. if the user configures the channel to operate in the auto loop-back mode, then all of the following is true. ? the ds1 framer block will automatically enter the remote loop-back mode anytime the receive ds1 framer block detects and validates the loop- up code within the incoming ds1 data-stream. ? the ds1 framer block will automatically exit the re mote loop-back mode anytime the receive ds1 framer block detects and validates the loop-down code within the incoming ds1 data-stream. ` 0 = does not configure the channel to operate in the auto loop-back mode. ` 1 = configures the channel to operate in the auto loop-back mode 10 6 bit sequence 11 7 bit sequence transmit loop-back code length t ransmit l oop -b ack c ode l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence 10 6 bit sequence 11 7 bit sequence t able 414: t1 f ramer b lock - t ransmit l oop - back c ode r egister (a ddress = 0 x n125, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit loop-back code[6:0] transmit loop-back code enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0 receive loop-back code de-activation length r eceive l oop -b ack c ode d e - activation l ength [1:0] l ength
XRT86SH328 preliminary 280 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [7:1] - transmit loop-back code[6:0]: these read/write bit-fields is used to specify the loop -back code that the transmit ds 1 framer block will transmit (to the remote terminal equipment) whenever the user command s it to do so by setting bit 0 (transmit loop-back code enable) to 1, within this register. bit 0 - transmit loop-back code enable: this read/write bit-field is used to command th e transmit ds1 framer block to transmit the loop-back code (which has been written into bits 7 through 1, within this register) to the remote terminal. ` 0 = configures the transmit ds1 framer block to not transmit the loop-back code to the remote terminal equipment. ` 1 = configures the transmit ds1 framer block to transm it the loop-back code to the remote terminal equipment. n ote : the transmit ds1 framer block will repeatedly transmit the loop-back code for the duration that this bit-field is set to 1. bit [7:1] - receive loop-b ack activation code[6:0]: these seven (7) read/write bit-fields are used to specify/ define one of the threee possible loop-code patterns that the receive ds1 framer block should respond to, and interpret as being the loop-up (or loop-back activate) code. n otes : 1. these read/write bit-fields are only active if bi t 0 (receive activation loop-back code detect enable) has been set to 1. 2. the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 0". bit 0 - receive activation loop-back code detect enable: this read/write bit-field is used to either enable or di sable the receive ds1 framer block for loop-back activation code detection for code 0. if the user enables the rece ive ds1 framer block for loop-back activation code detection for code 0, then the receive ds1 framer block (as it is receiving its incoming ds1 data-stream) will also begin to check the incoming ds1 data-stream for the pr esence of the loop-back activation code (which has been defined in bits 7 through 1 within this particular register). ` 0 = configures the receive ds1 framer block to not che ck the incoming ds1 data-stream for the presence of the loop-back activation code. ` 1 = configures the receive ds1 framer block to check t he incoming ds1 data-stream fo r the presence of the loop- back activation code. t able 415: r eceive t1 f ramer b lock - r eceive l oop - back a ctivation c ode r egister - c ode 0 (a ddress = 0 x n126, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive loop-back activation code[6:0] receive acti - vation loop- back code detect enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
preliminary XRT86SH328 281 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:1] - receive loop-bac k deactivation code[6:0]: these seven (7) read/write bit-fields are used to specif y/define one of the three possibl e loop-code pattern that the receive ds1 framer block should respond to, and interpret as being the loop-down (or loop-back deactivate) code. n otes : 1. these read/write bit-fields are only active if bit 0 (receive deactivation loop-back code detect enable) has been set to 1. 2. the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as co de 0, code 1"and code 2 within this document. this particular register applies to "ode 0. bit 0 - receive deactivation lo op-back code detect enable: this read/write bit-field is used to either enable or disable the receive ds1 framer block for loop-back deactivation code detection for code 0. if the user e nables the receive ds1 framer block for loop-back deactivation code detection for code 0, then the receive ds1 framer bloc k (as it is receiving its incoming ds1 data-stream) will also begin to check the incoming ds1 data-stream for th e presence of the loop-back deactivation code (which has been defined in bits 7 through 1 within this particular register). ` 0 = configures the receive ds1 framer block to not che ck the incoming ds1 data-stream for the presence of the loop-back deactivation code. ` 1 = configures the receive ds1 framer block to check t he incoming ds1 data-stream fo r the presence of the loop- back deactivation code. page 695 of word bits [7:6] - receive loop-back code activation length[1:0]: these two read/write bit-fields permit the user to specify the length of t he "loop-back activation" code that the receive ds1 framer block will use (for code 1), as depicted below in table _. t able 416: r eceive t1 f ramer b lock - r eceive l oop -b ack d eactivation c ode r egister - c ode 0 (a ddress = 0 x n127, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 receive loop-back deactivation code[6:0] receive deactivation loop-back code detect enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0 t able 417: t1 f ramer b lock - l oop - back c ode c ontrol r egister - c ode 1 (a ddress = 0 x n12a, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive loop-back code activation length[1:0] receive loop-back code deactivation length[1:0] unused framed loop-back code unused r/w r/w r/w r/w r/o r/o r/w r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 282 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits [5:4] - receive loop-back code deactivation length[1:0]: these two read/write bit-fields permit the user to specify the length of the "loop-back deactivation" code that the receive ds1 framer block will use (for code 1), as depicted below in table _. bits [3:2] - reserved: bit 1 - framed loop-back code: this read/write bit-field permits the user to configure the transmit ds1 framer and receive ds1 framer blocks to transmit and detect either "framed" or "un-fram ed" loop-codes (for code 1), as depicted below. ` 0 = configures the transmit ds1 framer block to tran smit loop-codes within an "u nframed" ds1 data-stream, and configures the receive ds1 framer block to detect loop-codes within an "unframed" ds1 data-stream. ` 1 = configures the transmit ds1 framer block to tran smit loop-codes within a "fra med" ds1 data-stream, and configures the receive ds1 framer block to dete ct loop-codes within a "framed" ds1 data-stream. bit 0 - reserved: bits [7:1] - receive loop-back activation code[6:0]: these seven (7) read/write bit-fields are used to specify/define one of the three possible "loop-code" patterns that the receive ds1 framer block should respond to, and interpret as being the "loop-up" (or loop-back activate) code. notes: r eceive l oop -b ack c ode a ctivation l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence 10 6 bit sequence 11 7 bit sequence r eceive l oop -b ack c ode d e - activation l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence 10 6 bit sequence 11 7 bit sequence t able 418: r eceive t1 f ramer b lock - r eceive l oop - back a ctivation c ode r egister - c ode 1 (a ddress = 0 x n12b, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive loop-back activation code[6:0] receive activation loop-back code detect enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
preliminary XRT86SH328 283 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n otes : 1. these read/write bit-fields are only active if bit 0 (receive activation loop-back code detect enable) has been set to "1". 2. the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 1". bit 0 - receive activation loop-back code detect enable: this read/write bit-field permits the user to either enab le or disable the receive ds1 framer block for "loop-back activation" code detection for "code 1". if the user enables the receive ds1 framer block for "loop-back activation" code detection (for code 1), then the re ceive ds1 framer block (as it is receiving its incoming ds1 data-stream) will also begin to check the incoming ds1 data-stream for the pr esence of the "loop-back activation" code (which has been defined in bits 7 through 1 withi n this particular register). ` 0 = configures the receive ds1 framer block to not che ck the incoming ds1 data-stream for the presence of the "loop-back activation" code. ` 1 = configures the receive ds1 framer block to check t he incoming ds1 data-stream fo r the presence of the "loop- back activation" code. bits [7:1] - receive loop-back deactivation code[6:0]: these seven (7) read/write bit-fields permits the user to specify/define one of the three possible "loop-code" patterns that the receive ds1 framer block should respond to, and interpret as being the "loop-down" (or loop-back deactivate) code. n otes : 1. these read/write bit-fields are only active if bit 0 (receive deactivation loop-back code detect enable) has been set to "1". 2. the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 1". bit 0 - receive deactivation loop-back code detect enable: this read/write bit-field permits the user to either enab le or disable the receive ds1 framer block for "loop-back deactivation" code detection for "code 1". if the us er enables the receive ds1 framer block for "loop-back deactivation" code detection (for code 1), then the receive ds 1 framer block (as it is receiving its incoming ds1 data- stream) will also begin to check the incoming ds1 data-str eam for the presence of the "loop-back deactivation" code (which has been defined in bits 7 through 1 within this particular register). ` 0 = configures the receive ds1 framer block to not che ck the incoming ds1 data-stream for the presence of the "loop-back deactivation" code. ` 1 = configures the receive ds1 framer block to check t he incoming ds1 data-stream fo r the presence of the "loop- back deactivation" code. t able 419: r eceive t1 f ramer b lock - r eceive l oop -b ack d eactivation c ode r egister - c ode 1 (a ddress = 0 x n12c, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive loop-back deactivation code[6:0] receive deactivation loop-back code detect enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
XRT86SH328 preliminary 284 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits [7:6] - receive loop-back code activation length[1:0]: these two read/write bit-fields permit the user to specif y the length of the "loop-back activation" code that the receive ds1 framer block will use (for code 2), as depicted below in table _. bits [5:4] - receive loop-back code deactivation length[1:0]: these two read/write bit-fields permit the user to specify the length of the "loop-back deactivation" code that the receive ds1 framer block will use (for code 2), as depicted below in table _. bits [3:2] - reserved: bit 1 - framed loop-back code: this read/write bit-field permits the user to configure the transmit ds1 framer and receive ds1 framer blocks to transmit and detect either "framed" or "un-fram ed" loop-codes (for code 2), as depicted below. ` 0 = configures the transmit ds1 framer block to tran smit loop-codes within an "u nframed" ds1 data-stream, and configures the receive ds1 framer block to detect loop-codes within an "unframed" ds1 data-stream. ` 1 = configures the transmit ds1 framer block to tran smit loop-codes within a "fra med" ds1 data-stream, and configures the receive ds1 framer block to dete ct loop-codes within a "framed" ds1 data-stream. bit 0 - reserved: t able 420: t1 f ramer b lock - l oop - back c ode c ontrol r egister - c ode 2 (a ddress = 0 x n12d, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive loop-back code activation length[1:0] receive loop-back code deactivation length[1:0] unused framed loop-back code unused r/w r/w r/w r/w r/o r/o r/w r/o 0 0 0 0 0 0 0 0 r eceive l oop -b ack c ode a ctivation l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence 10 6 bit sequence 11 7 bit sequence r eceive l oop -b ack c ode d e - activation l ength [1:0] l ength 00 4 bit sequence 01 5 bit sequence 10 6 bit sequence 11 7 bit sequence
preliminary XRT86SH328 285 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bits [7:1] - receive loop-back activation code[6:0]: these seven (7) read/write bit-fields permits the user to specify/define one of the three possible "loop-code" patterns that the receive ds1 framer block should respond to, and interpret as being the "loop-up" (or loop-back activate) code. n otes : 1. these read/write bit-fields are only active if bit 0 (receive activation loop-back code detect enable) has been set to "1". 2. the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 2". bit 0 - receive activation loop-back code detect enable: this read/write bit-field permits the user to either enab le or disable the receive ds1 framer block for "loop-back activation" code detection for "code 2". if the user enables the receive ds1 framer block for "loop-back activation" code detection (for code 2), then the re ceive ds1 framer block (as it is receiving its incoming ds1 data-stream) will also begin to check the incoming ds1 data-stream for the pr esence of the "loop-back activation" code (which has been defined in bits 7 through 1 withi n this particular register). ` 0 = configures the receive ds1 framer block to not che ck the incoming ds1 data-stream for the presence of the "loop-back activation" code. ` 1 = configures the receive ds1 framer block to check t he incoming ds1 data-stream fo r the presence of the "loop- back activation" code. bits [7:1] - receive loop-back deactivation code[6:0]: these seven (7) read/write bit-fields permits the user to specify/define one of the three possible "loop-code" patterns that the receive ds1 framer block should respond to, and interpret as being the "loop-down" (or loop-back deactivate) code. n otes : 1. these read/write bit-fields are only active if bit 0 (receive deactivation loop-back code detect enable) has been set to "1". t able 421: r eceive t1 f ramer b lock - r eceive l oop - back a ctivation c ode r egister - c ode 2 (a ddress = 0 x n12e, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive loop-back activation code[6:0] receive activation loop-back code detect enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0 t able 422: r eceive t1 f ramer b lock - r eceive l oop -b ack d eactivation c ode r egister - c ode 2 (a ddress = 0 x n12f, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive loop-back deactivation code[6:0] receive deactivation loop-back code detect enable r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
XRT86SH328 preliminary 286 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 2. the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 2". bit 0 - receive deactivation loop-back code detect enable: this read/write bit-field permits the user to either enab le or disable the receive ds1 framer block for "loop-back deactivation" code detection for "code 2". if the us er enables the receive ds1 framer block for "loop-back deactivation" code detection (for code 2), then the receive ds 1 framer block (as it is receiving its incoming ds1 data- stream) will also begin to check the incoming ds1 data-str eam for the presence of the "loop-back deactivation" code (which has been defined in bits 7 through 1 within this particular register). ` 0 = configures the receive ds1 framer block to not che ck the incoming ds1 data-stream for the presence of the "loop-back deactivation" code. ` 1 = configures the receive ds1 framer block to check t he incoming ds1 data-stream fo r the presence of the "loop- back deactivation" code. bit [7:6] - reserved. bit [5:4] - transmit zero suppression[1:0]: bit [3:0] - transmit ch annel conditioning[3:0]: these read/write bit-fields are used to specify how time-s lot # 0 (within the transmit ds1 signal is conditioned or modified). t able 423: t1 f ramer b lock - t ransmit c hannel c ontrol r egister - t1 t ime s lot # 0 (a ddress = 0 x n300, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved transmit zero suppres - sion[1:0] transmit channel conditioning[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 transmit channel conditioning t ransmit c hannel c onditioning [3:0] r esulting c onditioning of t ime -s lot # 0 0000 the input pcm data is unchanged (normal operation) 0001 all 8-bits of the pcm data are inverted 0010 the even bits of the pcm data are inverted 0011 the odd bits of the pcm data are inverted 0100 pcm data is replaced with user code data 0101 pcm data is replaced with the busy code (0x7f) 0110 pcm data is replaced with the vacant code (0xff) 0111 pcm data is replaced with the busy time -slot pattern (0xe0 in the case of time-slot # 0). 1000 pcm data is replaced with the mux ou t of frame (moof) pattern (0x1a).
preliminary XRT86SH328 287 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit [7:0] lapd buffer 0: this register is used to transmit and receive lapd messa ges within buffer 0 of the hd lc controller. users should determine the next available bu ffer by reading the bufaval bi t (bit7 of the transmit data link byte count register 0xn114h). if buffer 0 is available, writing to buffer 0 will in sert the message into the outgoing lapd frame after the lapd message is sent and the data from the transmit buffer cannot be retrieved. after detecting the receive end of transfer interrupt (rxeot), users should read the rbufptr bit (bit 7 of the receive data link byte count register 0xn115h) to determine which buffer contains the received lapd message ready to be read. if rbufptr bit indicates that buffer 0 is available to be r ead, reading buffer 0 continuous ly will retrieve the entire received lapd message. n ote : when writing to or reading from buffer 0, the register is automatically incremented su ch that the entire 64 byte lapd message can be written into or read from buffer 0 continuously. bit [7:0] lapd buffer 1: this register is used to transmit and receive lapd messa ges within buffer 1 of the hd lc controller. users should determine the next available bu ffer by reading the bufaval bi t (bit7 of the transmit data link byte count register 0xn114h). if buffer 1 is available, writing to buffer 1 will in sert the message into the outgoing lapd frame after the lapd message is sent and the data from the transmit buffer cannot be retrieved. after detecting the receive end of transfer interrupt (rxeot), users should read the rbufptr bit (bit 7 of the receive data link byte count register 0xn115h) to determine which buffer contains the received lapd message ready to be read. if rbufptr bit indicates that buffer 1 is available to be r ead, reading buffer 1 continuous ly will retrieve the entire received lapd message. n ote : when writing to or reading from buffer 1, the register is automatically incremented su ch that the entire 64 byte lapd message can be written into or read from buffer 1 continuously. t able 424: t1 f ramer b lock - lapd b uffer 0 c ontrol r egister (a ddress = 0 x n600 - 0 x n640, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lapd buffer 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 425: t1 f ramer b lock - lapd b uffer 1 c ontrol r egister (a ddress = 0 x n700 - 0 x n740, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lapd buffer 1 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 288 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - auxp pattern state: this read-only register bit indicates whether or not t he receive ds1 framer block is currently detecting the auxp pattern within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block is not currently detecting the auxp pattern within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 framer block is curr ently detecting the auxp pattern within the incoming ds1 data-stream. bit6 - change of auxp state interrupt status: this reset-upon-read bit-field indicates whether or not the receive ds1 framer block has declared the change of auxp state interrupt since the last read of this register . the receive ds1 framer bl ock will generate the change of auxp state interrupt in response to either of the following conditions. ? whenever it begins to detect the auxp pattern within the incoming ds1 data-stream, and ? whenever it ceases to detect the auxp pa ttern within the incoming ds1 data-stream. ` 0 = indicates that the change of auxp status interrupt has not occurred sinc e the last read of this register. ` 1 = indicates that the change of auxp status interrupt has occurred since the last read of this register.r bit 5 - crc-4 to non-crc-4 internetworking status: bit 4 - change of crc-4 to no n-crc-4 internetworking status: bit 3 - receive loop-back activation status -code 0: this read-only bit-field indicates whet her or not the receive ds1 framer bloc k is currently detecting (and flagging) the loop-up (or loop-back activate) code (associated wi th "code 0") within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block is not currently detecting (nor flagging) the loop-back activate code (associated with "code 0") within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 framer block is curr ently detecting (and flagging) the loop-back activate code (associated with "code 0") within the incoming ds1 data-stream. n ote : the receive ds1/e1 framer block can be configured to detect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 0". bit 2 - receive loop-back deactivation status - code 0: this read-only bit-field indicates whet her or not the receive ds1 framer bloc k is currently detecting (and flagging) the loop-down (or loop-back deactivate) code (associated with code 0) within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 fram er block is not currently detecting (nor flagging) the loop-back deactivate code (associated with "code 0") within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 framer block is current ly detecting (and flagging) the loop-back deactivate code (associated with "code 0") within the incoming ds1 data-stream. bit 1 - change of receive loop-back acti vation state interrupt status - mcode 0: t able 426: t1 f ramer i nterrupt r egister - r eceive l oop - back c ode i nterrupt and s tatus r egister - c ode 0 (a ddress = 0 x nb0a, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 auxp pattern state change of auxp state interrupt status crc-4 to non crc-4 inter-net - working status change of crc-4 to non-crc-4 inter-net - working sta - tus receive loop-back activation status -code 0 receive loop-back deactivation status -code 0 change of receive loop-back activation state interrupt status -code 0 change of receive loop-back deactivation state i nterrupt status -code 0 r/o rur r/o rur r/o r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 289 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications this reset-upon-read bit-field indicates whether or no t the receive ds1 framer block has generated the change of receive loop-back activation state interr upt, since the last read of this regi ster. the receive ds1 framer block will generate the change of receive loop-back activation state inte rrupt in response to either of the following events. ? whenever the receive ds1 framer bl ock detects (and validates) the loop-back activate code (associated with code 0) within the incoming ds1 data-stream ? whenever the receive ds1 framer block ceases to detect the loop-back activate code (associated with code 0) within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block has not generated the change of receive loop-back activation state interrupt for code 0 since t he last read of this register. ` 1 = indicates that the receive ds1 framer block has gene rated the change of receive loop-back activation state interrupt for code 0 since the last read of this register. bit 0 - change of receive loop-back deactivation status interrupt status: this reset-upon-read bit-field indicates whether or no t the receive ds1 framer block has generated the change of receive loop-back deactivation state in terrupt (based upon loop-code code 0), since the last read of this register. the receive ds1 framer block will generate the change of receive loop-back deactivation state interrupt in response to either of the following events. ? whenever the receive ds1 framer block detect s (and validates) the loop-back deactivate code (associated with code 0) within the incoming ds1 data-stream ? whenever the receive ds1 framer block ceases to detect the loop-back deactivate code (associated with code 0) within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block has no t generated the change of receive loop-back deactivation state interrupt for code 0 since t he last read of this register. ` 1 = indicates that the receive ds1 framer block has gener ated the change of receive loop-back deactivation state interrupt for code 0 since the last read of this register. bit7 - reserved: bit6 - change of auxp state interrupt enable: this read/write bit-field is used to either enable or dis able the change of auxp state inte rrupt. if the user enables the change of auxp state interrupt, then the receive ds 1 framer block will generate the change of auxp state interrupt in response to the following events. ? whenever it begins to detect the auxp pattern within the incoming ds1 data-stream, and ? whenever it ceases to detect the auxp patt ern within the incoming ds1 data-stream. ` 0 = disables the change of auxp state interrupt. ` 1 = enables the change of auxp state interrupt bit 5 - reserved bit 4 - change of crc-4 to non-crc-4 internetworking status interrupt enable: t able 427: t1 f ramer i nterrupt r egister - r eceive l oop -b ack c ode i nterrupt e nable r egister - c ode 0 (a ddress = 0 x nb0b, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved change of auxp state interrupt enable reserved change of crc-4 to non-crc-4 inter-net - working state interrupt enable reserved change of receive loop-back activation interrupt enable - code 0 change of receive loop-back deactivation interrupt enable - code 0 r/o r/w r/o r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 290 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [3:2] - reserved bit 1 - change of receive loop-back activation interrupt enable - code 0: this read/write bit-field is used to either enable or disable the change of receive loop-back activation state interrupt, associated with code 0. if the user enables the change of receive loop-back activation state interrupt, then the receive ds1 framer block will generate the change of receive loop-back activation state interrupt in response to the following events. ? whenever it detects and validates the receive loop-back activation pattern (associated with code 0) within the incoming ds1 data-stream, and ? whenever it ceases to detect the receive loop-back activation pattern (associated with code 0) within the incoming ds1 data-stream. ` 0 = disables the change of receive loop-back acti vation state interrupt for loop-code code 0. ` 1 = enables the change of receive loop-back acti vation state interrupt for loop-code code 0 bit 0 - change of receive loop-back deactivation interrupt enable -code 0: this read/write bit-field is used to either enable or disable the change of receive loop-back deactivation state interrupt associated with code 0. if the user enables th e change of receive loop-back deactivation state interrupt, then the receive ds1 framer block will generate the change of receive loop-back deactivation state interrupt in response to the following events. ? whenever it detects and validates the receive loop- back deactivation pattern (associated with code 0) within the incoming ds1 data-stream, and ? whenever it ceases to detect the receive loop-back d eactivation pattern (associated with code 0) within the incoming ds1 data-stream. ` 0 = disables the change of receive loop-back deactivation state interrupt for code 0. ` 1 = enables the change of receive loop-back deactivation state interrupt for code 0 page 710 of word bits 7 through 4 - unused: bit 3 - receive loop-back activation status - code 1: this read-only bit-field indicates whet her or not the receive ds1 framer bloc k is currently detecting (and flagging) the loop-up (or loop-back activate) code (associated with c ode 1) within the incoming ds1 data-stream, as depicted below. ` 0 = indicates that the receive ds1 fram er block is not currently detecting (nor flagging) the "loop-back activate" code (associated with "code 1") within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 fr amer block is currently detecting (and flagging) the "loop-back activate" code (associated with "code 1") within the incoming ds1 data-stream. n ote : the receive ds1/e1 framer block can be configured to det ect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 1". t able 428: t1 f ramer i nterrupt r egister - r eceive l oop - back c ode i nterrupt and s tatus r egister - c ode 1 (a ddress = 0 x nb14, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive loop-back activation status - code 1 receive loop-back deactivation status - code 1 change of receive loop-back activation state inter - rupt status - code 1 change of receive loop-back deactivation state inter - rupt status - code 1 r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 291 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 2 - receive loop-back deactivation status - code 1: this read-only bit-field indicates whet her or not the receive ds1 framer bloc k is currently detecting (and flagging) the loop-down (or loop-back deactivate) code (associated with code 1) within the incoming ds1 data-stream, as depicted below. ` 0 = indicates that the receive ds1 framer block is not cu rrently detecting (nor flagging) the "loop-back deactivate" code (associated with "code 1") within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 framer block is curr ently detecting (and flagging) the "loop-back deactivate" code (associated with "code 1") within the incoming ds1 data-stream. bit 1 - change of receive loop-back activation state interrupt status - code 1: this reset-upon-read bit-field indicates whether or not the receive ds1 framer block has generated the "change of receive loop-back activation state" interrupt (based upon l oop-code "code 1"), since the last read of this register. the receive ds1 framer block will generate the "change of re ceive loop-back activation state" interrupt in response to either of the following events. ? whenever the receive ds1 framer block detects (and vali dates) the "loop-back activate" code (associated with "code 1") within the incoming ds1 data-stream ? whenever the receive ds1 framer block ceases to detect the "loop-back activate" code (associated with "code 1") within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 fr amer block has not generated the "change of receive loop-back activation state" interrupt for "code 1" since the last read of this register. ` 1 = indicates that the receive ds1 framer block has generated the "change of receive loop-back activation state" interrupt for "code 1" since the last read of this register. bit 0 - change of receive loop-back deactivation status interrupt status - code 1: this reset-upon-read bit-field indicates whether or not the receive ds1 framer block has generated the "change of receive loop-back deactivation state" interrupt (based upon loop-code "code 1"), since the last read of this register. the receive ds1 framer block will generate the "change of receive loop-back deactivation state" interrupt in response to either of the following events. ? whenever the receive ds1 framer block detects (and valid ates) the "loop-back deactivate" code (associated with "code 1") within the incoming ds1 data-stream ? whenever the receive ds1 framer blo ck ceases to detect the "loop-back de activate" code (associated with "code 1") within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block has not generated the "change of receive loop-back deactivation state" interrupt for "code 1" since the last read of this register. ` 1 = indicates that the receive ds1 framer block has generated the "change of receive loop-back deactivation state" interrupt for "code 1" since the last read of this register. bits 7 through 2 - reserved: bit 1 - change of receive loop-back activation interrupt enable - code 1: this read/write bit-field permits the user to either enable or disable the "change of receive loop-back activation t able 429: t1 f ramer i nterrupt r egister - r eceive l oop -b ack c ode i nterrupt e nable r egister - c ode 1 (a ddress = 0 x nb15, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of receive loop-back activation interrupt enable - code 1 change of receive loop-back deactivation interrupt enable - code 1 r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 292 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 state" interrupt associated with loop-code "code 1". if th e user enables the "change of receive loop-back activation state" interrupt, then the receive ds1 framer block will gene rate the "change of receive l oop-back activation state" interrupt in response to the following events. ? whenever it detects and validates the "receive loop-ba ck activation" pattern (associated with "code 1") within the incoming ds1 data-stream, and ? whenever it ceases to detect the "receive loop-back activation" pattern (associated with "code 1") within the incoming ds1 data-stream. ` 0 = disables the "change of receive loop-back acti vation state" interrupt for loop-code "code 1". ` 1 = enables the "change of receive loop-back activation state" interrupt for loop-code "code 1". bit 0 - change of receive loop-back deactivation interrupt enable - code 1: this read/write bit-field permits the user to either enable or disable the "change of receive loop-back deactivation state" interrupt. if the user enables the "change of receiv e loop-back deactivation state" interrupt, then the receive ds1 framer block will generate the "change of receive loop-back deactivation state" interrupt in response to the following events. ? whenever it detects and validates the "receive loop-back deactivation" pattern (associated with "code 1") within the incoming ds1 data-stream, and ? whenever it ceases to detect the "receive loop-back de activation" pattern (associated with "code 1") within the incoming ds1 data-stream. ` 0 = disables the "change of receive loop-back deactivation state" interrupt for "code 1". ` 1 = enables the "change of receive loop-back deactivation state" interrupt for "code 1". bits 7 through 4 - unused: bit 3 - receive loop-back activation status - code 2: this read-only bit-field indicates whet her or not the receive ds1 framer bloc k is currently detecting (and flagging) the loop-up (or loop-back activate) code (associated with c ode 2) within the incoming ds1 data-stream, as depicted below. ` 0 = indicates that the receive ds1 fram er block is not currently detecting (nor flagging) the "loop-back activate" code (associated with "code 2") within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 fr amer block is currently detecting (and flagging) the "loop-back activate" code (associated with "code 2") within the incoming ds1 data-stream. n ote : the receive ds1/e1 framer block can be configured to det ect three different loop activate/deactivate codes in parallel. these three (3) codes will be referred to as "code 0", "code 1" and "code 2" within this document. this particular register applies to "code 2". bit 2 - receive loop-back deactivation status - code 2: this read-only bit-field indicates whet her or not the receive ds1 framer bloc k is currently detecting (and flagging) the loop-down (or loop-back deactivate) code (associated with code 2) within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block is not cu rrently detecting (nor flagging) the "loop-back deactivate" t able 430: t1 f ramer i nterrupt r egister - r eceive l oop - back c ode i nterrupt and s tatus r egister - c ode 2 (a ddress = 0 x nb1a, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive loop-back activation status - code 2 receive loop-back deactivation status - code 2 change of receive loop-back activation state inter - rupt status - code 2 change of receive loop-back deactivation state inter - rupt status - code 2 r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 293 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications code (associated with "code 2") within the incoming ds1 data-stream. ` 1 = indicates that the receive ds1 framer block is curr ently detecting (and flagging) the "loop-back deactivate" code (associated with "code 2") within the incoming ds1 data-stream. bit 1 - change of receive loop-back activation state interrupt status - code 2: this reset-upon-read bit-field indicates whether or not the receive ds1 framer block has generated the "change of receive loop-back activation state" interrupt (based upon l oop-code "code 2"), since the last read of this register. the receive ds1 framer block will generate the "change of re ceive loop-back activation state" interrupt in response to either of the following events. ? whenever the receive ds1 framer block detects (and vali dates) the "loop-back activate" code (associated with "code 2") within the incoming ds1 data-stream ? whenever the receive ds1 framer block ceases to detect the "loop-back activate" code (associated with "code 2") within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 fr amer block has not generated the "change of receive loop-back activation state" interrupt for "code 2" since the last read of this register. ` 1 = indicates that the receive ds1 framer block has generated the "change of receive loop-back activation state" interrupt for "code 2" since the last read of this register. bit 0 - change of receive loop-back deactivation status interrupt status - code 2: this reset-upon-read bit-field indicates whether or not the receive ds1 framer block has generated the "change of receive loop-back deactivation state" interrupt (based upon loop-code "code 2"), since the last read of this register. the receive ds1 framer block will generate the "change of receive loop-back deactivation state" interrupt in response to either of the following events. ? whenever the receive ds1 framer block detects (and valid ates) the "loop-back deactivate" code (associated with "code 2") within the incoming ds1 data-stream ? whenever the receive ds1 framer blo ck ceases to detect the "loop-back de activate" code (associated with "code 2") within the incoming ds1 data-stream. ` 0 = indicates that the receive ds1 framer block has not generated the "change of receive loop-back deactivation state" interrupt for "code 2" since the last read of this register. ` 1 = indicates that the receive ds1 framer block has generated the "change of receive loop-back deactivation state" interrupt for "code 2" since the last read of this register. bits 7 through 2 - reserved: bit 1 - change of receive loop-back activation interrupt enable - code 2: this read/write bit-field permits the user to either enable or disable the "change of receive loop-back activation state" interrupt associated with loop-code "code 2". if th e user enables the "change of receive loop-back activation state" interrupt, then the receive ds1 framer block will gene rate the "change of receive l oop-back activation state" interrupt in response to the following events. ? whenever it detects and validates the "receive loop-back activation" pattern (associated with "code 2") within the incoming ds1 data-stream, and t able 431: t1 f ramer i nterrupt r egister - r eceive l oop -b ack c ode i nterrupt e nable r egister - c ode 2 (a ddress = 0 x nb1b, where n ranges in value from 0 x 01 to 0 x 38) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of receive loop-back activation interrupt enable - code 2 change of receive loop-back deactivation interrupt enable - code 2 r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 294 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 ? whenever it ceases to detect the "receive loop-back activation" pattern (associated with "code 2") within the incoming ds1 data-stream. ` 0 = disables the "change of receive loop-back acti vation state" interrupt for loop-code "code 2". ` 1 = enables the "change of receive loop-back activation state" interrupt for loop-code "code 2". bit 0 - change of receive loop-back deactivation interrupt enable - code 2: this read/write bit-field permits the user to either enable or disable the "change of receive loop-back deactivation state" interrupt. if the user enables the "change of receiv e loop-back deactivation state" interrupt, then the receive ds1 framer block will generate the "change of receive loop-back deactivation state" interrupt in response to the following events. ? whenever it detects and validates the "receive loop-back deactivation" pattern (associated with "code 2") within the incoming ds1 data-stream, and ? whenever it ceases to detect the "receive loop-back de activation" pattern (associated with "code 2") within the incoming ds1 data-stream. ` 0 = disables the "change of receive loop-back deactivation state" interrupt for "code 2". ` 1 = enables the "change of receive loop-back deactivation state" interrupt for "code 2". 2.14 ds1/e1 framer block registers - e1 applications bit7 - reserved bit6 - set t1 mode: this read/write bit-field is used to configure the channel to operate in either the t1 or e1 mode. ` 0 = configures the framer channel to operate in the e1 mode ` 1 = configures the framer channel to operate in the t1 mode bit 5 - force all channels to sync to 8khz: this read/write bit-field is used to c onfigure all active (either 21 or 42) transmit e1 fr amer blocks to synchronize their transmit output frame ali gnment with the 8khz signal that is derived from the mclk pll. ` 0 = does not configure each of the transmit e1 framer blocks to synchronize their tr ansmit output fr ame alignment with the 8khz signal (from the mclk pll). ` 1 = configures each of the transmit e1 framer blocks to synchronize their transmit output frame alignment with the 8khz signal (from the mclk pll). n ote : this feature should only be used if the XRT86SH328 has been configured to operate in the 21-channel e1 framer/liu combo mode. the user must not use this feature if the XRT86SH328 has been configured to operate in any of the aggregation modes. bit [4:2] - reserved bit [1:0] - clock source select[1:0]: these two read/write bit-fields is used to specify the timing source for the ingress and direction transmit e1 framer block, within this particular channel. t able 432: e1 f ramer b lock - c lock s elect r egister (a ddress = 0 x n100, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused set e1 mode force all channels to sync to 8khz unused clock source select[1:0] r/o r/w r/w r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 1
preliminary XRT86SH328 295 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 - transmit los pattern: this read/write bit-field configures the transmit e1 fr amer block to generate and transmit the los pattern to the remote terminal. ` 0 = configures the transmit e1 framer block to transmit normal e1 traffic ` 1 = configures the transmit e1 framer block to transmit the los pattern. n ote : the user must set this bit-field to 0 for normal operation. bit6 - reserved bit [5:4] - framer loop-back[1:0]: these two read/write bit-fields are us ed to configure the transmit/receive e1 framer blocks to operate in a variety of possible loop-back modes, as depicted in the table below. the relationship between the clock source select[1 :0] bit-fields and the re sulting timing source for the transmit e1 framer block, within this particular channel c lock s ource s elect [1:0] t iming s ource for t ransmit e1 f ramer b lock 00 loop-timing mode:the transmit e1 framer blo ck will derive its timing from the received or recovered clock signal within the corresponding receive e1 framer block n ote : this timing option is only available if the user has configured the XRT86SH328 to operate in the 21-channel e1 framer/liu combo mode 01 local-timing mode (txe1clk_n input)the transmit e1 framer block will either use up- stream timing or the txe1clk_n input as its timing source. n ote : for aggregation applications, the user mu st configure all active t1/e1 framer blocks to operate in this timing mode. 10 local-timing mode (mclk pll input)the transmi t e1 framer block will derive its timing from the mclk pll.note: this timing option is only available if the user has configured the XRT86SH328 to operate in the 21- channel e1 framer/liu combo mode. 11 loop-timing modethe transmit e1 framer block will derive its timing from the received or recovered clock signal within the corresponding receive e1 framer block n ote : this timing option is only available if the user has configured the XRT86SH328 to operate in the 21-channel e1 framer/liu combo mode. t able 433: e1 f ramer b lock - l ine i nterface c ontrol r egister (a ddress = 0 x n101, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit los pattern reserved framer loop- back[1:0] reserved r/w r/o r/w r/w r/o r/o r/o r/o 0 1 0 0 0 0 0 0 relationship between the framer loop-back[1:0] bit-fields and the corresponding loop-back mode within the e1 framer block f ramer l oop - back [1:0] r esulting l oop -b ack m ode ( within f ramer b lock ) 00 normal operation (no loop-back) mode 01 local loop-back mode
XRT86SH328 preliminary 296 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - g.706 annex b crc-4 calculation enable: this bit configures the e1 receive framer block to be compliant with itu-t g.706 annex b for crc-to-non-crc interworking detection. if annex b is enabled, g.706 annex b crc-4 multi frame alignment algorithm is implemented. if crc-4 alignment is enabled and not achieved in 400 msec while the basic frame alignment signal is present, it is assumed that the remote end is a non crc-4 equipment. a crc-to-non-crc interworking interrupt will be generated. ` 0 = configures the receive e1 framer block to not support the g.706 annex b crc-4 multi frame alignment algorithm. ` 1 = configures the receive e1 framer block to suppor t the g.706 annex b crc-4 multi frame alignment algorithm. bit6 - transmit crc-4 error: this bit is used to force a continuous errored crc pa ttern in the outbound crc mu lti frame to be sent on the transmission line. the transmit e1 framer block will implement this error by inverting the value of crc bit (c1). ` 0 = disabled ` 1 = forces the transmit e1 framer block to transmit continuous errored crc bit. bit [5:4] - cas multi frame select[1:0]: these bits allow the user to select wh ich cas multi frame alignment declaration algorithm the receive e1 framer block will employ, according to the table below. 10 remote loop-back mode 11 reserved t able 434: e1 f ramer b lock - f raming s elect r egister (a ddress = 0 x n107, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 annex b tx crc-4 error cas multiframe sel[1:0] crc multiframe sel[1:0] add frame chkenable fas frame alignment r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 e1 framer block - framing select register (address = 0xn107, where n ranges in value from 0x01 to 0x38) cas mf a lign s el [1:0] cas m ulti f rame a lignment d eclaration a lgorithm s elected 00, 11 cas multi frame alignment disabled. 01 the 16-frame algorithmif this alignment al gorithm is selected, then the receive e1 framer block will monitor the 16th timeslot of each incoming e1 frame and will declare cas multi frame alignment (e.g., clear the loss of cas multi frame defect) condition anytime that it detects 15 consecutive e1 frames in which bits 1-4 (of time slot 16) do not contain the cas multi fr ame alignment pattern, which is immedi - ately followed by an e1 frame that does contain the cas multi frame alignment pattern. 10 the 2-frame (itu-t g.732) algorithmif this alignment algorithm is selected, then the receive e1 framer block will declare cas multi frame ali gnment anytime it detects a single e1 frame rather than 15 consecutive e1 frames as described above in the 16-frame algorithm. relationship between the framer loop-back[1:0] bit-fields and the corresponding loop-back mode within the e1 framer block f ramer l oop - back [1:0] r esulting l oop -b ack m ode ( within f ramer b lock )
preliminary XRT86SH328 297 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : for information on the criteria that the receive e1 framer block uses in order to declare the loss of cas multi frame defect condition, please s ee the register description for the framing control register 0xn10bh. bit [3:2] - crc multi frame alignmen t declaration criteria select[1:0]: these bits allow the user to select which crc multi frame alignment declaration criteria the receive e1 framer block will employ. the receive e1 framer block will check for crc multi frame alignmnet by che cking the incoming e1 data stream and determining whether the intern ational bits (bit 1 of time slot 0) of non-fas frames match the crc multi frame alignment pattern (0,0,1,0,1,1,e1,e2). n ote : for information on the criteria that the receive e1 framer block uses to declare the loss of crc multi frame alignment defect condition, please see the register description for t he framing control register 0xn10bh. bit 1 - additional frame check enable - fas frame alignment declaration: this bit is used to configure the receiv e e1 framer block to perform some additional fas frame synchronization checking prior to declaration fas frame alignment. if the user implem ents this feature, then the re ceive e1 framer block will perform some more testing on two additional e1 frames , prior to declaring the fas frame alignment condition. ` 0 = disabled. ` 1 = enables additional fas frame checking. bit 0 - fas alignment declaration algorithm select: this bit specifies which algorithm the receive e1 fram er block uses in its search for the fas alignment. ` 0 = fas alignment algorithm 1 ` 1 = fas alignment algorithm 2 fas alignment algo rithm 1 desciption a. step 1: the receive e1 framer block begins by searchin g for the correct 7-bit fas pattern. go to step 2 if found. b. step 2: check if the fas is absent in the following fram e by verifying that bit 2 of the assumed time slot 0 of the non-fas frame is a one. go back to step 1 if failed, otherwise go to step 3. c. step 3: check if the fas is present in the assumed time slot 0 of the third frame. go back to step 1 if failed. after the first three steps (if all passed), the receive e1 fr amer block will declare fas in sync if frame check sequence (bit 1 of this register) is disabled. if frame check sequence is enabled, then the receive e1 framer block will need to verify the correct frame alignment. fas alignment algori thm 2 description algorithm 2 is similar to algorithm 1 but adds a one-frame hold off time after the second step fails. after the second step fails, it waits for the next a ssumed fas in the next frame before it begins the new search for th e correct fas pattern. cas mf align sel cas mf a lign s el [1:0] cas m ulti f rame a lignment d eclaration a lgorithm c riteria 00 crc multi frame alignment disabled. 01 crc multi frame alignment is enabled. alignment is declared if at least 1 valid crc multi frame alignment signal is observed within 8 msec. 10 crc multi frame alignment is enabled. alignment is declared if at least 2 valid crc multi frame alignment signals are observed within 8 msec. 11 crc multi frame alignment is enabled. alignment is declared if at least 3 valid crc multi frame alignment signals are observed within 8 msec.
XRT86SH328 preliminary 298 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - transmit auxiliary pattern: this bit is used to transmit an auxiliary patter n (repeating ?010101) to the transmit line interface. ` 0 = disabled ` 1 = enable auxp pattern bit6 - loss of frame declaration criteria this bit is used to select loss of frame declar ation criteria for the receive e1 framer block. ` 0 = loss of frame is declared immediately if either crc multi frame alignment or fas alignment is lost. ` 1 = loss of frame is declared immediately if fas alignment is lost. if crc multi frame alignment is lost for more than 8 msec, the e1 receive framer will force a frame search. bit [5:4] - yellow alarm and mult i yellow alarm generation [1:0]: these bits activate or deactivate the transmission of yellow and multi frame yellow alarm. the yellow alarm and multi frame yellow alarm can be forced to transmit as 1, or be inserted upon detection of loss of alignment. bit [3:2] - transmit ais pattern select[1:0] these two read/write bit-fields are used to select the ty pe of ais pattern that the transmit e1 framer block will send if enabled. t able 435: e1 f ramer b lock - a larm g eneration r egister (a ddress = 0 x n108, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmi - tauxp pat - tern lof decla - rationcriteria transmit yel and multi yel[1:0] transmit ais pattern select[1:0] ais defect declaration cri - teria[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 yel and multi ye yel and m ulti yel[1:0] y ellow a larm t ransmitted 00 / 10 disabled. 01 automatic transmission of yel and cas multi yelwhenever the receive e1 framer block declares lof or loss cas multi frame alignment, the corresponding transmit e1 framer block wi ll automatically transmit the yellow alarm indicator by setting bit 3 of time slot 0 within the non-fas frames to 1. 11 force transmission of yel and cas multi yelboth yellow and multi frame yel - low alarm are transmitted as '1' the relationship between transmit ais pattern select[1:0] and the resulting behavior of the transmit e1 framer block t ransmit ais p attern s elect [1:0] t ransmit e1 f ramer b lock a ction 00 transmits normal traffictransmit e1 framer bl ock does not transmit the ais indicator. it will (instead) transmit normal traffic 01 unframed all ones patternthe transmit e1 framer block will transmit an unframed all ones pattern (as an ais pattern) for the duration that these bit-fields are set to [0, 1].
preliminary XRT86SH328 299 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[1:0] - ais defect declaration criteria[1:0] these two read/write bit-fields are used to select the type of ais pattern that the receive e1 framer block will look for in order to determine whether or not it should declare or clear the ais defect condition. bit [7:6] - e-bit source select ? these bits are used to specify the source of e-bits wihin each outbound e1 frame. 10 the ais-16 patternin this case, time slot 16 in each frame will be set to an all ones pattern. 11 framed all ones patternthe transmit e1 framer block will transmit a framed all ones pattern (as an ais pattern) for the durat ion that these bit-fields are set to [1, 0]. the relationship between ais defect declaration criteria[1:0] and the resulting ais pattern that the receive e1 framer block will look for in declaring/clearing the ais defect condition ais d efect d eclaration c riteria [1:0] r eceive e1 f ramer b lock - ais d efect d eclaration c riteria 00 ais defect declaration is disabledthe receive e1 framer block will not declare the ais defect condition at all. 01 unframed and framed all ones pattern:the receive e1 framer block will declare the ais defect cond ition whenever it receives either the framed or unframed all ones pattern for at least 42ms. 10 ais-16 all ones pattern:the receive e1 framer block will declare the ais defect condition whenever it receives all ones in the 16th time slot. 11 framed all ones pattern:the receive e1 framer block will only declare the ais defect condition whenever it receives the framed all ones pattern for at least 42ms. t able 436: e1 f ramer b lock - s ynchronization mux r egister (a ddress = 0 x n109, where n ranges in value from 0 x 01 to 0 x 38) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e-bit sourceselect reserved data link sourceselect crc-4 source select framing alignment pattern select r/o r/w r/w r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0 e-bits e- bits [1:0] e-b it s ource s elect 00 internal framer blockthe e-bits are used to indicate whether the receive e1 framer block has detected a crc error within the most recently received sub-multi frame. the receive e1 framer will indicate a received errored sub-multi frame by setting the binary state of the e-bits from 1 to 0 for each errored sub-multi frame. the relationship between transmit ais pattern select[1:0] and the resulting behavior of the transmit e1 framer block t ransmit ais p attern s elect [1:0] t ransmit e1 f ramer b lock a ction
XRT86SH328 preliminary 300 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit [5:4] - reserved bit [3:2] - data li nk source select these bits are used to specify the so urce of the data link bits that will be inserted in the outbound e1 frames. bit 1 - crc-4 source select bit 0 - framing alig nment pattern select 2.15 channel control-vt mapper block registers the register map for the channel control vt-mapper block registers is presented in the table below. additionally, a detailed description of each of the chan nel control vt-mapper bloc k registers is presented below. in order to provide some orientatio n for the reader, an illustration of th e functional block diagram for the XRT86SH328, with both the vt/tu mapper and vt/tu de-mapper blocks highlighted is presented below in figure 19 . 01 all e-bits within the outbound e1 data stream are set to 0. 10 all e-bits within the outbound e1 data stream are set to 1. 11 the e-bits are used to carry the data link information. yel and multi yel yel and m ulti yel[1:0] y ellow a larm t ransmitted 00 / 11 the transmit serial input from the transmit payload data input block will be the source for the data link bits. 01 the transmit hdlc controller will generate either bos (bit oriented signaling) or mos (message oriented signaling) messages wh ich will be inserted into the data link bits in the outbound e1 frames. 10 reserved. e-bits e- bits [1:0] e-b it s ource s elect
preliminary XRT86SH328 301 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[7:2] - unused: bit[1:0] - transmit rdi-v type[1:0]: this read/write bit-field is used to specify the source of bits 5, 6 and 7 (within the k4 vt-poh byte), whenever the transmit vt-mapper block is configured to suppor t the transmission of the extended rdi-v indicators. f igure 19. i llustration of the f unctional b lock d iagram of the XRT86SH328 device , with the vt- m apper block highlighted t able 437: c hannel c ontrol - vt-m apper b lock - i ngress d irection ds1/e1 i nsertion c ontrol r egister - 2 (a ddress = 0 x nd41) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused transmit rdi-v source[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 transmit rdi-v source t ransmit rdi-v s ource [1:0] r esulting s ource of b its 5, 6 and 7 of k4 b yte 00 receive status per the corresponding receive vt-mapper block 01 from on-chip register sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0
XRT86SH328 preliminary 302 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - receive (ingress direction) ds1/e1 ais defect declared: this read/write bit-field indicates whether or not the corr esponding ds1 or e1 signal (that is being handled by this transmit vt-mapper block) is transporting the ais indicator. ` 0 - indicates that the ingress direction ds1 or e1 si gnal is not currently transporting the ais indicator. ` 1 - indicates that the ingress direction ds1 or e1 signal is currently transporting the ais indicator. bit 6 - unused bit 5 - bip-2 error insert this read/write bit-field is used to configure the corre sponding vt-mapper block to transmit vts with erred bip-2 bits into the "ingress direction vt-data-stream (towards th e transmit sts-1/sts-3 poh pr ocessor block). if the user opts to invoke this feature, then the vt-mapper block will automatically inve rt the value of the "locally-computed" bip-2 bits (within each outbound vt), prior to transmitting th is data to the transmit sts-1/sts-3 poh processor block. ` 0 - configures the transmit vt-mapper block to not transmit vts with erred bip-2 bits to downstream circuitry (normal operation). ` 1 - configures the transmit vt-mapper bl ock to transmit vts with erred bip-2 bits to downstream circuitry(normal operation). n ote : for normal operation, the user should set this bit-field to 0. bit [4:2] - vt label[2:0]: these three (3) read/write bit-fields are used to set the vt label bit-fields (within each outbound v5 byte) the value of the users choice. bit 1 - auto transm it rfi-v indicator this read/write bit-field is used to select the source of the rfi-v bit-field, within the v5 byte of the outbound vt1.5/vt2 traffic. in this case, the user has the following two options. a. the user can configure the vt-mapper block to use an on- chip register as the source of the rfi-v bit-fields (within the v5 byte). more specifically, the vt-mapper block will read out the contents within bit 7 (transmit rfi-v value) within the "vt-mapper block - ingress dire ction - ds1/e1 insertion control register (address = 0xnd43)" and it will load this value into rfi-v bit-field pos ition within each outbound vt. in this case, the user will have software control over the state of the rfi-v bit-field, wit hin the v5 byte of the outbound vt traffic) or b. the transmit vt-mapper block will set the rfi-v bit-fi elds to the appropriate value, based upon any defect conditions that are currently being declared by the corresponding vt-de-mapper block. ` 0 - configures the transmit vt-mapper block to use the on-chip register as the source of the rfi-v bit-field. 10 do not use 11 receive status per the corresponding receive vt-mapper block t able 438: c hannel c ontrol - vt-m apper b lock - i ngress d irection - ds1/e1 i nsertion c ontrol r egister - 1 (a ddress = 0 x nd42, where n ranges from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ingress direction ds1/e1 ais defect declared unused bip-2 error insert vt signal label[2:0] auto transmit rfi-v indicator auto transmit rdi-v indicator r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 transmit rdi-v source t ransmit rdi-v s ource [1:0] r esulting s ource of b its 5, 6 and 7 of k4 b yte
preliminary XRT86SH328 303 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 1 - configures the transmit vt-mapper block to set the rf i-v bit-fields to the appropriate value, based upon any defects that the corresponding receive vt-mapper block is currently declaring. bit 0 - auto transmit rdi-v indicator this read/write bit-field is used to select the source of the rdi-v bit-field, within the v5 byte of each outbound vt1.5/vt2 traffic. in this case, the user has the following two options. a. the user can configure the transmit vt-mapper block to use an on-chip register as the source of the rdi-v bit-fields (within the v5 byte). more specifically, the transmit vt-mapper block will read out the contents within bit6 (transmit rdi-v value) within the vt mapper block - ingress direction - ds1/e1 insertion control register (address = 0xnd43) and it will load this value into the rdi-v bit-field position within each outbound vt. in this case, the user will have software control over the state of the rdi-v bit-fields, within the outbound vt traffic) or b. the transmit vt-mapper block will set the rdi-v bit-fiel ds to the appropriate value, based upon any defect conditions that are currently being declared by the corresponding vt-de-mapper block. ` 0 - configures the transmit vt-mapper block to use the on-chip register as the source of the rdi-v bit-field. ` 1 - configures the transmit vt-mapper block to set the rd i-v bit-fields to the appropriate value, based upon any defects that the corresponding vt-de -mapper block is currently declaring. bit7 - transmit rfi-v value: this read/write bit-field is used to exercise software cont rol over the state of the rf i-v bit-field (within each v5 byte) of the outbound vt data-stream. if the user sets bi t 1 (auto transmit rfi-v indi cator), within the vt-mapper block - ingress direction - ds1/e1 insertion control register - 2 to 0, then the transmit vt-mapper block will read out the contents within this bit-field, and it will load this valu e into the rfi-v bit-field within each v5 byte of the outbound vt - data-stream. n ote : this bit-field is ignored if the user sets bit 1 (auto transmit rfi-v indicator), within the vt mapper block - ingress direction - ds1/e1 inserti on control register - 1 to 1. bit6 - transmit rdi-v value: this read/write bit-field is used to exercise software cont rol over the state of the rdi-v bit-field (within each v5 byte) of the outbound vt data-stream. if the user sets bit 0 (auto transmit rdi-v indicator), within the vt-mapper block - ingress direction - ds1/e1 insertion control register - 2 to 0, then the transmit vt-mapper block will read out the contents within this bit-field, and it will load this value into the rdi-v bit-field within each v5 byte of the outbound vt-data-stream. n ote : this bit-field is ignored if the user sets bit 0 (auto transmit rdi-v indicator), within the vt mapper block - ingress direction - ds1/e1 inserti on control register - 1 to 1. bit 5 - transmit ais-v indicator this read/write bit-field is used to command the transmit vt-mappper block to transmit the ais-v indicator (within the corresponding vt1.5 or vt2) within the outbound vt-data-stream. 0 - configures the transmit vt-mapper block to not transm it the ais-v indicator withi n the outbound vt-data-stream. 1 - configures the transmit vt-mapper block to transmit the ais-v indicator within the outbound vt -data-stream as shown in figure 20 . t able 439: c hannel c ontrol - vt-m apper b lock - i ngress d irection - ds1/e1 i nsertion c ontrol r egister - 0 (a ddress = 0 x nd43 , where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transmit rfi-v value transmit rdi-v value transmit ais-v indicator ds1/e1 cross connect channel select_ingress direction[4:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 304 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit[4:0] - ds1/e1 (cross-c onnect) channe l select[4:0]: these read/write bit-fields is used to configure the internal vt-cross connect. more specifically, these read/write bit-fields are used to select which (of the 28 i ngress direction) t1/e1 signals to be mapped into either a vt1.5 or vt2 by this particular transmit vt-mapper block. the following table presents the relationship between the settings of these bit-fields and the resulting cross connect configuration. f igure 20. a n i llustration of the f unctional b lock d iagram of the XRT86SH328 whenever the vt- m apper block ( associated with a given channel ) has been configured to transmit the ais-v indicator towards down - stream circuitry cross connect configuration ds1/e1 (c ross - c onnect ) c hannel s elect [4:0] r esulting i ngress d irection t1/e1 c hannel being handled by this particular t ransmit vt-m apper block c omments 00000 none this particular vt will be transmitted as an un-equipped signal 00001 ingress direction t1/e1 channel 1 00010 ingress direction t1/e1 channel 2 00011 ingress direction t1/e1 channel 3 00100 ingress direction t1/e1 channel 4 00101 ingress direction t1/e1 channel 5 sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 ais-v indicator
preliminary XRT86SH328 305 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications 00110 ingress direction t1/e1 channel 6 00111 ingress direction t1/e1 channel 7 01000 ingress direction t1/e1 channel 8 01001 ingress direction t1/e1 channel 9 01010 ingress direction t1/e1 channel 10 01011 ingress direction t1/e1 channel 11 01100 ingress direction t1/e1 channel 12 01101 ingress direction t1/e1 channel 13 01110 ingress direction t1/e1 channel 14 01111 ingress direction t1/e1 channel 15 10000 ingress direction t1/e1 channel 16 10001 ingress direction t1/e1 channel 17 10010 ingress direction t1/e1 channel 18 10011 ingress direction t1/e1 channel 19 10100 ingress direction t1/e1 channel 20 10101 ingress direction t1/e1 channel 21 10110 ingress direction t1/e1 channel 22 10111 ingress direction t1/e1 channel 23 11000 ingress direction t1/e1 channel 24 11001 ingress direction t1/e1 channel 25 11010 ingress direction t1/e1 channel 26 11011 ingress direction t1/e1 channel 27 11100 ingress direction t1/e1 channel 28 11101 none 11110 the test channel 11111 test pattern - from vt pattern generator cross connect configuration ds1/e1 (c ross - c onnect ) c hannel s elect [4:0] r esulting i ngress d irection t1/e1 c hannel being handled by this particular t ransmit vt-m apper block c omments
XRT86SH328 preliminary 306 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit[7:4] - rdi-v accepted value[3:0]: these read-only bit-fields reflect the most recently val ue for rdi-v that has been accepted (or validated) by the vtde--mapper block. the vt-de--mapper block will accept (or validate) a given rdi-v value, once it has received this same rdi-v value, within rdi-v_accept_threshold[3:0] number of consecutive, in coming vt multi-frames. n otes : 1. these bit-fields are only active if the user has configured the receive vt-de-mapper block to support erdi-v (enhanced rdi-v). 2. these bit-fields reflect the four-bit rdi-v value that the vt de-mapper block has accepted via the k4 bytes within the incoming vt/tu data-stream. bit[3:0] - rdi-v accept threshold[3:0]: these read/write bit-fields are used to define the rdi-v validation criteria for the vt-de-mapper block. more specifically, these bit-fields are used to specify the number of consecutive, inco ming vt multi-frame, in which the vt- de-mapper block must receive a given rdi-v value before it validates it and loads it in to bit[7:4] (rdi-v accepted value[3:0]). bit[7:1] - unused: bit 0 - rdi-v type: this read/write bit-field is used to configure the vt-de-mapper blocks (associated with a given channel) to support either the srdi-v (single bit - rdi-v) or erdi-v (extended - rdi-v) form of signaling. if the user uses only single-bit rdi-v, then the rdi-v indicator will only be transported via bit 8 (rdi-v) within the v5 byte in a vt-data-stream. conversely, if a user uses extended rd i-v, then the rdi-v indicator will be tr ansported via both bits 8 (rdi-v) within the v5 byte, and bits 5, 6 and 7 within the z7/k4 byte. ` 0 - configures the vt-de- mapper blocks to use the s rdi-v form of signaling. ` 1 - configures the vt-de-mapper blocks to use the erdi-v form of signaling. n ote : this configuration setting only applies to the vt-de-mapper block. if the user wishes to configure the vt-mapper block to support either the "srdi-v" or the "erdi-v" form of signaling, t hen he/she must set bit 1 (rdi-v type) within the "channel control - vt-mapper block - ingress direc tion - transmit rdi-v control register - byte 0" to the appropriate state. t able 440: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - ds1/e1 d rop c ontrol r egister - b yte 3 (a ddress = 0 x nd44, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdi-v accepted value[3:0] rdi-v accept threshold[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 441: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - ds1/e1 d rop c ontrol r egister - b yte 2 (a ddress = 0 x nd45, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused rdi-v type r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 307 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit7 -unused: bit6 - vt size errodefect declared: this read-only bit-field indicates whether or not the rece ive vt-de-mapper block is currently declaring the vt size error defect condition. the receive vt-de-mapper block wi ll declare the vt size error defect condition anytime it receives a vt data-stream with v1 bytes that contains the incorrect vt-size bit values, as depicted below. ` 0 - indicates that the receive vt-de-mapper block is not currently declaring the vt size error defect condition. ` 1 - indicates that the receive vt-de-mapper block is currently declaring the vt size error defect condition. bit 5 - lop-v defect declared: this read-only bit-field indicates whether or not the receive vt-mapper block is currently declaring the lop-v defect condition. ` 0 - indicates that the receive vt-de-mapper block is currently not declaring the lop-v defect condition. ` 1 - indicates that the receive vt-de-mapper block is currently declaring the lop-v defect condition bit 4 - change in vt label[2:0] indicator: this read/write 1 to clear bit-field indicates whether or not the receive vt-de-mapper block has detected a change in vt signal label, since the last time the user read and cleared this register bit 0 - indicates that the receive vt-de-mapper block has not det ected a change in vt signal label since the last time the user read and cleared this register bit. bit[3:1] - vt label value[2:0]: this read-only bit-field reflects the value of the most recently accepted (or validated) vt signal label value. bit 0 - ais-v defect declared: this read-only bit-field indicates whether or not the rece ive vt-de- mapper block is currently declaring the ais-v defect condition. ` 0 - indicates that the receive vt-de-mapper block is not currently declaring the ais-v defect condition. ` 1 - indicates that the receive vt-de-mapper block is currently declaring the ais-v defect condition. t able 442: c hannel c ontrol - vt-d e -m apper b lock - e ngress d irection - ds1/e1 d rop c ontrol r egister - b yte 1 (a ddress = 0 x nd46, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused vt size error defect declared lop-v defect declared change in vt label value[2:0] indicator vt label value[2:0] ais-v defect declared r/o r/o r/o r/w1c r/o r/o r/o r/o 0 0 1 0 0 0 0 0 t able 443: c hannel c ontrol - vt-d e -m apper b lock - e ngress d irection - ds1/e1 d rop c ontrol r egister - b yt e 0 (a ddress = 0 x nd47, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rfi-v defect declared rdi-v defect declared force ds1/e1 ais in egress direction ds1/e1 cross connect channel select_egress direction[4:0] r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 308 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit7 - rfi-v defect declared: this read/write bit-field indicates whether or not the re ceive vt-de-mapper block is currently declaring the rfi-v defect condition. ` 0 - indicates that the receive vt-de-mapper block is not currently declaring the rfi-v defect condition. ` 1 - indicates that the receive vt-de-mapper block is currently declaring the rfi-v defect condition. bit6 - rdi-v defect declared: this read/write bit-field indicates whether or not the re ceive vt-de-mapper block is currently declaring the rdi-v defect condition. ` 0 - indicates that the receive vt-de-mapper block is not currently declaring the rdi-v defect condition. ` 1 - indicates that the receive vt-de-mapper block is currently declaring the rdi-v defect condition. bit 5 - force ds1/e1 ais in egress direction this read/write bit-field is used to configure this particu lar receive vt-de-mapper block to transmit the ds1/e1 ais indicator within the egress direction of this particular ds1/e1 channel. ` 0 - configures the receive vt-de-mapper block to not tr ansmit the ds1/e1 ais pattern within the egress direction corresponding to this particular channel. ` 1 - configures the receive vt-de-mapper block to transm it the ds1/e1 ais pattern within the egress direction corresponding to this particular channel. figure 21 presents an illustration of the functional block dia gram of the XRT86SH328, wh enever the vt-de-mapper block has been configured to overwrite the contents within the corresponding ds1/e1 channel with the ds1/e1 ais pattern (as it is being de-mapped from the vt1.5 or vt2 data-stream by the vt de-mapper block. f igure 21. a n i llustration of the f unctional b lock d iagram of the XRT86SH328, whenever the vt- d e -m apper block ( associated with a given channel ) overwrites the contents of a de - mapped ds1/e1 signal with the ds1/e1 ais p attern sts-1/ sts-3 telecom bus interface sts-1/ sts-3 telecom bus interface transmit sts-1/3 toh processor block transmit sts-1/3 toh processor block receive sts-1/3 toh processor block receive sts-1/3 toh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block receive sts-1 poh processor block receive sts-1 poh processor block vt/tu de-mapper block receive ds3 framer block receive ds3 framer block transmit ds3 framer block transmit ds3 framer block m23 mux block m23 mux block m23 de-mux block m23 de-mux block ingress direction receive ds1/e1 framer block egress direction receive ds1/e1 framer block ingress direction transmit ds1/e1 framer block egress direction transmit ds1/e1 framer block receive ds1/e1 liu block transmit ds1/e1 liu block ds3/ sts-1 liu interface ds3/ sts-1 liu interface m12 mux block m12 de-mux block ds1/e1 jitter atten block ds1/e1 channel 0 ds1/e1 channel 0 ds2 channel 0 from ds1/e1 channels 1 - 27 from ds2 channels 1 - 6 to ds2 channels 1 - 6 from ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 3 to ds1/e1 channels 1 - 27 vt/tu mapper block vt/tu mapper block ds2 channel 0 ds1/e1 ais
preliminary XRT86SH328 309 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit[4:0] - ds1/e1 cross connect ch annel select_egress direction[4:0]: these read/write bit-fields are used to configure the internal vt-cross connect. more specifically, these read/write bit-fields are used to select which (of the 28 egress direction) t1/e1 ports, that this particular receive vt-mapper block will route (or direct) its egress direction t1/e1 signal to. the following table presents the relationship between the sett ings of these bit-fields a nd the resulting cross-connect configuration. cross connect configuration ds1/e1 (c ross c onnect ) c hannel s elect [4:0] r esulting p ort that this r eceive vt-m apper block will direct its t1/e1 t raffic to c omments 00000 no clock or data is output via corresponding egress direction t1/e1 port 00001 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 1 00010 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 2 00011 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 3 00100 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 4 00101 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 5 00110 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 6 00111 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 7 01000 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 8 01001 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 9 01010 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 10 01011 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 11 01100 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 12 01101 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 13 01110 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 14 01111 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 15 10000 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 16
XRT86SH328 preliminary 310 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - 4 - vt payload po inter increment count[3:0]: these reset-upon-read bit-fields refl ect the number of vt payload pointer increment events that the receive vt- de-mapper block has detected since the last read of this register. the receive vt-mapper block will increment the contents within these bit-fields each time that it detects a vt payload pointer increment event within the incoming vt data-stream. 10001 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 17 10010 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 18 10011 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 19 10100 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 20 10101 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 21 10110 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 22 10111 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 23 11000 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 24 11001 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 25 11010 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 26 11011 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 27 11100 egress direction t1/e1 signal is routed to the egress direction output of t1/e1 channel 28 11101 11110 11111 t able 444: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - bip-2 e rror c ount r egister - b yte 1 (a ddress = 0 x nd4a, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt payload pointer increment count[3:0] bip-2 error count[11:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 cross connect configuration ds1/e1 (c ross c onnect ) c hannel s elect [4:0] r esulting p ort that this r eceive vt-m apper block will direct its t1/e1 t raffic to c omments
preliminary XRT86SH328 311 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications n ote : the user must induce a "0 to 1 transition" within bit 3 (latch count) within the "global vt-mapper block - vt mapper block control register (address = 0x0c03) prior to reading out the contents within these bit-fields. bit[3:0] - bip-2 error count[11:8]: these reset-upon-read bit-fields, alo ng with those within the vt mapper blo ck - egress direction - bip-2 error count register - byte 0, presents a 12-b it expression that reflects the number of bip-2 errors that the receive vt- mapper block has detected (within the incoming vt-dat a-stream) since the last read of this register. these particular bit-fields are the four most si gnificant bit-fields within this 12-bit expression. n ote : the user must induce a "0 to 1 transition" within bit 3 (latch count) within the "global vt-mapper block - vt de- mapper block control register (address = 0x0c03) prio r to reading out the contents within these bit-fields bit [7:0] - bip-2 error count[7:0]: these reset-upon-read bit-fields, alo ng with those within the vt mapper blo ck - egress direction - bip-2 error count register - byte 1, presents a 12-bi t expression that refl ects the number of bip-2 errors that the receive vt-de- mapper block has detected (within the incoming vt-dat a-stream) since the last read of this register. these particular bit-fields are the eight least sign ificant bit-fields within this 12-bit expression. n ote : the user must induce a "0 to 1 transition" within bit 3 (latch count) within the "global vt-mapper block - vt mapper block control register (address = 0x0c03) prior to reading out the contents within these bit-fields. bit [7:4] - vt payload poin ter decrement count[3:0]: these reset-upon-read bit-fields reflect the number of vt payload pointer decrement events that the receive vt- de-mapper block has detected since the last read of this register. the receive vt-mapper block will increment the contents within these bit-fields each time that it detects a vt payload pointer decrement event within the incoming vt data-stream. n ote : the user must induce a "0 to 1 transition" within bit 3 (latch count) within the "global vt-mapper block - vt mapper block control register (address = 0x0c03) prio r to reading out the contents within these bit-fields bit [3:0] - rei-v event count[11:8]: these reset-upon-read bit-fields, alo ng with those within the vt mapper blo ck - egress direction - rei-v event count register - byte 0, presents a 12-b it expression that reflects the number of rei-v events that the receive vt- mapper block has detected (within the incoming vt-dat a-stream) since the last read of this register. these particular bit-fields are the four most si gnificant bit-fields within this 12-bit expression. n ote : the user must induce a "0 to 1 transition" within bit 3 (latch count) within the "global vt-mapper block - vt mapper block control register (address = 0x0c03) prior to reading out the contents within these bit-fields. t able 445: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - bip-2 e rror c ount r egister - b yte 0 (a ddress = 0 x nd4b, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bip-2 error count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 446: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - rei-v e vent c ount r egister - b yte 1 (a ddress = 0 x nd4e, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vt-payload pointer decrement count[3:0] rei-v event count[11:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 312 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit[7:0] - rei-v event count[7:0]: these reset-upon-read bit-fields, alo ng with those within the vt mapper blo ck - egress direction - rei-v event count register - byte 1, presents a 12-b it expression that reflects the number of rei-v events that the receive vt-de- mapper block has detected (within the incoming vt-dat a-stream) since the last read of this register. these particular bit-fields are the eight least sign ificant bit-fields within this 12-bit expression. n ote : the user must induce a "0 to 1 transition" within bit 3 (latch count) within the "global vt-mapper block - vt mapper block control register (address = 0x0c03) prior to reading out the contents within these bit-fields. bit 7 - 4 - unused: this read/wtc bit-field indicates whether or not the ch ange of receive aps value event has occurred (within this tributary) since the last time that the user has written a 1 to clear this bit-field. the receive vt-de-mapper block will declare the change of receive aps value whenever it has acce pted a new value from the k4 bytes within the incoming vt data-stream. ` 0 - indicates that the change of receive aps value event ha s not occurred since the last time the user has written a 1 to clear this bit-field. ` 1 - indicates that the change of receiv e aps value event has occurred since the last time the user has written a 1 to clear this bit-field. bit 3 - 0 - receive aps value[3:0]: these four (4) read-only bit-field reflects the aps valu e that the vt-de-mapper block has received (via bits 1 through 4, within the k4 byte) and has validated. bit 7 - change of ds1/e1 ais defect condition - event mask: this read/write bit-field permits the user to either enabl e or disable the "change of ds1/e1 ais defect condition" event to/from causing the "change of ds1/e1 ais defect condit ion" interrupt to be generated. if the user enables this t able 447: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - rei-v e vent c ount r egister - b yte 0 (a ddress = 0 x nd4f, where n ranges in value from 0 x 01 to 0 x 1c) bit7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rei-v event count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 t able 448: c hannel c ontrol - vt-m apper b lock - e gress d irection - r eceive aps r egister - b yte 0 (a ddress = 0 x nd53, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive aps value[3:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 449: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit aps r egister - b yte 2 (a ddress = 0 x nd56, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ds1/e1 ais - event mask ds1/e1 loc -event mask reserved transmit elastic store overflow reserved r/w r/o r/o r/o rur r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 313 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications feature, then the vt-mapper block will a ssert the "change of ds1/e1 ais defect condition" interrupt in response to either of the following conditions. ? whenever the vt-mapper block declares the "ds1/e1 ais" defect condition within the ingress direction ds1/e1 data-stream. ? whenever the vt-mapper block clears the "ds1/e1 ais" def ect condition within the ingress direction ds1/e1 data stream. ` 0 - configures the vt-mapper block to not generate the "change of ds1/ e1 ais defect condition" interrupt, whenever it declares or clears the ds1/e1 ais defect condition. ` 1 - configures the vt-mapper block to generate the "change of ds1/e1 ais defe ct condition" interrupt, whenever it declares or clears the "ds1 /e1 ais defect condition. bit 6 - 4 reserved: bit 3 - transmit elastic store overflow: this reset-upon-read bit-field indicate s whether or not the vt ma pper block has declared a "transmit elastic store overflow" event since the last read of this register. the vt-mapper block will declare a "transmit elastic store overflow" event anytime that the "trans mit fifo" (within the vt-mapper block) has experience an "overflow" event. ` 0 - indicates that the "transmit elastic store overflow" ev ent has not occurred since the last read of this register. ` 1 - indicates that the "transmit elastic store overflow" event has occurred since the la st read of this register. n ote : the vt-mapper block will typically handle "small timing offsets" (between the ingress direction t1/e1 signal and the "transmit direction" 19.44mhz or 51.84mhz clock signal via bit-stuffing (as it maps this t1/e1 data into vts. however, if this bit-field is set to "1", this is typicall y a indication of a significant clock frequency accuracy problem within the system. bit 0 - reserved: bit 7 - unused: bit 6 - 4 - transmit erdi-v[2:0] these three (3) read/write bit-fields permit the user to exer cise software control over th e value of the "erdi-v" bits that are transported via "bits 5 th rough 7" (within the k4 byte) wit hin the outbound vt data-stream. n ote : this bit-field is only active if both of the following is true. a. the user has configured vt-mapper/de-mapper blocks to support the erdi-v (e xtended - rdi-v) form of signaling and, b. the user has set bit 6 (transmit rdi-v value) withi n the "channel control - vt mapper block - ingress direction - ds1/e1 insertion control register - 0" to "1". bit 3 - 0 - transmit aps value[3:0] these four (4) read/write bit-fields permit the user to exer cise software control over the value of the "aps" bits that are transported via bits 1 through 4 (within the k4 byte) within the outbound vt data-stream t able 450: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit aps/k4 r egister (a ddress = 0 x nd57, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txerdi ] txaps[3:0 r/w r/w r/w r/w r/o r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 314 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - 3 - unused: bit 2 - tim-v defect declared: this read-only bit-field indicates whether or not the vt-de-mapper block is currently declaring the "vt trace identification mismatch" (t im-v) defect condition. the vt-de-mapper block will declare the tim-v defect conditio n, when none of the received 1, 16 or 64-byte string (received via the j2 byte, within the incoming vt-data-st ream) matches the expected 1, 16 or 64 byte message. the vt-de-mapper block will clear the "tim-v" defect condit ion, when 80% of the received 1, 16 or 64 byte string (received via the j2 byte) matches the 1, 16 or 64 byte message. ` 0 - indicates that the vt-de-mapper block is no t currently declaring the tim-v defect condition. ` 1 - indicates that the vt-de-mapper block is currently declaring the tim-v defect condition. bit 1 - vt path trace message unstable defect declared: this read-only bit-field indicates whether or not the vt-d e-mapper block is currently declaring the "vt path trace message unstable" defect condition. the vt-de-mapper block will declare the "vt path trace message unstable" defect condition, whenever the "vt path trace message unstable" counter reache s the value "8". the vt-de-mapper block will increment the "vt path trace message unstable" co unter for each time that it receives a "vt path trace message" that differs from the previous ly received message. the "vt path trace message unstable" counter is cleared to "0" whenever the vt-de-mapper block has received a give n "vt path trace message" 3 (or 5) consecutive times. ` 0 - indicates that the vt-de-mapper block is not currentl y declaring the "vt:path trace message unstable" defect condition. ` 1 - indicates that the vt de-mapper block is current ly declaring the "vt path trace message unstable" defect condition. n ote : the vt-de-mapper block will also set this bit-field "0" anyti me it receives a given "vt path trace message" 3 (or 5) consecutive times. bit 0 - unused: bits 7 - 2: unused: bit 1 - change of receive aps value interrupt: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "change of t able 451: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - j2 b yte s tatus r egister (a ddress = 0 x nd63, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused tim-v defect declared vt path trace message unstable defect declared unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 t able 452: c hannel c ontrol - vt-m apper b lock - e gress d irection - c omposite s tatus r egister - b yte 0 (a ddress = 0 x nd64, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of receive aps value - composite elastic store overflow event - composite r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0
preliminary XRT86SH328 315 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications receive aps value" interrupt since the last read of this register. the vt-de-mapper blo ck will generate this interrupt whenever it has "accepted" a new "aps" value (from the k4 bytes wit hin the incoming vt-data-stream). ` 0 - indicates that the "change of receive aps value" in terrupt has not occurred since t he last read of this register. ` 1 - indicates that the "change of receive aps value" interrupt has occurred since the last read of this register. bit 0 - transmit or receive elastic store overflow event interrupt: this reset-upon-read bit-field indicates whether or no t the "vt mapper/vt-de-mapper " block has generated the "elastic store overflow event" interrupt since the last read of this regist er. the vt-mapper/de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the "transmit fifo" within the vt-map per block, experiences an overflow event. ? whenever the "receive fifo" within the vt-de- mapper block, experiences an overflow event. ` 0 - indicates that the channel has not ge nerated an "elastic store overflow" in terrupt since the last read of this register. ` 1 - indicates that the channel has generated an "elastic store overflow" interrupt since the last read of this register. bit 7 - vt size erro r interrupt status: this reset-upon-read bit-field indicates whether or not th e "vt-de-mapper" block has generated the "vt size error" interrupt since the last read of this register. the vt-de-ma pper block will generate the "vt size error" interrupt anytime it declares the "vt size error" defect condition. ` 0 - indicates that the vt size e rror interrupt has not o ccurred since the last read of this register. ` 1 - indicates that the vt size e rror interrupt has occurre d since the last read of this register. bit 6 - change of lop-v defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "change of lop-v defect condition" interrupt sinc e the last read of this register. th e vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block de clares the lop-v defect condition ? whenever the vt-de-mapper block cl ears the lop-v defect condition. ` 0 - indicates that the "change of lop- v defect condition" interrupt has not occurred since the last read of this register. ` 1 - indicates that the "change of lop-v defect condition" in terrupt has occurred since the la st read of this register. bit 5 - change of rfi-v defect condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "change of rfi-v defect condition" interrupt since the last read of this register. the vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the rfi-v defect condition ? whenever the vt-de-mapper block cl ears the rfi-v defect condition. ` 0 - indicates that the "change of rfi-v defect condition" interrupt has not occurred since the last read of this t able 453: c hannel c ontrol - vt-m apper b lock - e gress d irection - c omposite s tatus r egister - b yte 0 (a ddress = 0 x nd65, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 vt size error interrupt status change of lop-v defect condition interrupt status change of rfi-v defect condition interrupt status change of rdi-v defect condition interrupt status change of ais-v fail - ure condition interrupt status change of ais-v defect condition interrupt status change of vt label interrupt status change of ds1/e1 ais defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 316 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 register. ` 1 - indicates that the "change of rfi-v defect condition" in terrupt has occurred since the last read of this register. bit 4 - change of rdi-v defe ct condition interrupt status this reset-upon-read bit-field in dicates whether or not the "vt-de -mapper" block has generated the "change of rdi-v defect condition" in terrupt since the last re ad of this register. the vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block de clares the rdi-v defect condition ? whenever the vt-de-mapper block cl ears the rdi-v defect condition. ` 0 - indicates that the "change of rdi-v defect condition" interrupt has not occurred since the last read of this register. ` 1 - indicates that the "change of rdi-v defect condition" interrupt has occurred since the last read of this register. bit 3 - change of ais-v failure condition interrupt status this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "change of ais-v failure condition" interrupt since the last read of this register. the vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the ais-v failure condition ? whenever the vt-de-mapper block clears the ais-v failure condition. ` 0 - indicates that the "change of ais-v failure condition" interrupt has not occurred since the last read of this register. ` 1 - indicates that the "change of ais-v failure condition" in terrupt has occurred since the last read of this register. bit 2 - change of ais-v defe ct condition interrupt status this reset-upon-read bit-field in dicates whether or not the "vt-de -mapper" block has generated the "change of ais-v defect condition" in terrupt since the last read of this register. the vt-d e-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block de clares the ais-v defect condition ? whenever the vt-de-mapper block clears the ais-v defect condition. 0 - indicates that the "change of ais- v defect condition" interrupt has not oc curred since the last read of this register. 1 - indicates that the "change of ais-v defect condition" interrupt has occurred since the last read of this register. bit 1 - change of vt label value interrupt status this reset-upon-read bit-field indicates whether or not the "change of vt label value" inte rrupt has occurred since the last read of this register. the vt-de-mapper block will generate this interrupt anytime it has "accepted" a new vt label value (that it has received via the v5 byte within the incoming vt data-stream). ` 0 - indicates that the "change of vt label value" interrup t has not occurred since the last read of this register. ` 1 - indicates that the "change of vt label value" interr upt has occurred since the last read of this register. bit 0 - change of ds1/e1 ais de fect condition interrupt status this reset-upon-read bit-field indi cates whether or not the "change of ds1/e1 ais defect condition" interrupt has occurred since the last re ad of this register. the vt-mapper block will generate th is interrupt in response to any one of the following conditions. ? whenever the vt-mapper block declares the ds1/e1 ais defect (with the ingress direction t1/e1 traffic). ? whenever the vt-mapper block clears the ds1/e1 ais defect (within the ingress direction t1/e1 traffic) ` 0 - indicates that the "change of ds1/e1 ais defect condition" interrupt has not occurred since the last read of this register. ` 1 - indicates that the "change of ds1/ e1 ais defect condition" interrupt has occurred since the last read of this register.
preliminary XRT86SH328 317 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bits 7 - 6 - unused: bit 5 - change of vt path trace message un stable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the "change of vt path trace message unstable defect condition" interrupt has occurred since the last read of this register. the vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever the vt-de-mapper block declares the "v t path trace message unstable" defect condition. ? whenever the vt de-mapper block clears the "vt path trace message unstable" defect condition. ` 0 - indicates that the "change of vt path trace message unstable defect condition" interrupt has not occurred since the last read of this register. ` 1 - indicates that the "change of vt path trace message unstable defect condition" interrupt has occurred since the last read of this register. bit 4 - new vt path trace message interrupt status: this reset-upon-read bit-field indicates whether or not the "new vt path trace message" interrupt has occurred since the last read of this re gister. the vt-de-mapper block will generate this interrupt whenever it has "accepted" a new "vt path trace message" via the incoming vt-data-stream. ` 0 - indicates that the "new vt path trace message" interr upt has not occurred since the la st read of this register. ` 1 - indicates that the "new vt path trace message" inte rrupt has occurred since the last read of this register. bit 3 - change of tim-v defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the "vt-de-mapper" block has generated the "change of tim-v defect condition" interrupt sinc e the last read of this register. the vt-de-mapper block will generate this interrupt in response to either of the following conditions. ? whenever it declares the tim-v defect condition. ? whenever it clears the tim-v defect condition. ` 0 - indicates that the "change of tim-v defect condition" interrupt has not occurred since the last read of this register. ` 1 - indicates that the "change of tim-v defect condition" interrupt has occurred since the last read of this register. bits 2 - 0 - unused: t able 454: c hannel c ontrol - vt-m apper b lock - e gress d irection - i nterrupt s tatus r egister (a ddress = 0 x nd67, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of vt path trace message unstable defect condition interrupt status new vt path trace message interrupt status change of tim-v defect condition interrupt status unused r/o r/o rur rur rur r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 318 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits 7 - 2: unused: bit 1 - change of receive aps value interrupt enable: this read/write bit-field permits the us er to either enable or disable the "change of receive aps value" interrupt. if the user enables this interrupt, then the vt-de-mapper bl ock will generate this interrupt anytime it has "accepted" a new aps value (via the k4 byte wit hin the incoming vt-data-stream). ` 0 - disables the "change of receive aps value" interrupt. ` 1 - enables the "change of receive aps value" interrupt. bit 0 - transmit or receive elastic store overflow event interrupt enable: this read/write bit-field permits the user to either enable or disable the "elastic store overflow event" interrupt. if the user enables this interrupt, then the channel will generate this interrupt in response to either of the following conditions. ? whenever the "transmit fifo" within the vt-map per block, experiences an overflow event. ? whenever the "receive fifo" within the vt-de- mapper block, experiences an overflow event. ` 0 - disables the "elastic store overflow event" interrupt ` 1 - enables the "elastic store overflow event" interrupt bit 7 - vt size error interrupt enable: this read/write bit-field permits the user to either enable or disable the "vt size error" interrupt. if the user enables this interrupt, then the "vt-de-mapper" block will generate this interrupt anytime it declares the "vt size error" defect condition. ? 0 - disables the "vt size error" interrupt. ? 1 - enables the "vt size error" interrupt. bit 6 - change of lop-v defect condition interrupt enable this read/write bit-field permits the user to either enable or disable the "change of lop-v defect condition" t able 455: c hannel c ontrol - vt-m apper b lock - e gress d irection - i nterrupt e nable r egister (a ddress = 0 x nd68, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of receive aps value interrupt enable elastic store overflow event interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 t able 456: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - i nterrupt e nable r egister (a ddress = 0 x nd69, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 vt size error interrupt enable change of lop-v defect condition i nterrupt enable change of rfi-v defect condition interrupt enable change of rdi-v defect condition interrupt enable change of ais-v failure condition interrupt enable change of ais-v defect condition interrupt enable change of vt label interrupt enable change of ds1/e1 ais defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 319 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications interrupt. if the user enables this in terrupt, then the "vt-de-mapper" block will generate this interrupt in response to either of the following conditions. ? whenever it declares the lop-v defect condition ? whenever it clears the lop-v defect condition ` 0 - disables the "change of lop-v defect condition" interrupt ` 1 - enables the "change of lop- v defect condition" interrupt bit 5 - change of rfi-v defect condition interrupt enable this read/write bit-field permits the user to either enable or disable the "change of rfi-v defect condition" interrupt. if the user enables this in terrupt, then the "vt-de-mapper" block will generate this interrupt in response to either of the following conditions. ? whenever it declares the rfi-v defect condition ? whenever it clears the rfi-v defect condition ` 0 - disables the "change of rfi-v defect condition" interrupt ` 1 - enables the "change of rfi-v defect condition" interrupt bit 4 - change of rdi-v defe ct condition interrupt enable this read/write bit-field permits the user to either enable or disable the "change of rdi-v defect condition" interrupt. if the user enables this in terrupt, then the "vt-de-mapper" block will generate this interrupt in response to either of the following conditions. ? whenever it declares the rdi-v defect condition ? whenever it clears the rdi-v defect condition ` 0 - disables the "change of rdi-v defect condition" interrupt ` 1 - enables the "change of rdi-v defect condition" interrupt bit 3 - change of ais-v failure condition interrupt enable this read/write bit-field permits the user to either enable or disable the "change of ais-v failure condition" interrupt. if the user enables this in terrupt, then the "vt-de-mapper" block will generate this interrupt in response to either of the following conditions. ? whenever it declares the ais-v failure condition ? whenever it clears the ais-v failure condition ` 0 - disables the "change of ais-v failure condition" interrupt ` 1 - enables the "change of ais-v failure condition" interrupt bit 2 - change of ais-v defe ct condition interrupt enable this read/write bit-field permits the user to either enable or disable the "change of ais-v defect condition" interrupt. if the user enables this in terrupt, then the "vt-de-mapper" block will generate this interrupt in response to either of the following conditions. ? whenever it declares the ais-v defect condition ? whenever it clears the ais-v defect condition ` 0 - disables the "change of ais-v defect condition" interrupt ` 1 - enables the "change of ais-v defect condition" interrupt bit 1 - change of vt label value interrupt enable this read/write bit-field permits the user to either enable or disable the "change of vt label value" interrupt. if the user enables this interrupt, then the "vt-de-mapper" block will generate this interrupt anytime it has "accepted" a new "vt label value" via the v5 bytes within the incoming vt-data-stream. ` 0 - disables the "change of vt label value" interrupt. ` 1 - enables the "change of vt label value" interrupt. bit 0 - change of ds1/e1 ais de fect condition interrupt enable this read/write bit-field permits the user to either enabl e or disable the "change of ds 1/e1 ais defect condition" interrupt. if the user enables this interrupt, then the "vt-ma pper" block will generate this interrupt in response to either
XRT86SH328 preliminary 320 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 of the following events. ? whenever it declares the ds1/e1 ais defect condition. ? whenever it clears the ds 1/e1 ais defect condition ` 0 - disables the "change of ds1/e1 ais defect condition" interrupt. ` 1 - enables the "change of ds1/e1 ais defect condition" interrupt. bits 7 - 6 - unused: bit 5 - change of vt path trace message unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the "change of vt path trace message unstable defect condition" interrupt. if the user enables this interrupt, then the vt-de-mapper block will generate this interrupt in response to either of the following events. ? whenever the vt-de-mapper block declares the "vt-path trace message unstable" defect condition. ? whenever the vt-de-mapper block clears the "vt- path trace message unstable" defect condition. ` 0 - disables the "change of vt path trace message unstable defect condition" interrupt. ` 1 - enables the "change of vt path trace message unstable defect condition" interrupt. bit 4 - new vt path trace message interrupt enable: this read/write bit-field permits the user to either enable or disable the "new vt path trace message" interrupt. if the user enables this interrupt, then the vt-de-mapper blo ck will generate this interrupt whenever it has "accepted" a new "vt path trace message" via the incoming vt-data-stream. ` 0 - disables the "new vt path trace message" interrupt. ` 1 - enables the "new vt path trace message" interrupt bit 3 - change of tim-v defect condition interrupt enable: this read/write bit-field permits the user to eith er enable or disable the "change of tim-v defect condition" interr upt. if the user enables this in terrupt, then the vt-d e-mapper block will gene rate this interrupt in response to either of the following events. ? whenever it declares the tim-v defect condition ? whenever it clears the tim-v defect condition ` 0 - disables the "change of tim-v defect condition" interrupt ` 1 - enables the "change of tim-v defect condition" interrupt bits 2 - 0 - unused: t able 457: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - i nterrupt e nable r egister (a ddress = 0 x nd6b, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of vt path trace message unstable defect condition interrupt enable new vt path trace message interrupt status change of tim-v defect condition interrupt status unused r/o r/o rur rur rur r/o r/o r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 321 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bit 7 - 6 - reserved for normal operation, please set these two bit-fields to "0". bit 5 - unused bit 4 - receive vt path trace message buffer select: this read/write bit-field permits a user to specify which of the following "receive vt path trace message" buffer segments that the microprocessor will read out whenever it re ads out the contents of the receive path trace message buffer. a. the "actual" receive vt path trace message buffer. the "actual" receive vt path trace message buffer contains the contents of the most re cently received (and accepted) vt path trace messages via the incoming vt-data-stream. b. the "expected" receive vt path trace message buffer. the "expected" receive path trace message buffer contains the contents of the "vt path trace messa ge" that the user "expects" to receive. the contents of this particular buffer are usually specified by the user. ` 0 - configures the chip to return th e contents of the "actual" receive vt pa th trace message" buffer, whenever the user executes a read to the "receive vt path trace message" buffer. ` 1 - configures the chip to return the contents of the "e xpected" receive vt path trace message" buffer, whenever the user executes a read to the "rec eive vt path trace message" buffer. bit 3 - receive vt path trace message accept threshold this read/write bit-field permits a user to select the number of consecutive times that the "vt-de-mapper" block must receive a given "vt path trace message" before it is "validated" and loaded into the "actual" receive vt path trace message buffer, as described below. ` 0 - configures the vt-de-mapper block to "validate" the inco ming vt path trace message after it has received it the third time in succession. ` 1 - configures the vt-de-mapper block to "validate" the inco ming vt path trace message after it has received it the fifth time in succession. bit 2 - receive vt path trace message type this read/write bit-field permits the user to specif y how the "vt-de-mapper" bloc k will locate the boundary of the incoming vt path trace message (within the incoming vt-data-stream) as depicted below. ` 0 - configures the vt-de-mapper block to expect the "v t path trace message" boundary to be denoted by a "line feed" character. ` 1 - configures the vt-de-mapper block to except the "vt path trace message" boundary to be denoted by the presence of a "1" in the "msb" (most signifi cant bit) of the first byte (within the incoming vt path trace message). in this case, all of the remaining bytes (within the incoming vt path trace message) will each have a "0" within their msbs. bits 1 - 0 - vt path trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the "receive vt path trace message that the "vt-de-mapper" block will accept and load into the "actual" receive vt path trace message buffer. the relationship between the contents of these bit-fields and the corresponding "receive vt pa th trace message" length is presented t able 458: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - vt-p ath t race b uffer c ontrol r egister (a ddress = 0 x nd71, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved unused receive vt path trace message buffer select vt path trace message accept threshold vt path trace message type vt path trace message length[1:0] r/w r/w rur rur rur r/o r/o r/o 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 322 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 below. bits 7 - 6 - unused: bit 5 - auto transmit ais-v upon ais-v defect: this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator via the "egress direction" traffic (e.g., towards t he transmit t1/e1 liu block), anytime (and for the duration that) it declares the ais-v defect condit ion within the incoming vt-data-stream. ` 0 - does not configure the vt-de-mapper block to automati cally transmit the ais-v indicator (via the "downstream" traffic) whenever it declares the ais-v defect condition. ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream" traffic) whenever it declares the ais-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v en able) within the "channel control - vt-de-mapper block - egress direction - receive vt auto ais control" register to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in response to this defect condition. bit 4 - auto transmit ais-v upon uneq-v defect: this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator via the "egress direction" traffic (e.g., towards t he transmit t1/e1 liu block), anytime (and for the duration that) it declares the uneq-v defect condit ion within the incoming vt-data-stream. ` 0 - does not configure the vt-de-mapper block to automati cally transmit the ais-v indicator (via the "downstream" traffic) whenever it declares the uneq-v defect condition. ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream" traffic) whenever it declares t he uneq-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v en able) within the "channel control - vt-de-mapper block - egress direction - receive vt auto ais control" register to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in response to this defect condition. bit 3 - unused: bit 2 - auto transmit ais-v upon lop-v defect: this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator via the "egress direction" traffic (e.g., towards t he transmit t1/e1 liu block), anytime (and for the duration that) it declares the lop-v defect condition within the incoming vt-data-stream. ` 0 - does not configure the vt-de-mapper block to automati cally transmit the ais-v indicator (via the "downstream" traffic) whenever it declar es the lop-v defect condition. vt p ath t race m essage l ength [1:0] r esulting vt p ath t race m essage l ength (b ytes ) 00 1 01 16 1x 64 t able 459: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - a uto ais c ontrol r egister - b yte 1 (a ddress = 0 x nd72, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused auto trans - mit ais-v upon ais-v defect auto trans - mit ais-v upon uneq- v defect unused auto trans - mit ais-v upon lop-v defect auto trans - mit ais-v upon plm-v defect unused r/o r/o r/w r/w r/o r/w r/w r/o 0 0 0 0 0 0 0 0
preliminary XRT86SH328 323 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream" traffic) whenever it declares t he lop-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v en able) within the "channel control - vt-de-mapper block - egress direction - receive vt auto ais control" register to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in response to this defect condition. bit 1 - auto transmit ais-v upon plm-v defect: this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit t1/e1 liu block), anytime (and for the duration that) it declares the plm-v defect conditi on within the incoming vt-data-stream. ` 0 - does not configure the vt-de-mapper block to automati cally transmit the ais-v indicator (via the "downstream" traffic) whenever it declares the plm-v defect condition. ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream" traffic) whenever it declares the plm-v defect condition. n ote : the user must also set bit 0 (auto transmit ais-v en able) within the "channel control - vt-de-mapper block - egress direction - receive vt auto ais control" register to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in response to this defect condition. bit 0 - unused: bit 7 - auto transmit ais-v upon vt path trace message unstable defect: this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit t1/e1 liu block), anytime (and for the duration that) it declares the vt path trace message unstable defect condition within the incoming vt-data-stream. ` 0 - does not configure the vt-de-mapper block to automati cally transmit the ais-v indicator (via the "downstream" traffic) whenever it declares the vt path trace message unstable defect condition. ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream" traffic) whenever it declares the vt path trace message unstable defect condition. n ote : the user must also set bit 0 (auto transmit ais-v en able) within the "channel control - vt-de-mapper block - egress direction - receive vt auto ais control" register to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in response to this defect condition. bit 6 - auto transmit ais-v upon tim-v defect: this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator via the "egress direction" traffic (e.g., towards the transmit t1/e1 liu block), anytime (and for the duration that) it declares the tim-v defect conditi on within the incoming vt-data-stream. ` 0 - does not configure the vt-de-mapper block to automati cally transmit the ais-v indicator (via the "downstream" traffic) whenever it declares the tim-v defect condition. ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream" traffic) whenever it declares the tim-v defect condition. t able 460: c hannel c ontrol - vt-d e -m apper b lock - e gress d irection - a uto ais c ontrol r egister - b yte 0 (a ddress = 0 x nd73, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 auto transmit ais-v upon vt path trace message unstable defect auto transmit ais-v upon tim-v defect reserved (set to "[0, 0, 0, 0, 0]" for normal operation) auto transmit ais-v enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
XRT86SH328 preliminary 324 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 n ote : the user must also set bit 0 (auto transmit ais-v en able) within the "channel control - vt-de-mapper block - egress direction - receive vt auto ais control" register to "1" in order to configure the vt-de-mapper block to automatically transmit the ais-v indicator, in response to this defect condition. bits 5 - 1 - reserved: please set each of these bit-fields to "0" for normal operation. bit 0 - auto transmit ais-v enable this read/write bit-field permits the user to configure the vt-de-mapper block to automatically transmit the ais-v indicator (via the down-stream traffic) whenever (and for th e duration that) it declares eith er the ais-v, lop-v, tim-v, uneq-v, plm-v or "vt path trace message unstable" defect conditions. ` 0 - configures the vt-de-mapper block to not automatically transmit the ai s-v indicator (via the "downstream traffic) upon declaration of any of t he "above-mentioned" defect conditions. ` 1 - configures the vt-de-mapper block to automatically tran smit the ais-v indicator (via the "downstream traffic) upon declaration of any of the "abo ve-mentioned" defect conditions. n ote : the user must also set the corresponding bit-fields (withi n this register) to "1" in order to configure the vt-de- mapper block to automatically transmit the ais-v indica tor upon detection of a given alarm/defect condition. bits 7 - 0 - transmit j2 byte value[7:0]: these read/write bit-fields permit the user to have softwa re control over the value of the j2 byte, within the outbound vt data-stream. if the user configures the vt-m apper block to use this register as the source of the j2 byte, then it will automatically write the contents of this register into the j2 byte location, within each "outbound" vt multi-frame. this feature is enabled wheneve r the user writes the value "[1, 0]" into bits 1 and 0 (transmit vt-path trace message source[1:0]) within the "channel control - vt mapper block - ingress direction - vt path trace message control" register. bits 7 - 0 - transmit n2 byte value[7:0]: these read/write bit-fields permit the user to have soft ware control over the value of the n2 byte, within the outbound vt data-stream. the vt-mapper block will (unc onditionally) use this regi ster as the source of the n2 byte, then it will automatically write the contents of th is register into the j2 byte location, within each "outbound" vt multi- frame. t able 461: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit j2 b yte v alue r egister (a ddress = 0 x nd76, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit j2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t able 462: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit n2 b yte v alue r egister (a ddress = 0 x nd77, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit n2 byte value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0
preliminary XRT86SH328 325 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications bits 7 - 6 - reserved: n ote : the user must set these two bits to "[0, 0]" for normal operation. bit 5 - txais: bit 4 - unused: bits 3 - 2 - transmit vt path trace message length[1:0]: these read/write bit-fields permit the user to specify th e length of the vt path trac e message that the vt-mapper block will repeatedly transmit to the remote vt pte. the re lationship between the contents of these bit-fields and the corresponding vt path trace message length is presented below. bits 1 - 0 - transmit vt path trace message source[1:0]: these read/write bit-fields permit the user to specify the source of the "outbound" vt path trace message that will transported via the j2 by te channel (within t he outbound vt-data-str eam) as depicted below. t able 463: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit vt-p ath t race m essage c ontrol r egister (a ddress = 0 x nd79, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved unused transmit vt path trace message length[1:0] transmit vt path trace message source[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 t ransmit vt p ath t race m essage l ength [1:0] r esulting vt p ath t race m essage l ength ( in terms of bytes ) 00 1 byte 01 16 bytes 1x 64 bytes t ransmit vt p ath t race m essage s ource [1:0] r esulting s ource of the vt p ath t race m essage 00 fixed value:the vt-mapper block will automatic ally set the j2 byte, within the each out - bound vt-multi-frame to the value "0x01". 01 the transmit vt path trace message buffer :the vt-mapper block will read out the con - tents within the "transmit vt-path trace message " buffer, and will transmit this message to the remote vt pte. 10 from the "transmit j2 byte value[7:0]" regist er:in this setting, the vt-mapper block will read out the contents of the "transmit j2 byte value register, and will insert this value into the j2 byte-position within each outbound vt-multi-frame. 11 do not use
XRT86SH328 preliminary 326 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bits 7 - 4 - unused: bits 3- 1 - plm-v rdi code[2:0]: these three read/write bit-field permits the user to spec ify the value that the vt-map per block will transmit, within the rdi-v bit-fields of the k4 byte (within each outb ound vt-frame) whenever (and for the duration that) the corresponding vt-de-mapper block detects and declare the plm-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon plm-v) within this register to "1". bit 0 - transmit rdi-v upon plm-v this read/write bit-field permits the user to configure t he vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this register) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the plm-v defect condition. ` 0 - configures the vt-mapper block to not automatically tr ansmit the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-map per block declares the plm-v defect condition. ` 1 - configures the vt-mapper block to automatically transmi t the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-mapper block declares the plm-v defect condition. bits 7 - 5 - tim-v rdi code[2:0]: these three read/write bit-field permits the user to spec ify the value that the vt-map per block will transmit, within the rdi-v bit-fields of the k4 byte (within each outb ound vt-frame) whenever (and for the duration that) the corresponding vt-de-mapper block detects and declare the tim-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon tim-v) within this register to "1". bit 4 - transmit rdi-v upon tim-v this read/write bit-field permits the user to configure t he vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this register) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the tim-v defect condition. ` 0 - configures the vt-mapper block to not automatically tr ansmit the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-map per block declares the tim-v defect condition. ` 1 - configures the vt-mapper block to automatically transmi t the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-mapper block declares the tim-v defect condition. bits 3 - 1 - uneq-v rdi code[2:0]: t able 464: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 3 (a ddress = 0 x nd84, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused plm-v rdi code[2:0] transmit rdi-v upon plm-v r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 0 0 t able 465: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 2 (a ddress = 0 x nd85, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-v rdi code[2:0] transmit rdi-v upon tim-v uneq-v rdi code[2:0] transmit rdi-v upon uneq-v r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 1 1 0 0
preliminary XRT86SH328 327 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications these three read/write bit-field permits the user to spec ify the value that the vt-map per block will transmit, within the rdi-v bit-fields of the k4 byte (within each outb ound vt-frame) whenever (and for the duration that) the corresponding vt-de-mapper block dete cts and declare the uneq-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon uneq-v) within this register to "1". bit 0 - transmit rdi-v upon uneq-v this read/write bit-field permits the user to configure t he vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this register) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the uneq-v defect condition. ` 0 - configures the vt-mapper block to not automatically tr ansmit the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-map per block declares the uneq-v defect condition. ` 1 - configures the vt-mapper block to automatically transmi t the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-mapper block declares the uneq-v defect condition. bits 7 - 5 - lop-v rdi code[2:0]: these three read/write bit-field permits the user to spec ify the value that the vt-map per block will transmit, within the rdi-v bit-fields of the k4 byte (within each outb ound vt-frame) whenever (and for the duration that) the corresponding vt-de-mapper block detect s and declare the lop-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon lop-v) within this register to "1". bit 4 - transmit rdi-v upon lop-v this read/write bit-field permits the user to configure t he vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this register) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the lop-v defect condition. ` 0 - configures the vt-mapper block to not automatically tr ansmit the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-map per block declares the lop-v defect condition. ` 1 - configures the vt-mapper block to automatically transmi t the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-mapper block declares the lop-v defect condition. bits 3 - 1 - ais-v rdi code[2:0]: these three read/write bit-field permits the user to spec ify the value that the vt-map per block will transmit, within the rdi-v bit-fields of the k4 byte (within each outb ound vt-frame) whenever (and for the duration that) the corresponding vt-de-mapper block detects and declare the ais-v defect condition. n ote : in order to enable this feature, the user must set bit 0 (transmit rdi-v upon ais-v) within this register to "1". bit 0 - transmit rdi-v upon ais-v this read/write bit-field permits the user to configure t he vt-mapper block to automatically transmit the rdi code (as configured in bits 3 through 1 - within this register) towards the remote vt pte whenever (and for the duration that) the corresponding vt-de-mapper block declares the ais-v defect condition. ` 0 - configures the vt-mapper block to not automatically tr ansmit the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-map per block declares the ais-v defect condition. ` 1 - configures the vt-mapper block to automatically transmi t the rdi code (via the k4 byte) whenever (and for the duration that) the corresponding vt-de-mapper block declares the ais-v defect condition. t able 466: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 1 (a ddress = 0 x nd86, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 lop-v rdi code[2:0] transmit rdi-v upon lop-v ais-v rdi code[2:0] transmit rdi-v upon ais-v r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
XRT86SH328 preliminary 328 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications rev. p1.0.6 bit 7 - rfi-v upon ds1/e1 rai enable: this read/write bit-field permits the user to configure the vt-mapper block to automatically transmit the rfi-v indicator (within the outbound vt-data-stream) whenever (and for the duration) that the corresponding ingress direction receive ds1/e1 framer block declares the rai defect condition. ` 0 - does not configure the vt-mapper block to automatically transmit the rf i-v indicator whenever (and for the duration) that the corresponding ingress direction receive ds1/e1 framer block declares the rai defect condition. ` 1 - configures the vt-mapper block to aut omatically transmit the rfi-v indicato r whenever (and for the duration) that the corresponding ingress direction receive ds1/e1 framer block declares the rai defect condition. bits 6 - 5 - unused: bits 4 - 2 - transit rdi-v value[2:0]: these three read/write bit-fields permits the user to s pecify the value that the vt-ma pper block will transmit, within the rdi-v bit-fields of the k4 byte (within each outbound vt-frame) regardless of any defects that the corresponding vt-de-mapper block is (or is not) currently declaring. n ote : the user must set bit 0 (rdi-v insert type) within this regi ster to "1" in order to configure the vt-mapper block to use these bit-fields as the "source" of the rdi-v value. bit 1 - rdi-v type this read/write bit-field permits the user to configure the vt-mapper block to either support the "srdi-v" (single- bit - rdi-v) or "erdi-v" (extended - rdi-v) form of signaling. if the user opts to use only "single-bit" rdi-v, then the rdi-v indicator will only be transported via bit 8 (rdi-v) within th e v5 byte in a vt-data-stream. conversely, if the user opts to use the "extended" rdi-v, then the rdi-v indicator will be transported via both bit 8 (rdi-v) within the v5 byte, and bits 5, 6 and 7 within the z7/k4 byte. ` 0 - configures the vt mapper block to use the srdi-v form of signaling. ` 1 - configures the vt-mapper block to use the erdi-v form of signaling. n ote : this configuration setting only applies to the vt-mapper bl ock. if the user wishes to configure the vt-de-mappe block to support either the "srdi-v" or the "erdi-v" form of signaling, t hen he/she must set bit 0 (rdi-v type) within the "channel control - vt-de-mapper block - egress direction - ds1/e1 drop control register - byte 2. bit 0 - rdi-v insert type: this read/write bit-field permits the us er to select the source of the rdi-v code word that the vt-mapper block will transmit within the outbound vt-data-stream, as depicted below. in this case, the user has two options. ? to configure the vt-mapper block to transmit the ap propriate rdi-v code (based upon defects that the corresponding vt-de-mapper block declares). in this ca se, the vt-mapper block will transmit the rdi-v codes, as configured in the "channel control - vt mapper block - ingr ess direction - transmit rdi-v control register - bytes 3 - 1" registers. ? to configure the vt-mapper block to use the value written in to the "transmit rdi-v value[2:0]" bit-fields within this register. ` 0 - configures the vt-mapper block to transmit the appropriate rdi-v code (bas ed upon defects that the corresponding vt-de-mapper block declares). ` 1 - configures the vt-mapper block to use the value written in to the "transmit rdi-v value[2:0]" bit-fields within this register. t able 467: c hannel c ontrol - vt-m apper b lock - i ngress d irection - t ransmit rdi-v c ontrol r egister - b yte 0 (a ddress = 0 x nd87, where n ranges in value from 0 x 01 to 0 x 1c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rfi-v upon ds1/e1 rai enable unused transmit rdi-v value[2:0] rdi-v type rdi-v insert type r/w r/w r/w r/w r/w r/w r/w r/w 1 0 1 0 1 0 1 0
329 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet january 2007. all effort hs been made to provide correct information in this data sheet, iif discrepencies are found or more information is required please contact exar application engineering at < ntapplications@exar.com > reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. preliminary XRT86SH328 rev. p1.0.6 28-channel ds1/e1 framer/liu with ds 3 mux & vt-mapper - sonet applications revisions d ate r ev # d escription 09/09/06 p1.0.0 initial issue of register information. 11/09/06 p1.0.5 made edits to register map. 1/17/07 p1.0.6 made edits to register map and register definitions.

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